V6207610 VID

REVISIONS
LTR
DESCRIPTION
A
Correct derating factor for case outline X in
section 1.3. Update boilerplate to current MILPRF-38535 requirements. - PHN
DATE
APPROVED
14-11-24
Thomas M. Hess
CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Phu H. Nguyen
Original date of drawing
YY-MM-DD
CHECKED BY
TITLE
Phu H. Nguyen
07-02-07
MICROCIRCUIT, LINEAR, DUAL-OUTPUT LOWDROPOUT VOLTAGE REGULATOR WITH
POWER-UP SEQUENCING FOR SPLIT-VOLTAGE
DSP SYSTEM, MONOLITHIC SILICON
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
.
CODE IDENT. NO.
DWG NO.
V62/07610
16236
A
PAGE
1
OF
10
5962-V009-15
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance dual-output low-dropout voltage regulator with
power-up sequencing for split-voltage DSP systems, with an extended operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/07610
01
X
E
Drawing
number
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s). 1/
Device
Generic
01
Output voltage
TPS70751-EP
Circuit function
1.8 V / 3.3 V
Dual-output low-dropout voltage regulator with
power-up sequencing for split-voltage DSP systems
1.2.2 Case outline(s). The case outline are as specified herein.
Outline letter
Number of pins
X
20
JEDEC PUB 95
Package style
JEDEC MO-153
Plastic small outline
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/07610
PAGE
2
1.3 Absolute maximum ratings.
1/
Input voltage range: 2/
(VIN1) .......................................................................................................... -0.3 V to +7.0 V
(VIN2) ......................................................................................................... -0.3 V to +7.0 V
Voltage range at EN ............................................................................................. -0.3 V to +7.0 V
Maximum output voltage:
VOUT1, VSENSE1 ........................................................................................... 5.5 V
VOUT2, VSENSE2 ........................................................................................... 5.5 V
Maximum RESET and PG1 voltage .................................................................... 7.0 V
Maximum MR1 , MR 2 , and SEQ voltage .............................................................
Peak output current ..............................................................................................
Continuous total power dissipation........................................................................
Operating virtual junction temperature range (TJ) .................................................
Storage temperature range (TSTG).........................................................................
ESD rating, (HBM) ................................................................................................
VIN1
Internally limited
See dissipation rating tables
-55C to +150C
-65C to +150C
2 kV
Dissipation Rating Table – Ambient Temperatures
Case
Air Flow
TA ≤ 25C
outline
(CFM)
Power rating
0
250
X 3/
Derating Factor
TA = 70C
TA = 85C
3.067 W
30.67 mW/C
1.687 W
1.227 W
4.115 W
41.15 mW/C
2.265 W
4.646 W
1.4 Recommended operating conditions.
Input voltage (VI) ...................................................................................................
Output current (IO):
Regulator 1 ...............................................................................................
Regulator 2 ...............................................................................................
Operating virtual junction temperature range (TJ) .................................................
+2.7 V to +6.0 V
4/
0 to 250 mA
0 to 125 mA
-55C to +125C
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2/ All voltage are tie to network ground.
3/ This parameter is measured with the recommended copper heat sink pattern on a four-layer PCB, 1-oz copper on 4-in x 4-in
ground layer. For more information, see manufacturer data..
4/ To calculate the minimum input voltage for maximum output current, use VI(min) = VO(max) + VDO(max load).
1/
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
3
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.5.3 Block diagrams. The block diagrams shall be as specified on figure 3.
3.5.4 Timing diagram. The timing diagram shall be as specified on figure 4.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Test conditions
2/
unless otherwise specified
1.8 V output
Min
2.7 V  VI  6.0 V, FB connected to VO,
TJ = 25C
Reference
voltage
Output voltage
3/ 4/
Limits
VO
3.3 V output
Quiescent current (GND current) for regulator
Max
1.22 Typ
2.8 V  VI  6.0 V, TJ = 25C
1.8 Typ
2.8 V  VI  6.0 V
4.3 V  VI  6.0 V, TJ = 25C
1.764
1.836
3.3 Typ
4.3 V  VI  6.0 V
3.234
V
3.366
A
190 Typ
TJ = 25C
230
1 and regulator 2, EN = 0 V 3/ 4/
Output voltage line regulation (VO/VO) for
regulator 1 and regulator 2
4/ 5/
Load regulation for VOUT1 and VOUT2
Unit
3/
Regulator 1
Output noise voltage
Regulator 2
Regulator 1
Output current limit
Regulator 2
Thermal shutdown junction temperature
Standby current
Regulator 1 and
regulator 2
PSRR Power supply ripple rejection
Vn
VO + 1 V  VI  6.0 V, TJ = 25C
VO + 1 V  VI  6.0 V
0.01%
0.1%
/V
TJ = 25C
BW = 300 Hz to 50 kHz,
CO = 33 F, TJ = 25C
VO = 0 V
1 Typ
mV
65 Typ
65 Typ
Vrms
2.1
1.1
A
C
A
150 Typ
EN = VI , TJ = 25C,
2
EN = VI
f = 1 kHz, CO = 33 F, TJ = 25C
6
II(standby)
60 Typ
dB
RESET
Minimum input voltage for valid RESET
I(RESET) = 300 A, V(RESET) ≤ 0.8 V
Trip threshold voltage
Hysteresis voltage
t(RESET)
VO deceasing
Measured at VO
tr(RESET)
Output low voltage
Leakage current
PG1
Minimum input voltage for valid PG1
Trip threshold voltage
Hysteresis voltage
tf(PG1)
Output low voltage
Leakage current
Rising edge deglitch
VI = 3.5 V, I(RERSET) = 1 mA
V(RERSET) = 6.0 V
1.3
RESET pulse duration
V
92%
98%
0.5% Typ
80
160
VO
VO
ms
30 Typ
μs
V
μA
0.4
1
IO(PG1) = 300 μA, V(PG1) ≤ 0.8 V
VO deceasing
Measured at VO
Falling edge deglitch
VI = 2.7 V, I(PG1) = 1 mA
V(PG1) = 6.0 V
1.3
92%
98%
0.5% Typ
30 Typ
0.4
1
V
VO
VO
μs
V
μA
EN
2
High level EN input voltage
Low level EN input voltage
-1
Input current ( EN )
V
0.7
V
1
μA
See notes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
SEQ
High level SEQ input voltage
Low level SEQ input voltage
SEQ pullup current source
MR1/MR2
High level MR1/MR2 input voltage
Low level MR1/MR2 input voltage
MR1/MR2 pullup current source
VOUT2
VOUT2 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
VOUT2 UV comparator – falling edge deglitch
Peak output current
Discharge transistor current
VOUT1
VOUT1 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
VOUT1 UV comparator – hysteresis
VOUT1 UV comparator – falling edge deglitch
Dropoutput voltage 6/
Peak output current
Discharge transistor current
UVLO threshold
1/
2/
3/
4/
5/
6/
Symbol
Test conditions
2/
unless otherwise specified
Limits
Min
Unit
Max
2
0.7
6 Typ
V
V
μA
0.7
6 Typ
V
V
μA
86% VO
V
2
80% VO
VSENSE2 decreasing below threshold
2-ms pulse width
VOUT2 = 1.5 V
μs
mA
mA
140 Typ
375 Typ
7.5 Typ
80% VO
V
0.5% VO
140 Typ
83 Typ
mV
μs
mV
140
750 Typ
7.5 Typ
2.4
2.65
mA
mA
V
VSENSE2 decreasing below threshold
IO = 250 mA, VIN1 = 3.2 V, TJ = 25C
IO = 250 mA, VIN1 = 3.2 V
2-ms pulse width
VOUT1 = 1.5 V
86% VO
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended operating junction temperature range (TJ = -55C to 125C), VIN1 or VIN2 = VO(nom) + 1 V, IO = 1 mA, ,
EN = 0 V, CO = 33 F, unless otherwise specified.
IO = 1 mA to 250 mA for regulato1 and 1 mA to 125 mA for regulator2.
Minimum input operating voltage is 2.7 V or VO(Typ) + 1V, whichever is greater. Maximum input voltage 6.0 V, minimum output
current 1 mA.
If VO < 1.8 V then Vi(max) = 6.0 V, VI(min) = 2.7 V:
VO ( VI(max)  2.7V )
Line regulation (mV) = (%/V) x
x 1000
100
If VO > 2.5 V then VI(max) = 6.0 V, Vi(min) VO + 1 V:
VO ( VI(max)  VO  1V )
Line regulation (mV) = (%/V) x
x 1000
100
Input voltage (VIN1 or VIN2) = VO(Typ) – 100 mV. For 1.8 V regulators, the dropout voltage is limited by the input voltage range. The
3.3 V regulator input voltage is to 3.2 V to perform this test.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
6
Case X
Symbol
A
A1
b
c
D
Min
Max
1.20
0.05
0.15
0.19
0.30
0.15 NOM
6.40
6.60
Symbol
e
E
E1
L
Min
Max
0.65 BSC
4.30
4.50
6.20
6.60
0.50
0.75
Notes:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. The package thermal performance may be enhanced by bonding the thermal pad to an external plane. This solderable pad
is electrically and thermally connected to the backside of the die and leads 1, 10, 11, and 20.
4. Body dimensions do not include mold flash or protrusions. Mold flash and protrusion shall not exceed 0.15 mm per side.
5. Falls within JEDEC MO-153.
FIGURE 1. Case outline.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
7
Case X
Terminal
number
1
2
3
4
Terminal
symbol
NC
VIN1
VIN1
MR1
Terminal
number
11
12
13
14
Terminal
symbol
NC
VOUT2
VOUT2
VSENSE2/FB2
5
MR 2
15
EN
7
SEQ
8
GND
9
VIN2
10
VIN2
NC = Not internal connection
16
RESET
PG1
17
18
19
20
VSENSE1/FB1
VOUT1
VOUT1
NC
6
FIGURE 2. Terminal connections.
NOTES:
1. For most applications, VSENSE1 and VSENSE2 should be internally connected to VOUT as closed as possible to the device. For
other implementations, refer to the SENSE terminal connection discussion in the manufacturer data.
2. If the SEQ terminal is floating at the input, VOUT2 powers up first.
FIGURE 3. Block diagrams.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
8
Notes:
1.
2.
3.
VRES is the minimum input voltage for a valid RESET . The symbol VRES is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
VIT- Trip voltage is typically 5% lower than the output voltage (95% VO) VIT– to VIT+ is the hysteresis voltage.
VPG1 is the minimum input voltage for a valid PG1. The symbol V PG1 is not currently listed within EIA or JEDEC standards
for semiconductor symbology
FIGURE 4. Timing diagram.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
9
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control number 1/
V62/07610-01XE
1/
Device manufacturer
CAGE code
01295
Vendor part number
TPS70751MPWPREP
The vendor item drawing establishes an administrative control number for identifying the
item on the engineering documentation.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/07610
PAGE
10