PD - 96274 IRFI4019HG-117P DIGITAL AUDIO MOSFET Key Parameters Features Integrated Half-Bridge Package Reduces the Part Count by Half Facilitates Better PCB Layout Key Parameters Optimized for Class-D Audio Amplifier Applications Low RDS(ON) for Improved Efficiency Low Qg and Qsw for Better THD and Improved Efficiency Low Qrr for Better THD and Lower EMI Can Delivery up to 200W per Channel into 8Ω Load in Half-Bridge Configuration Amplifier Lead-Free Package Halogen-Free Description h VDS 150 RDS(ON) typ. @ 10V 80 V m: Qg typ. 13 nC Qsw typ. 4.1 nC RG(int) typ. 2.5 Ω TJ max 150 °C G1 D1 S1/D2 G2 S2 TO-220 Full-Pak 5 PIN G1, G2 D1, D2 S1, S2 Gate Drain Source This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It consists of two power MosFET switches connected in half-bridge configuration. The latest process is used to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery, and internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable device for Class D audio amplifier applications. Absolute Maximum Ratings h Parameter Max. Units 150 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage ±20 ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 8.7 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 6.2 IDM Pulsed Drain Current 34 EAS Single Pulse Avalanche Energy Power Dissipation c PD @TC = 100°C f Power Dissipation f TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range PD @TC = 25°C d 7.2 0.15 -55 to + 150 h f RθJC Junction-to-Case RθJA Junction-to-Ambient Parameter f W/°C °C 300 (1.6mm from case) Thermal Resistance mJ W 77 18 Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw A x x 10lb in (1.1N m) Typ. Max. ––– 6.9 ––– 65 Units Notes through are on page 2 www.irf.com 1 10/08/09 IRFI4019HG-117P Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Min. h Typ. Max. Units Conditions BVDSS Drain-to-Source Breakdown Voltage 150 ––– ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C Reference to 25°C, ID = 1mA RDS(on) Static Drain-to-Source On-Resistance ––– 80 95 mΩ VGS = 10V, ID = 5.2A VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V VDS = VGS, ID = 50µA ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 20 µA ––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 IGSS V VGS = 0V, ID = 250µA e VDS = 150V, VGS = 0V VDS = 150V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V gfs Forward Transconductance 11 ––– ––– Qg Total Gate Charge ––– 13 20 Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.3 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– Qgd Gate-to-Drain Charge ––– 3.9 ––– ID = 5.2A Qgodr Gate Charge Overdrive ––– 5.0 ––– See Fig. 6 and 19 Qsw Switch Charge (Qgs2 + Qgd) ––– 4.1 ––– RG(int) Internal Gate Resistance ––– 2.5 ––– td(on) Turn-On Delay Time ––– 7.0 ––– VDD = 75V, VGS = 10V tr Rise Time ––– 6.6 ––– ID = 5.2A td(off) Turn-Off Delay Time ––– 13 ––– tf Fall Time ––– 3.1 ––– Ciss Input Capacitance ––– 810 ––– Coss Output Capacitance ––– 100 ––– Crss Reverse Transfer Capacitance ––– 15 ––– ƒ = 1.0MHz, Coss Effective Output Capacitance ––– 97 ––– VGS = 0V, VDS = 0V to 120V LD Internal Drain Inductance ––– 4.5 ––– Between lead, S VDS = 75V nC Internal Source Inductance ––– 7.5 VGS = 10V Ω ns e RG = 2.4Ω VGS = 0V pF nH LS VDS = 50V, ID = 5.2A ––– VDS = 25V See Fig.5 D 6mm (0.25in.) from package G S and center of die contact Diode Characteristics h Parameter IS @ TC = 25°C Continuous Source Current Min. Typ. Max. Units Conditions MOSFET symbol ––– ––– 8.7 ––– ––– 34 showing the integral reverse ISM (Body Diode) Pulsed Source Current VSD (Body Diode) Diode Forward Voltage ––– ––– 1.3 V p-n junction diode. TJ = 25°C, IS = 5.2A, VGS = 0V trr Reverse Recovery Time ––– 57 86 ns TJ = 25°C, IF = 5.2A Qrr Reverse Recovery Charge ––– 140 210 nC di/dt = 100A/µs c A Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 5.8mH, RG = 25Ω, IAS = 5.2A. Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 e e Rθ is measured at TJ of approximately 90°C. Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information Specifications refer to single MosFET. www.irf.com IRFI4019HG-117P 100 100 10 BOTTOM VGS 15V 12V 10V 9.0V 8.0V 7.0V 6.0V 5.5V 1 5.5V 0.1 ≤ 60µs PULSE WIDTH Tj = 25°C 10 BOTTOM 5.5V 1 ≤ 60µs PULSE WIDTH Tj = 150°C 0.01 0.1 0.1 1 10 100 0.1 VDS , Drain-to-Source Voltage (V) 10 100 Fig 2. Typical Output Characteristics 2.5 10 RDS(on) , Drain-to-Source On Resistance (Normalized) 100 ID, Drain-to-Source Current(Α) 1 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics TJ = 175°C TJ = 25°C 1 VDS = 50V ≤ 60µs PULSE WIDTH 0.1 4 5 6 7 ID = 5.2A VGS = 10V 2.0 1.5 1.0 0.5 0.0 8 -60 -40 -20 VGS, Gate-to-Source Voltage (V) 100000 VGS, Gate-to-Source Voltage (V) Ciss Coss 100 40 60 80 100 120 140 160 20 Coss = Cds + Cgd 1000 20 Fig 4. Normalized On-Resistance vs. Temperature VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 10000 0 TJ, Junction Temperature (°C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) VGS 15V 12V 10V 9.0V 8.0V 7.0V 6.0V 5.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP Crss 10 ID= 5.2A VDS = 120V VDS= 75V VDS= 30V 16 12 8 4 0 1 1 10 100 1000 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs.Drain-to-Source Voltage www.irf.com 0 5 10 15 20 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage 3 IRFI4019HG-117P 100 10 ID, Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 100 TJ = 150°C 1 TJ = 25°C OPERATION IN THIS AREA LIMITED BY R DS(on) 1msec DC 10msec 1 Tc = 25°C Tj = 150°C Single Pulse VGS = 0V 0.1 0.1 0.0 0.5 1.0 1 1.5 10 100 1000 VDS , Drain-toSource Voltage (V) VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 5.0 VGS(th) Gate threshold Voltage (V) 10 8 ID , Drain Current (A) 100µsec 10 6 4 2 4.0 ID = 50µA 3.0 2.0 0 25 50 75 100 125 -75 150 -50 -25 0 25 50 75 100 125 150 TJ , Temperature ( °C ) TJ , Junction Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( ZthJC ) D = 0.50 1 0.1 0.20 0.10 0.05 0.02 0.01 τJ R1 R1 τJ τ1 R2 R2 R3 R3 Ri (°C/W) τC τ1 τ2 τ3 τ2 Ci= τi/Ri Ci= τi/Ri τ3 τ τι (sec) 1.508254 0.000814 2.154008 0.111589 3.237738 2.2891 0.01 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 4 www.irf.com 0.5 EAS, Single Pulse Avalanche Energy (mJ) () RDS (on), Drain-to -Source On Resistance Ω IRFI4019HG-117P ID = 5.2A 0.4 0.3 0.2 TJ = 125°C 0.1 TJ = 25°C 0.0 4 5 6 7 8 9 350 I D 0.91A 1.1A BOTTOM 5.2A 300 TOP 250 200 150 100 50 0 10 25 VGS, Gate-to-Source Voltage (V) P.W. + + - * • • • • 125 150 D.U.T. ISD Waveform Reverse Recovery Current VDD ** P.W. Period *** + dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test D= Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - 100 Fig 13. Maximum Avalanche Energy Vs. Drain Current Driver Gate Drive D.U.T RG 75 Starting TJ, Junction Temperature (°C) Fig 12. On-Resistance Vs. Gate Voltage 50 + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode Forward Drop Inductor Curent Ripple ≤ 5% * Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel VDD ISD *** VGS = 5V for Logic Level Devices Fig 14. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs www.irf.com 5 IRFI4019HG-117P V(BR)DSS 15V D.U.T RG VGS 20V DRIVER L VDS tp + V - DD IAS tp A 0.01Ω I AS Fig 15b. Unclamped Inductive Waveforms Fig 15a. Unclamped Inductive Test Circuit RD VDS VDS 90% VGS D.U.T. RG + -VDD 10% VGS 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % td(on) Fig 16a. Switching Time Test Circuit td(off) tr tf Fig 16b. Switching Time Waveforms Id Vds Vgs L DUT 0 1K 20K S VCC Vgs(th) Qgs1 Qgs2 Fig 17a. Gate Charge Test Circuit 6 Qgd Qgodr Fig 17b Gate Charge Waveform www.irf.com IRFI4019HG-117P TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117 (Dimensions are shown in millimeters (inches)) TO-220 Full-Pak 5-Pin Part Marking Information 3 * + ,) 5, 1 $ 6, 6, +7 ( /3 $0 ;( (5% 0 8 1 57$ 3 U H EH HU) PQ QXW HJ UD RO SQ D+ L[ V ILX HWD V FLG * QL HVW R1 $/1 2 7,$ 1 (57 1, * + ,) (5, ), 7 & (5 ( ' 2 & 7($ ' $ : : <3 2 * 2 / (( )5 ' ($/ 6 7($ 1 * ,6 ( ' 3 5$ <( < /<% (' 02 & 6(6 72 $ / . (( : 5. 2 : : : (' 2 &( 7, 6< /% 0 (6 $6 $ TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2009 www.irf.com 7