IRF IRFB4019PBF

PD - 97075
IRFB4019PbF
DIGITAL AUDIO MOSFET
Features
Key Parameters
• Key Parameters Optimized for Class-D Audio
VDS
150
RDS(ON) typ. @ 10V
80
V
m:
• Low RDSON for Improved Efficiency
Qg typ.
13
nC
• Low QG and QSW for Better THD and Improved
Qsw typ.
5.1
nC
RG(int) typ.
2.4
Ω
TJ max
175
°C
Amplifier Applications
Efficiency
• Low QRR for Better THD and Lower EMI
• 175°C Operating Junction Temperature for
D
Ruggedness
D
• Can Deliver up to 200W per Channel into 8Ω Load in
Half-Bridge Configuration Amplifier
G
G
S
Description
D
S
TO-220AB
G
D
S
Gate
Drain
Source
This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes
the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode
reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance
factors such as efficiency, THD and EMI. Additional features of this MOSFET are 175°C operating junction
temperature and repetitive avalanche capability. These features combine to make this MOSFET a highly efficient,
robust and reliable device for ClassD audio amplifier applications.
Absolute Maximum Ratings
Parameter
Max.
Units
V
VDS
Drain-to-Source Voltage
150
VGS
Gate-to-Source Voltage
±20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
17
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
12
IDM
Pulsed Drain Current c
51
PD @TC = 25°C
Power Dissipation f
80
PD @TC = 100°C
Power Dissipation f
40
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
W
0.5
-55 to + 175
Soldering Temperature, for 10 seconds
W/°C
°C
300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
A
10lbxin (1.1Nxm)
Thermal Resistance
Parameter
Typ.
Max.
RθJC
Junction-to-Case f
–––
1.88
RθCS
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient f
0.50
–––
–––
62
RθJA
Units
°C/W
Notes  through … are on page 2
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1
3/2/06
IRFB4019PbF
Electrical Characteristics @ T J = 25°C (unless otherwise specified)
Parameter
Min.
Typ. Max. Units
Conditions
BV DSS
Drain-to-Source Breakdown Voltage
150
–––
–––
∆ΒV DSS/∆T J
Breakdown Voltage Temp. Coefficient
–––
0.19
–––
V/°C Reference to 25°C, ID = 1mA
R DS(on)
Static Drain-to-Source On-Resistance
–––
80
95
mΩ
V GS = 10V, ID = 10A
V GS(th)
Gate Threshold Voltage
3.0
–––
4.9
V
V DS = V GS, ID = 50µA
∆V GS(th)/∆T J
Gate Threshold Voltage Coefficient
–––
-13
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
20
µA
V DS = 150V, V GS = 0V
–––
–––
250
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
V GS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
14
–––
–––
g fs
Forward Transconductance
Qg
V
V GS = 0V, ID = 250µA
V DS = 150V, V GS = 0V, T J = 125°C
V GS = -20V
S
V DS = 10V, ID = 10A
Total Gate Charge
–––
13
20
Q gs1
Pre-Vth Gate-to-Source Charge
–––
3.3
–––
Q gs2
Post-Vth Gate-to-Source Charge
–––
0.95
–––
Q gd
Gate-to-Drain Charge
–––
4.1
–––
ID = 10A
Q godr
See Fig. 6 and 19
Gate Charge Overdrive
–––
4.7
–––
Q sw
Switch Charge (Q gs2 + Q gd)
–––
5.1
–––
e
V DS = 75V
nC
V GS = 10V
R G(int)
Internal Gate Resistance
–––
2.4
–––
td(on)
Turn-On Delay Time
–––
7.0
–––
tr
Rise Time
–––
13
–––
td(off)
Turn-Off Delay Time
–––
12
–––
tf
Fall Time
–––
7.8
–––
C iss
Input Capacitance
–––
800
–––
C oss
Output Capacitance
–––
74
–––
C rss
Reverse Transfer Capacitance
–––
19
–––
C oss
Effective Output Capacitance
–––
99
–––
V GS = 0V, V DS = 0V to 120V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
LS
Internal Source Inductance
–––
7.5
–––
Ω
V DD = 75V, V GS = 10V
e
ID = 10A
ns
R G = 2.4Ω
V GS = 0V
pF
V DS = 50V
ƒ = 1.0MHz,
nH
See Fig.5
D
6mm (0.25in.)
from package
G
S
and center of die contact
Avalanche Characteristics
Parameter
E AS
Single Pulse Avalanche Energy
IAR
Avalanche Current
E AR
Repetitive Avalanche Energy
g
d
Typ.
Max.
Units
–––
73
mJ
See Fig. 14, 15, 17a, 17b
g
A
mJ
Diode Characteristics
Parameter
IS @ T C = 25°C Continuous Source Current
Min.
Typ. Max. Units
–––
–––
17
Conditions
MOSFET symbol
ISM
(Body Diode)
Pulsed Source Current
–––
–––
51
V SD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
trr
Reverse Recovery Time
–––
64
96
ns
T J = 25°C, IF = 10A
Q rr
Reverse Recovery Charge
–––
160
240
nC
di/dt = 100A/µs
c
A
V
showing the
integral reverse
p-n junction diode.
T J = 25°C, IS = 10A, V GS = 0V
e
e
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 1.46mH, RG = 25Ω, IAS = 10A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
„ Rθ is measured at TJ of approximately 90°C.
… Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
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IRFB4019PbF
100
100
10
BOTTOM
1
0.1
5.0V
≤ 60µs PULSE WIDTH
Tj = 25°C
0.01
10
BOTTOM
5.0V
1
≤ 60µs PULSE WIDTH
Tj = 175°C
0.1
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
100.0
VDS = 25V
≤ 60µs PULSE WIDTH
10.0
TJ = 175°C
1.0
TJ = 25°C
0.1
2
4
6
8
ID = 10A
VGS = 10V
2.5
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
2.0
1.5
1.0
0.5
10
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
10000
20
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
Ciss
Coss
100
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
1000
0
TJ, Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
Crss
ID= 10A
VDS = 120V
16
VDS= 75V
VDS= 30V
12
8
4
0
10
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
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0
5
10
15
20
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
3
IRFB4019PbF
1000
10
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
100
TJ = 175°C
1
TJ = 25°C
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
100µsec
1msec
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1
1.5
10
100
1000
VDS , Drain-toSource Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
5.0
VGS(th) Gate threshold Voltage (V)
20
16
ID , Drain Current (A)
DC
12
8
4
4.0
ID = 50µA
3.0
2.0
1.0
0
25
50
75
100
125
150
-75
175
-50 -25
0
25
50
75
100 125 150 175
TJ , Temperature ( °C )
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
τJ
0.02
0.01
R1
R1
τJ
τ1
R2
R2
Ri (°C/W)
τC
τ2
τ1
Ci= τi/Ri
Ci= τi/Ri
0.01
R3
R3
τ2
τ3
τ3
τ
τι (sec)
0.535592 0.000222
0.913763 0.001027
0.432454 0.006058
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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300
0.5
EAS, Single Pulse Avalanche Energy (mJ)
RDS (on), Drain-to -Source On Resistance (Ω)
IRFB4019PbF
ID = 10A
0.4
0.3
0.2
TJ = 125°C
0.1
TJ = 25°C
0.0
4
6
8
10
12
14
ID
1.3A
2.3A
BOTTOM 10A
TOP
250
200
150
100
50
0
16
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
10
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
80
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 10A
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long as neither
Tjmax nor Iav (max) is exceeded
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
5
IRFB4019PbF
Driver Gate Drive
D.U.T
ƒ
-
‚
-
-
*
RG
•
•
•
•
„
P.W.
Period
***
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+

Period
P.W.
+
VDD
**
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 16. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 17a. Unclamped Inductive Test Circuit
LD
Fig 17b. Unclamped Inductive Waveforms
VDS
VDS
+
90%
VDD D.U.T
VGS
10%
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
Fig 18a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
tr
td(off)
Fig 18b. Switching Time Waveforms
Id
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 19a. Gate Charge Test Circuit
6
Qgs1 Qgs2
Qgd
Qgodr
Fig 19b Gate Charge Waveform
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IRFB4019PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS SEMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in as s embly line pos ition
indicates "Lead - Free"
INTERNATIONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/06
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