HV57009 64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current Ordering Information Package Options Device 80-Lead Quad Ceramic Gullwing HV57009 HV57009DG 80 Lead Quad Plastic Gullwing HV57009PG Die 80 Lead Quad Ceramic Gullwing (MIL-Std-833 Processed*) HV57009X RBHV57009DG * For Hi-Rel process flows, refer to page 5-3 of the Databook. Features General Description ❏ Processed with HVCMOS technology ® The HV570 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. ❏ 5V CMOS Logic ❏ Output voltage up to -85V The device has two parallel 32-bit shift registers, permitting data rate twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. ❏ Output current source control ❏ 16MHz equivalent data rate ❏ Latched data outputs ❏ Forward and reverse shifting options (DIR pin) ❏ Diode to VDD allows efficient power recovery ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD1 -0.5V to +7.5V 1 VDD + 0.5V to -95V Output Voltage, VNN Logic input levels1 Ground -0.3V to VDD +0.3V Current2 Continuous total power The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source. 1.5A dissipation3 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Plastic Ceramic 1200mW 1900mW Plastic -40°C to +85°C Ceramic -55°C to +125°C -65°C to +150°C 260°C Notes: 1. All voltages are referenced to VSS. 2. Limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. 03/12/02 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV57009 Electrical Characteristics DC Characteristics (All voltages are referenced to VSS, VSS = 0, TA = 25°C) Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA VDD = VDD, max fCLK = 8MHz INN High voltage supply current -10 µA Outputs off, HVOUT = -85V (total of all outputs) IDDQ Quiescent VDD supply current 100 µA All inputs = VDD, except +IN = VSS = GND VOH High-level output V IO = -100µA VDD V IO = -2mA +0.5 V IO = 100µA Data out HVOUT VDD -0.5 +1 VOL Low-level output IIH High-level logic input current 1 µA VIH = VDD IIL Low-level logic input current -1 µA VIL = 0V ICS HV output source current -2 mA VREF = 2V, REXT = 1K, see Figures 8a and 8b mA VREF = 0.1V, REXT = 1K, see Figure 8a and 8b Data out -0.1 ∆ICS HV output source current for IREF = 2.0mA 10 % VREF = 2V, REXT = 1K Notes 1: Current going out of the chip is considered negative. AC Characteristics (Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points] for measurements) Symbol Parameter Min Max Units 8 MHz Conditions fCLK Clock frequency DC tWL, tWH Clock width high or low 62 ns tSU Data set-up time before clock rises 10 ns tH Data hold time after clock rises 15 ns tON, tOFF Time for latch enable to HVOUT 500 ns CL = 15pF tDHL Delay time clock to data high to low 70 ns CL = 15pF tDLH Delay time clock to data low to high 70 ns CL = 15pF tDLE Delay time clock to LE low to high 25 ns tWLE Width of LE pulse 25 ns tSLE LE set-up time before clock rises 0 ns tr, tf Maximum allowable clock rise and fall time (10% and 90% points) 100 2 ns Per register HV57009 Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V HVOUT HV output off voltage -85 VDD V VIH High-level input voltage VDD - 1.2V VDD V VIL Low-level input voltage 0 1.2 V fCLK Clock frequency per register DC 8 MHz TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 °C Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above. Figure 1: Input and Output Equivalent Circuits VDD VDD Data Out Input VSS VSS Logic Data Output Logic Inputs VDD VDD ICS PCTL Input To Internal Circuits HVOUT VSS Analog Input High Voltage Output 3 HV57009 Figure 2: Switching Waveforms VDD Data Input 50% Data Valid 50% VSS CLK 50% tf tH tSU 90% 50% 50% tWL tr VDD 10% 10% tWH 90% 50% VSS VDD 50% VSS tDLH Data Out VDD 50% VSS tDHL LE VSS tDLE HVOUT w/ data input LOW VDD 50% 50% tWLE tSLE VDD 90% 10% Previous IO = IREF IO = 0 HVOUT (off) tOFF HVOUT w/ data input HIGH 10% Previous IO = 0 tON 4 90% IO = IREF VDD HVOUT (off) HV57009 Figure 3: Functional Block Diagram DI/O2A DI/O1A LE VDD BL I/O DIR CLK HVOUT1 HVOUT2 HVOUT3 • • • HVOUT32 Latch SR1 Latch HVOUT33 HVOUT34 HVOUT35 • • • HVOUT64 Latch SR2 Latch Programmable Current I/O DI/O2B DI/O1B VSS VBP +IN -IN Note: Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64. Figure 4: Function Table Inputs Function Data In BL DIR Shift Reg HV Outputs Data Out X L X * ON * L H H X L....L ON L H H H X H....H H L H X * OFF Inversion of Stored Data DI/O1-2A H H H Qn→Qn+1 New ON or OFF DI/O1-2B DI/O1-2A L H H Qn→Qn+1 Previous ON or OFF DI/O1-2B DI/O1-2B L H L Qn→Qn-1 Previous ON or OFF DI/O1-2A DI/O1-2B H H L Qn→Qn-1 New ON or OFF DI/O1-2A All O/P High X Data Falls Through (Latches Tansparent) Data Stored in Latches I/O Relation X CLK X X LE Outputs Notes: * = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift. H = VDD (Logic)/VNN (HV Outputs) L = VSS 5 * HV57009 Figure 5: Pin Configurations 80-pin Gullwing Package Pin Pin Function 41 1 HVOUT 24 42 2 HVOUT 23 43 3 HVOUT 22 44 4 HVOUT 21 45 5 HVOUT 20 46 6 HVOUT 19 47 7 HVOUT 18 48 8 HVOUT 17 49 9 HVOUT 16 50 10 HVOUT 15 51 11 HVOUT 14 52 12 HVOUT 13 53 13 HVOUT 12 54 14 HVOUT 11 55 15 HVOUT 10 56 16 HVOUT 9 57 17 HVOUT 8 58 18 HVOUT 7 59 19 HVOUT 6 60 20 HVOUT 5 61 21 HVOUT 4 62 22 HVOUT 3 63 23 HVOUT 2 64 24 HVOUT 1 65 25 DI/O1A 66 26 DI/O2A 67 27 N/C 68 28 N/C 69 29 LE 70 30 CLK 71 31 BL 72 32 VSS 73 33 DIR 74 34 VDD 75 35 -IN 76 36 DI/O2B 77 37 DI/O1B 78 38 N/C 79 39 +IN 40 VBP 80 Figure 6: Package Outline Function HVOUT 64 HVOUT 63 HVOUT 62 HVOUT 61 HVOUT 60 HVOUT 59 HVOUT 58 HVOUT 57 HVOUT 56 HVOUT 55 HVOUT 54 HVOUT 53 HVOUT 52 HVOUT 51 HVOUT 50 HVOUT 49 HVOUT 48 HVOUT 47 HVOUT 46 HVOUT 45 HVOUT 44 HVOUT 43 HVOUT 42 HVOUT 41 HVOUT 40 HVOUT 39 HVOUT 38 HVOUT 37 HVOUT 36 HVOUT 35 HVOUT 34 HVOUT 33 HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 41 64 40 65 Index 25 80 24 1 top view 80-pin Gullwing Package Figure 7: Shift Register Operation HVOUT 32 DIR = VDD; CW (HVOUT1→HVOUT64) DIR = VSS; CCW (HVOUT64→HVOUT1) • HVOUT 33 • • • SR1 →CW • • • • →CW • • SR2 HVOUT 2 HVOUT 63 HVOUT 1 HVOUT 64 Pin DIR = VDD: DIR = VSS: Notes: 1. Pin designation for DIR = VDD. 2. A 0.1µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. See Fig. 8a and 8b. 6 25 DI/O1A DI/O2A 26 DI/O2A DI/O1A 36 DI/O2B DI/O1B 37 DI/O1B DI/O2B HV57009 Typical Current Programming Circuits VREF Since IOUT = IREF = REXT VDD 0.1µF Therefore, if IOUT = 2mA and VREF = -5V → REXT = 2.5KΩ. If IOUT = 1mA and REXT = 1KΩ → VREF = -1V. HV570 VBP If REXT >10KΩ, add series network RD and CD to ground for stability as shown. To other outputs This control method behaves linearly as long as the operational amplifier is not saturated. However, it requires a negative power source and needs to provide a current IREF = IOUT for each HV570 chip being controlled. Logic IOUT - + HVOUT +IN REXT IREF If HVOUT ≥ +1V, the HVOUT cascode may no longer operate as a perfect current source, and the output current will diminish. This effect depends on the magnitude of the output current. VSS -IN RD* 10K C D* 390pF VREF Given IOUT and VREF, the REXT can be calculated by using: Figure 8a: Negative Control REXT = = IREF VREF IOUT The intersection of a set of IOUT and VREF values can be located in the graph shown below. The value picked for REXT must always be in the shaded area for linear operation. This control method has the advantage that VREF is positive, and draws only leakage current. If REXT > 10K, add series network RD and CD to ground for stability as shown. VDD 0.1µF VREF Note: Lower reference current IREF, results in higher distortion, ∆ICS, on the output. HV570 VBP To other outputs Logic IOUT - + HVOUT VREF -IN REXT IREF 8 7 RD* 10K IOUT (mA) +IN VSS CD* 390pF 6 5 4 100 250 500 3 Figure 8b: Positive Control REXT = 1K 2 2K *Required if REXT > 10K or REXT is replaced by a constant current source. 1 5K 0 1 2 3 VREF (V) 4 5 03/12/02 ©2001 Supertex Inc. All rights reserved. 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