INTEGRATED CIRCUITS DATA SHEET TDA8764 10-bit high-speed low-power ADC with internal reference regulator Preliminary specification 1999 Jan 12 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 FEATURES APPLICATIONS • 10-bit resolution (binary or gray code) High-speed analog-to-digital conversion for: • Sampling rate up to 40 MHz (/4 version) • Video data digitizing • Radar pulse analysis Sampling rate up to 80 MHz (/8 version) • DC sampling allowed • Transient signal analysis • One clock cycle conversion only • High energy physics research • High signal-to-noise ratio over a large analog input frequency range (9.5 effective bits at 5 MHz; full-scale input at fclk = 40 MHz) • Σ∆ modulators • Medical imaging. • No missing codes guaranteed GENERAL DESCRIPTION • In-Range (IR) CMOS output The TDA8764 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 40 MHz (/4 version) and 80 MHz (/8 version). All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed. • TTL and CMOS levels compatible digital inputs • 2.7 to 3.6 V CMOS digital outputs • Low-level AC clock input signal allowed • Internal reference voltage regulator • Power dissipation only 250 mW (typical for /4 version) Power dissipation only 375 mW (typical for /8 version) • Low analog input capacitance, no buffer amplifier required The device includes an internal voltage reference regulator. • No sample-and-hold circuit required. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8764TS/4 SSOP28 LQFP32 TDA8764TS/8 TDA8764HL/4 TDA8764HL/8 1999 Jan 12 VERSION SAMPLING FREQUENCY (MHz) plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 40 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1 DESCRIPTION 2 80 40 80 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 2.7 3.3 3.6 V ICCA analog supply current TDA8764TS/4; TDA8764HL/4 − 25 tbf mA TDA8764TS/8; TDA8764HL/8 − 45 tbf mA TDA8764TS/4; TDA8764HL/4 − 25 tbf mA TDA8764TS/8; TDA8764HL/8 − 30 tbf mA ICCD ICCO INL DNL fclk(max) Ptot 1999 Jan 12 digital supply current output stages supply current TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − 0 tbf mA TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − 0 tbf mA TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − ±0.8 tbf LSB TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − ±0.8 tbf LSB TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − ±0.25 tbf LSB TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − ±0.25 tbf LSB TDA8764TS/4; TDA8764HL/4 40 − − MHz TDA8764TS/8; TDA8764HL/8 80 − − MHz integral non-linearity differential non-linearity maximum clock frequency total power dissipation TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − 250 tbf mW TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − 375 tbf mW 3 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 BLOCK DIAGRAM handbook, full pagewidth VCCA 3 (7) DEC 5 (10) 1 (5) REFERENCE VOLTAGE REGULATOR VRT VCCD2 CLK OE GRAY 11 (17) 10 15 (21) (16) CLOCK DRIVER 2 (6) 9 (15) 25 (31) 24 (30) 23 (29) analog VI 8 (14) voltage input VRM 7 (13) 22 (28) 21 (27) ANALOG-TO-DIGITAL CONVERTER LATCHES CMOS OUTPUTS RLAD 20 (26) 19 (25) 18 (24) 17 (23) 16 (22) VRB D9 MSB D8 D7 D6 D5 data outputs D4 D3 D2 D1 D0 LSB 13 (19) 6 (12) VCCO IN-RANGE LATCH TDA8764 CMOS OUTPUT 26 (2) 28 (4) 4 (8) AGND analog ground 12 (18) 14 (20) DGND2 digital ground 27 (3) OGND output ground DGND1 digital ground The pin numbers given in parenthesis refer to the LQFP32 package. Fig.1 Block diagram. 1999 Jan 12 TC 4 FCE099 IR output VCCD1 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 PINNING PINS SYMBOL DESCRIPTION SSOP28 LQFP32 CLK 1 5 clock input TC 2 6 twos complement input (input active LOW) VCCA 3 7 analog supply voltage (+5 V) AGND 4 8 analog ground DEC 5 10 decoupling input VRB 6 12 reference voltage BOTTOM input VRM 7 13 reference voltage MIDDLE input VI 8 14 analog input voltage VRT 9 15 reference voltage TOP input OE 10 16 output enable input (input active LOW) VCCD2 11 17 digital supply voltage 2 (+5 V) DGND2 12 18 digital ground 2 VCCO 13 19 supply voltage for output stages (2.7 to 3.6 V) OGND 14 20 output ground GRAY 15 21 gray code input (input active HIGH) D0 16 22 data output; bit 0 (LSB) D1 17 23 data output; bit 1 D2 18 24 data output; bit 2 D3 19 25 data output; bit 3 D4 20 26 data output; bit 4 D5 21 27 data output; bit 5 D6 22 28 data output; bit 6 D7 23 29 data output; bit 7 D8 24 30 data output; bit 8 D9 25 31 data output; bit 9 (MSB) IR 26 2 in-range data output DGND1 27 3 digital ground 1 VCCD1 28 4 digital supply voltage 1 (+5 V) n.c. − 1999 Jan 12 1, 9, 11 and 32 not connected 5 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 handbook, halfpage CLK 1 28 VCCD1 TC 2 27 DGND1 VCCA 3 26 IR AGND 4 25 D9 DEC 5 24 D8 VRB 6 23 D7 VRM 7 22 D6 TDA8764TS VI 8 21 D5 VRT 9 20 D4 OE 10 19 D3 VCCD2 11 18 D2 DGND2 12 17 D1 VCCO 13 16 D0 OGND 14 15 GRAY FCE100 25 D3 26 D4 27 D5 28 D6 29 D7 30 D8 handbook, full pagewidth 31 D9 32 n.c. Fig.2 Pin configuration (SSOP28). n.c. 1 24 D2 IR 2 23 D1 DGND1 3 22 D0 VCCD1 4 CLK 5 20 OGND TC 6 19 VCCO VCCA 7 18 DGND2 AGND 8 17 VCCD2 21 GRAY OE 16 VRT 15 VI 14 VRM 13 VRB 12 n.c. 11 DEC 10 n.c. 9 TDA8764HL Fig.3 Pin configuration (LQFP32). 1999 Jan 12 6 FCE125 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCA − VCCO −1.0 +4.0 V VCCD − VCCO −1.0 +4.0 V VI input voltage −0.3 +7.0 V Vi(sw)(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Tj junction temperature − 150 °C referenced to AGND Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Jan 12 PARAMETER CONDITIONS VALUE UNIT SSOP28 110 K/W LQFP32 90 K/W thermal resistance from junction to ambient in free air 7 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 CHARACTERISTICS The characteristics given refer to the SSOP28 package. VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 2.7 to 3.6 V; AGND and DGND shorted together; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 10 pF and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD1 digital supply voltage 1 4.75 5.0 5.25 V VCCD2 digital supply voltage 2 4.75 5.0 5.25 V VCCO output stages supply voltage 2.7 3.3 3.6 V ∆VCC supply voltage difference VCCA − VCCD −0.20 − +0.20 V VCCA − VCCO −0.20 − +2.55 V VCCD − VCCO −0.20 − +2.55 V TDA8764TS/4; TDA8764HL/4 − 25 tbf mA TDA8764TS/8; TDA8764HL/8 − 45 tbf mA TDA8764TS/4; TDA8764HL/4 − 25 tbf mA TDA8764TS/8; TDA8764HL/8 − 30 tbf mA ICCA ICCD ICCO analog supply current digital supply current output stages supply current TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − 0 tbf mA TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − 0 tbf mA 0 − 0.8 V Inputs CLOCK INPUT; CLK (REFERENCED TO DGND); note 1 VIL LOW-level input voltage VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VCLK = 0.8 V −1 0 +1 µA IIH HIGH-level input current VCLK = 2 V − 2 10 µA Ci input capacitance − 2 − pF 0 − 0.8 V INPUTS OE, TC AND GRAY (REFERENCED TO DGND); see Tables 3 and 4 VIL LOW-level input voltage VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VIL = 0.8 V −1 − − µA IIH HIGH-level input current VIH = 2 V − − 1 µA 1999 Jan 12 8 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8764 CONDITIONS MIN. TYP. MAX. UNIT VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL IIH Yi LOW-level input current TDA8764TS/4; TDA8764HL/4 VI = VRB − 0 − µA TDA8764TS/8; TDA8764HL/8 VI = VRB − 0 − µA TDA8764TS/4; TDA8764HL/4 VI = VRT − 45 − µA TDA8764TS/8; TDA8764HL/8 VI = VRT − 85 − µA input resistance − 70 − kΩ input capacitance 3 5 7 pF input resistance − 45 − kΩ input capacitance 3 5 7 pF HIGH-level input current input admittance TDA8764TS/4; TDA8764HL/4 input admittance TDA8764TS/8; TDA8764HL/8 fi = 5 MHz; note 2 fi = 5 MHz; note 2 Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1 VRB reference voltage BOTTOM tbf 1.3 tbf V VRT reference voltage TOP tbf 3.7 tbf V Vdiff(ref) differential reference voltage VRT − VRB tbf 2.4 tbf V TCVdiff temperature coefficient of differential reference voltage − tbf − mV/K Voffset(B) offset voltage BOTTOM note 3 − 161 − mV Voffset(T) offset voltage TOP note 3 − 161 − mV VI(p-p) analog input voltage (peak-to-peak value) note 4 tbf 2.08 tbf V Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND) VOL VOH IOZ 1999 Jan 12 LOW-level output voltage TDA8764TS/4; TDA8764HL/4 IOL = 1 mA 0 − 0.5 V TDA8764TS/8; TDA8764HL/8 IOL = 2 mA 0 − 0.5 V TDA8764TS/4; TDA8764HL/4 IOH = −1 mA VCCO − 0.5 − VCCO V TDA8764TS/8; TDA8764HL/8 IOH = −2 mA VCCO − 0.5 − VCCO V 0.5 V < Vo < VCCO −20 +20 µA HIGH-level output voltage output current in 3-state mode 9 − Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8764 CONDITIONS MIN. TYP. MAX. UNIT Switching characteristics CLOCK INPUT; CLK; see Fig.5; note 1 fclk(max) tCPH tCPL maximum clock frequency TDA8764TS/4; TDA8764HL/4 40 − − MHz TDA8764TS/8; TDA8764HL/8 80 − − MHz TDA8764TS/4; TDA8764HL/4 7 − − ns TDA8764TS/8; TDA8764HL/8 5 − − ns TDA8764TS/4; TDA8764HL/4 7 − − ns TDA8764TS/8; TDA8764HL/8 5 − − ns clock pulse width HIGH clock pulse width LOW Analog signal processing LINEARITY INL DNL integral non-linearity TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − ±0.8 tbf LSB TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − ±0.8 tbf LSB TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz; ramp input − ±0.25 tbf LSB TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz; ramp input − ±0.25 tbf LSB differential non-linearity Eoffset offset error middle code − ±1 − LSB EG gain error (from device to device) using internal reference voltage note 5 − tbf − % full-scale sine wave; note 6 − 20 − MHz 75% full-scale sine wave; note 6 − 30 − MHz small signal at mid-scale; VI = ±10 LSB at code 512; note 6 − 350 − MHz BANDWIDTH (fclk = 40 MHZ)/4 VERSION; B analog bandwidth tstLH analog input settling time LOW-to-HIGH full-scale square wave; see Fig.7 and note 7 − tbf tbf ns tstHL analog input settling time HIGH-to-LOW full-scale square wave; see Fig.7 and note 7 − tbf tbf ns 1999 Jan 12 10 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8764 CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH (fclk = 80 MHZ) /8 VERSION; B analog bandwidth full-scale sine wave; note 6 − 40 − MHz 75% full-scale sine wave; note 6 − 60 − MHz small signal at mid-scale; Vi = ±10 LSB at code 512; note 6 − 700 − MHz tstLH analog input settling time LOW-to-HIGH full-scale square wave; see Fig.7 and note 7 − tbf tbf ns tstHL analog input settling time HIGH-to-LOW full-scale square wave; see Fig.7 and note 7 − tbf tbf ns − −70 tbf dBc HARMONICS (fclk = 40 MHZ) /4 VERSION; Hall(FS) harmonics (full-scale); all components fi = 5 MHz second harmonics − −90 tbf dBc SFDR spurious free dynamic range fi = 5 MHz − tbf − dBc THD total harmonic distortion fi = 5 MHz − −70 − dB second harmonics − −71 tbf dBc third harmonics − −87 tbf dBc third harmonics HARMONICS (fclk = 80 MHZ)/8 VERSION; Hall(FS) harmonics (full-scale); all components fi = 5 MHz SFDR spurious free dynamic range fi = 5 MHz − tbf − dBc THD total harmonic distortion fi = 5 MHz − −70 − dB fclk = 40 MHz; /4 version tbf 58 − dB fclk = 80 MHz; /8 version tbf 58 − dB fi = 5 MHz tbf 9.5 tbf bits fi = 7.5 MHz tbf 9.2 tbf bits fi = 10 MHz tbf 9.0 tbf bits fi = 20 MHz tbf tbf tbf bits SIGNAL-TO-NOISE RATIO; note 8 SNR(FS) signal-to-noise ratio (full-scale) without harmonics; fi = 5 MHz EFFECTIVE BITS; note 8 EB effective bits TDA8764TS/4; TDA8764HL/4 effective bits TDA8764TS/8; TDA8764HL/8 1999 Jan 12 fclk = 40 MHz fclk = 80 MHz fi = 5 MHz tbf 9.5 tbf bits fi = 10 MHz tbf tbf tbf bits fi = 20 MHz tbf tbf tbf bits fi = 40 MHz tbf tbf tbf bits 11 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8764 CONDITIONS MIN. TYP. MAX. UNIT TWO-TONE; note 9 TTID two-tone intermodulation distortion fclk = 40 MHz − tbf − dB fclk = 80 MHz − tbf − dB fclk = 40 MHz − 10−13 − times/ sample fclk = 80 MHz − 10−13 − times/ sample BIT ERROR RATE BER bit error rate fi = 5 MHz; Vi = ±16 LSB at code 512 Timing (fclk = 40 MHz; CL = 10 pF) /4 version; see Fig.5 and note 10 tds sampling delay time − − 2 ns th output hold time 5 − − ns td output delay time VCCO = 2.7 V tbf 12 tbf ns VCCO = 3.3 V tbf 11 tbf ns − − 10 pF − − tbf V/µs CL digital output load capacitance SR slew rate VCCO = 2.7 V; CL = 10 pF Timing (fclk = 80 MHz; CL = 10 pF) /8 version; see Fig.5 and note 10 tds sampling delay time − − 2 ns th output hold time 4 − − ns td output delay time VCCO = 2.7 V tbf 8 tbf ns VCCO = 3.3 V tbf 7 tbf ns − − 10 pF − − tbf V/µs CL digital output load capacitance SR slew rate VCCO = 2.7 V; CL = 10 pF 3-state output delay times (fclk = 40 MHz) /4 version; see Fig.6 tdZH enable HIGH − tbf tbf ns tdZL enable LOW − tbf tbf ns tdHZ disable HIGH − tbf tbf ns tdLZ disable LOW − tbf tbf ns 3-state output delay times (fclk = 80 MHz) /8 version; see Fig.6 tdZH enable HIGH − tbf tbf ns tdZL enable LOW − tbf tbf ns tdHZ disable HIGH − tbf tbf ns tdLZ disable LOW − tbf tbf ns 1999 Jan 12 12 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 1 2. The input admittance is V i = ----- + Cijw Ri 3. Analog input voltages producing code 0 up to and including code 1023: a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) Voffset(T) (offset voltage TOP) is the difference between reference voltage TOP (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. 4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4. V RT – V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is V I = R L × I L = ------------------------------------------ × ( V RT – V RB ) = 0.866 × ( V RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ------------------------------------------ will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 5. ( V 1023 – V 0 ) – V i ( p – p ) E G = ------------------------------------------------------------ × 100 Vi ( p – p) 6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. 8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 10. Output data acquisition: the output data is available after the maximum delay time of td(max). For the 80 MHz version it is recommended to have the lowest possible output load. 1999 Jan 12 13 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 handbook, halfpage VRT ROT code 1023 RL VRM IL RLAD code 0 ROB VRB MGD281 Fig.4 Explanation of note 4. Table 1 Output coding and input voltage (typical values; referenced to AGND); binary and gray codes BINARY OUTPUT BITS STEP Vi(p-p) GRAY OUTPUT BITS IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 U/F <tbf 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tbf 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1022 ... 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1023 tbf 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 O/F >tbf 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Table 2 Output coding and input voltage (typical values; referenced to AGND); binary and twos complement codes BINARY OUTPUT BITS STEP Vi(p-p) TWO’S COMPLEMENT OUTPUT BITS IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 U/F <tbf 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 tbf 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ... 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1022 ... 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1023 tbf 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 O/F >tbf 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1999 Jan 12 14 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator Table 3 TDA8764 Mode selection TC OE X 1 high impedance high impedance 0 0 active; two complement active 1 0 active; binary active Table 4 D9 TO D0 IR Mode selection GRAY OE D9 TO D0 IR X 1 high impedance high impedance 0 0 active; binary active 1 0 active; gray active t CPL handbook, full pagewidth t CPH VCCO 50% CLK 0V sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D9 th VCCO DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td Fig.5 Timing diagram. 1999 Jan 12 15 MBG916 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 VCCD handbook, full pagewidth 50% OE tdHZ tdZH HIGH output data 90% tdLZ 50% tdZL LOW HIGH output data 50% LOW 10% VCCD 3.3 kΩ S1 TDA8764 15 pF TEST S1 tdLZ VCCD tdZL VCCD tdHZ DGND tdZH DGND FCE101 OE fOE = 100 kHz. Fig.6 Timing diagram and test conditions of 3-state output delay time. t STHL t STLH code 1023 VI 50% 50% code 0 2 ns 2 ns CLK MBE566 50% 50% 0.5 ns Fig.7 Analog input settling time diagram. 1999 Jan 12 16 0.5 ns Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 INTERNAL PIN CONFIGURATIONS handbook, halfpage handbook, halfpage VCCO V CCA D9 to D0 IR VI OGND AGND MBG915 MGC040 - 1 Fig.8 CMOS data and in range outputs. Fig.9 Analog inputs. DEC handbook, halfpage VCCA handbook, halfpage VCCO VRT OE TC GRAY VRM RLAD REGULATOR VRB OGND FCE102 AGND MBE558 - 1 Fig.10 OE, GRAY and TC inputs. 1999 Jan 12 Fig.11 VRB, VRM and VRT. 17 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator handbook, halfpage VCCD 1.5 V CLK DGND FCE103 Fig.12 CLK input. 1999 Jan 12 18 TDA8764 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 APPLICATION INFORMATION handbook, full pagewidth CLK TC VCCA 100 nF (2) AGND DEC 4.7 nF AGND VRB(1) VRM(1) 1 nF AGND 1 nF VI VRT(1) AGND 1 nF OE AGND V CCD2 100 nF 28 2 27 3 26 4 25 5 24 6 23 7 22 TDA8764TS 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCCD1 DGND1 (2) IR D9 D8 D7 D6 D5 D4 D3 D2 (2) DGND2 VCCO 100 nF 1 (2) OGND D1 D0 GRAY FCE104 The analog and digital supplies should be separated and well decoupled. An application note is available which describes the design and the realization of a demonstration board that uses TDA8764HL in an application environment. (1) VRB, VRM and VRT are decoupled to AGND. (2) Decoupling capacitor for supplies; it must be placed close to the device. Fig.13 Application diagram (SSOP28). 1999 Jan 12 19 100 nF Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator handbook, full pagewidth n.c. n.c. IR DGND1 100 nF(2) VCCD1 CLK TC VCCA 100 nF(2) AGND D9 32 31 D8 D7 30 29 TDA8764 D6 28 D5 27 D4 26 D3 25 1 24 2 23 3 22 4 21 TDA8764HL 5 20 6 19 7 18 8 17 9 10 n.c. DEC 4.7 nF AGND 11 12 n.c. 13 VRB 1 nF(1) 14 VRM 1 nF(1) AGND AGND VI 15 D0 GRAY OGND VCCO AGND 100 nF(2) DGND2 VCCD2 OE 1 nF(1) Fig.14 Application diagram (LQFP32). 20 D1 16 VRT The analog and digital supplies should be separated and well decoupled. An application note is available which describes the design and the realization of a demonstration board that uses TDA8764HL in an application environment. (1) VRB, VRM and VRT are decoupled to AGND. (2) Decoupling capacitor for supplies; it must be placed close to the device. 1999 Jan 12 D2 FCE126 100 nF(2) Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 PACKAGE OUTLINES SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1999 Jan 12 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 21 o Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index θ bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT401-1 1999 Jan 12 EUROPEAN PROJECTION 22 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Jan 12 TDA8764 23 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator TDA8764 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Jan 12 24 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 12 25 TDA8764 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 12 26 TDA8764 Philips Semiconductors Preliminary specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 12 27 TDA8764 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 295002/750/01/pp28 Date of release: 1999 Jan 12 Document order number: 9397 750 04632