IRF IRF6720S2TR1PBF

PD - 97315
IRF6720S2TRPbF
IRF6720S2TR1PbF
l
l
l
l
l
l
l
l
l
RoHS Compliant Containing No Lead and Bromide 
Low Profile (<0.7 mm)
Dual Sided Cooling Compatible 
Ultra Low Package Inductance
Optimized for High Frequency Switching 
Ideal for CPU Core DC-DC Converters
Optimized for Control FET Application
Compatible with existing Surface Mount Techniques 
100% Rg tested
DirectFET™ Power MOSFET ‚
Typical values (unless otherwise specified)
VDSS
VGS
RDS(on)
30V max ±20V max 6.0mΩ@ 10V 9.8mΩ@ 4.5V
Qg
tot
7.9nC
Qgd
Qgs2
Qrr
Qoss
Vgs(th)
2.8nC
0.9nC
14nC
5.1nC
2.0V
S1
Applicable DirectFET Outline and Substrate Outline 
S1
S2
SB
M2
RDS(on)
M4
DirectFET™ ISOMETRIC
L4
L6
L8
Description
The IRF6720S2PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve
improved performance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual
sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6720S2PbF has low gate resistance and low charge along with ultra low package inductance providing significant reduction in
switching losses. The reduced losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6720S2PbF has been optimized for the control FET socket of synchronous buck operating from 12 volt bus converters.
Absolute Maximum Ratings
Max.
Units
Drain-to-Source Voltage
30
V
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
±20
9.2
Parameter
VGS
ID @ TA = 25°C
ID @ TA = 70°C
Continuous Drain Current, VGS
ID @ TC = 25°C
Continuous Drain Current, VGS
IDM
EAS
Pulsed Drain Current
IAR
Avalanche Current
g
e
@ 10V e
@ 10V f
Single Pulse Avalanche Energy
g
Typical RDS(on) (mΩ)
ID = 11A
16
12
T J = 125°C
8
T J = 25°C
4
5
10
15
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
A
35
92
h
20
0
11
VGS , Gate-to-Source Voltage (V)
VDS
12
mJ
8.8
A
12.0
ID= 8.8A
10.0
VDS= 24V
VDS= 15V
8.0
6.0
4.0
2.0
0.0
0
2
4
6
8
10
12
14
16
18
20
Q G Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
www.irf.com
„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 0.31mH, RG = 25Ω, IAS = 8.8A.
1
04/07/08
IRF6720S2TR/TR1PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
Drain-to-Source Breakdown Voltage
Min.
30
Conditions
Typ. Max. Units
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
19
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
6.0
8.0
–––
9.8
12.8
V
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 11A i
VGS = 4.5V, ID = 8.8A i
VDS = VGS, ID = 25µA
VGS(th)
Gate Threshold Voltage
1.35
2.0
2.35
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-6.9
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 20V, VGS = 0V
–––
–––
150
VDS = 20V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
21
–––
–––
Qg
VGS = -20V
S
VDS = 15V, ID =8.8A
Total Gate Charge
–––
7.9
12
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.2
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.9
–––
Qgd
Gate-to-Drain Charge
–––
2.8
–––
ID = 8.8A
Qgodr
See Fig. 2
VDS = 15V
nC
VGS = 4.5V
Gate Charge Overdrive
–––
2.0
–––
Qsw
Switch Charge (Qgs2 + Qgd)
–––
3.7
–––
Qoss
Output Charge
–––
5.1
–––
nC
RG
Gate Resistance
–––
0.30
–––
Ω
td(on)
Turn-On Delay Time
–––
13
–––
VDD = 15V, VGS = 4.5Vi
tr
Rise Time
–––
35
–––
ID = 8.8A
td(off)
Turn-Off Delay Time
–––
11
–––
tf
Fall Time
–––
11
–––
Ciss
Input Capacitance
–––
1140
–––
Coss
Output Capacitance
–––
240
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
Min.
Typ. Max. Units
–––
–––
ns
VDS = 16V, VGS = 0V
RG= 6.2Ω
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Diode Characteristics
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
A
–––
–––
Conditions
MOSFET symbol
22
showing the
integral reverse
92
p-n junction diode.
(Body Diode)g
VSD
Diode Forward Voltage
–––
–––
1.0
V
TJ = 25°C, IS = 8.8A, VGS = 0V i
trr
Reverse Recovery Time
–––
16
24
ns
TJ = 25°C, IF =8.8A
Qrr
Reverse Recovery Charge
–––
14
21
nC
di/dt = 200A/µs i
Notes:
… Repetitive rating; pulse width limited by max. junction temperature.
‡ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF6720S2TR/TR1PbF
Absolute Maximum Ratings
Parameter
PD @TC = 25°C
e
Power Dissipation e
Power Dissipation f
TP
Peak Soldering Temperature
TJ
Operating Junction and
TSTG
Storage Temperature Range
Max.
Units
1.7
W
Power Dissipation
PD @TA = 25°C
PD @TA = 70°C
1.2
17
270
°C
-55 to + 175
Thermal Resistance
Parameter
RθJC
el
Junction-to-Ambient jl
Junction-to-Ambient kl
Junction-to-Case fl
RθJ-PCB
Junction-to-PCB Mounted
RθJA
Typ.
Max.
–––
86
12.5
–––
20
–––
–––
8.6
Junction-to-Ambient
RθJA
RθJA
Linear Derating Factor
1.0
e
Units
°C/W
–––
0.012
W/°C
100
Thermal Response ( Z thJA )
D = 0.50
10
0.20
0.10
0.05
1
0.02
0.01
τJ
R1
R1
τJ
τ1
R2
R2
R3
R3
R4
R4
τ1
τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri
Ci= τi/Ri
0.1
1E-005
0.0001
τ5
τ5
τA
0.00017
9.578
0.007941
34.880
0.52375
22.105
4.978
16.766
84
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
2.676
τA
τ2
τi (sec)
Ri (°C/W)
R5
R5
0.001
0.01
0.1
1
10
100
1000
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 
Notes:
‰ Mounted on minimum footprint full size board with metalized
ƒ Surface mounted on 1 in. square Cu board, steady state.
„ TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink.
Š Rθ is measured at TJ of approximately 90°C.
ˆ Used double sided cooling, mounting pad with large heatsink.
ƒ Surface mounted on 1 in. square Cu
board (still air).
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‰ Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. (still air)
3
IRF6720S2TR/TR1PbF
100
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
1
≤60µs PULSE WIDTH
Tj = 25°C
0.1
BOTTOM
10
≤60µs PULSE WIDTH
Tj = 175°C
2.5V
2.5V
0.01
1
0.1
1
10
100
0.1
Fig 4. Typical Output Characteristics
100
2.0
ID = 11A
VDS = 15V
≤60µs PULSE WIDTH
Typical R DS(on) (Normalized)
ID, Drain-to-Source Current (A)
10
Fig 5. Typical Output Characteristics
100
10
T J = 175°C
T J = 25°C
T J = -40°C
1
0.1
V GS = 10V
V GS = 4.5V
1.5
1.0
0.5
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)
Fig 7. Normalized On-Resistance vs. Temperature
Fig 6. Typical Transfer Characteristics
10000
16
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
14
Typical R DS(on) ( mΩ)
Coss = Cds + Cgd
C, Capacitance(pF)
1
V DS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Ciss
1000
Coss
Crss
100
12
10
8
6
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 10V
4
2
T J = 25°C
0
10
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
0
20
40
60
80
100
ID, Drain Current (A)
Fig 9. Typical On-Resistance vs.
Drain Current and Gate Voltage
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IRF6720S2TR/TR1PbF
100
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
10
T J = 175°C
T J = 25°C
1
T J = -40°C
100µsec
10
1msec
10msec
1
DC
T A = 25°C
0.1
T J = 150°C
VGS = 0V
Single Pulse
0
0.01
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.01
0.10
1.00
10.00
100.00
VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
Fig 11. Maximum Safe Operating Area
3.5
Typical V GS(th) Gate threshold Voltage (V)
35
ID, Drain Current (A)
30
25
20
15
10
5
3.0
2.5
2.0
50
75
100
125
150
ID = 250µA
ID = 1.0mA
1.0
ID = 1.0A
0.5
0.0
0
25
ID = 25µA
1.5
-75 -50 -25
175
25
50
75 100 125 150 175
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 12. Maximum Drain Current vs. Case Temperature
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
50
EAS , Single Pulse Avalanche Energy (mJ)
320
T J = 25°C
G fs , Forward Transconductance (S)
0
40
30
T J = 175°C
20
10
V DS = 15V
380µs PULSE WIDTH
2
0
ID
1.5A
2.4A
BOTTOM 8.8A
280
TOP
240
200
160
120
80
40
0
0
20
40
60
80
ID,Drain-to-Source Current (A)
100
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 14. Typ. Forward Transconductance vs. Drain Current Fig 15. Maximum Avalanche Energy vs. Drain Current
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5
IRF6720S2TR/TR1PbF
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming DTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
10
1
0.01
0.05
0.10
0.1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆ Tj = 25°C
and Tstart = 150°C.
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 16. Typical Avalanche Current vs.Pulsewidth
80
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 8.8A
EAR , Avalanche Energy (mJ)
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 17. Maximum Avalanche Energy
vs. Temperature
6
Notes on Repetitive Avalanche Curves , Figures 16, 17:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 19a, 19b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 16, 17).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRF6720S2TR/TR1PbF
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
S
20K
1K
Qgodr
Fig 18a. Gate Charge Test Circuit
Qgs2 Qgs1
Qgd
Fig 18b. Gate Charge Waveform
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
I AS
0.01Ω
tp
Fig 19a. Unclamped Inductive Test Circuit
VDS
VGS
RG
A
Fig 19b. Unclamped Inductive Waveforms
RD
VGS
90%
D.U.T.
+
- VDD
10%
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 20a. Switching Time Test Circuit
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VDS
td(off)
tf
td(on)
tr
Fig 20b. Switching Time Waveforms
7
IRF6720S2TR/TR1PbF
D.U.T
Driver Gate Drive
ƒ
+
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
-
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 19. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET™ Board Footprint, S1 (Small Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
CL
G = GATE
D = DRAIN
S = SOURCE
D
D
G
D
S
S
D
Optional additional pad to allow
interchangeability with S2
outline devices.
Mandatory pads to fit S1 outline.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
8
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IRF6720S2TR/TR1PbF
DirectFET™ Outline Dimension, S1 Outline (Small Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
METRIC
MAX
CODE MIN
4.85
A
4.75
3.95
B
3.70
2.85
C
2.75
0.45
D
0.35
0.52
E
0.48
0.62
F
0.58
0.52
G
0.48
1.12
H
1.08
N/A
J
N/A
0.90
K
0.80
1.80
L
1.70
0.740
M
0.68
R
0.020 0.080
0.17
P
0.08
IMPERIAL
MIN
0.187
0.146
0.108
0.014
0.019
0.023
0.019
0.042
N/A
0.031
0.066
0.027
0.001
0.003
MAX
0.191
0.156
0.112
0.018
0.020
0.024
0.020
0.044
N/A
0.035
0.070
0.029
0.003
0.007
DirectFET™ Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
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9
IRF6720S2TR/TR1PbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6720S2TRPBF). For 1000 parts on 7"
reel, order IRF6720S2TR1PBF
REEL DIMENSIONS
STANDARD OPTION (QTY 4800)
TR1 OPTION (QTY 1000)
IMPERIAL
IMPERIAL
METRIC
METRIC
MIN
MAX
MIN
CODE
MAX
MIN
MIN
MAX
MAX
12.992
A
N.C
6.9
N.C
177.77 N.C
330.0
N.C
0.795
B
0.75
N.C
N.C
19.06
20.2
N.C
N.C
0.504
C
0.53
0.50
13.5
12.8
0.520
13.2
12.8
0.059
D
0.059
1.5
1.5
N.C
N.C
N.C
N.C
3.937
E
2.31
N.C
58.72
100.0
N.C
N.C
N.C
F
N.C
N.C
N.C
N.C
0.53
0.724
18.4
13.50
G
0.488
0.47
11.9
12.4
N.C
0.567
14.4
12.01
H
0.469
0.47
11.9
11.9
N.C
0.606
15.4
12.01
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
A
B
C
D
E
F
G
H
DIMENSIONS
IMPERIAL
METRIC
MIN
MAX
MIN
MAX
0.311
0.319
7.90
8.10
0.154
0.161
3.90
4.10
0.469
0.484
11.90
12.30
0.215
0.219
5.45
5.55
0.201
0.209
5.10
5.30
0.256
0.264
6.50
6.70
0.059
N.C
1.50
N.C
0.059
1.50
0.063
1.60
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Data and specifications subject to change without notice.
This product has been designed and qualified to MSL1 rating for the Consumer market.
Additional storage requirement details for DirectFET products can be found in application note AN1035 on IR’s Web site.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/08
10
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