CY7B995:2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer

CY7B995 RoboClock®
2.5/3.3 V 200 MHz High-Speed
Multi-Phase PLL Clock Buffer
2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Features
Functional Description
The CY7B995 RoboClock® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of high
performance computer and communication systems.
■
2.5 V or 3.3 V operation
■
Split output bank power supplies
■
Output frequency range: 6 MHz to 200 MHz
■
45 ps typical cycle-cycle jitter
■
± 2% max output duty cycle
■
Selectable output drive strength
■
Selectable positive or negative edge synchronization
■
Eight LVTTL outputs driving 50  terminated lines
■
LVCMOS/LVTTL over-voltage tolerant reference input
■
Selectable phase-locked loop (PLL) frequency range and lock
indicator
■
Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
■
(1-6, 8, 10, 12) x multiply and (1/2,1/4) x divide ratios
■
Spread-Spectrum compatible
■
Power down mode
■
Selectable reference divider
■
Industrial temperature range: –40 °C to +85 °C
■
44-pin TQFP package
Cypress Semiconductor Corporation
Document Number: 38-07337 Rev. *I
•
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Any one of the outputs can be connected to
feedback to achieve different reference frequency multiplication,
and divide ratios and zero input-output delay.
The device also features split output bank power supplies, which
enable the user to run two banks (1Qn and 2Qn) at a power
supply level, different from that of the other two banks (3Qn and
4Qn). The three-level PE/HD pin also controls the
synchronization of the output signals to either the rising, or the
falling edge of the reference clock and selects the drive strength
of the output buffers. The high drive option (PE/HD = MID)
increases the output current from ± 12 mA to ± 24 mA.
For a complete list of related documentation, click here.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2016
CY7B995 RoboClock®
Logic Block Diagram
TEST PE/HD
PD#/DIV
FS VDDQ1
3
3
/R
REF
3
3
LOCK
PLL
FB
/N
3
3
DS1:0
1F1:0
3
3
1Q0
Phase
Select
1Q1
2Q0
3
2F1:0
3F1:0
3
3
3
Phase
Select
2Q1
3Q0
Phase
Select
and /K
3Q1
VDDQ3
4F1:0
3
3
4Q0
Phase
Select
and /M
4Q1
VDDQ4 sOE#
Document Number: 38-07337 Rev. *I
Page 2 of 19
CY7B995 RoboClock®
Contents
Pinouts .............................................................................. 4
Pin Definitions .................................................................. 5
Device Configuration ....................................................... 6
Governing Agencies ......................................................... 7
Absolute Maximum Conditions ....................................... 8
DC Specifications at 2.5 V ............................................... 9
DC Specifications at 3.3 V ............................................. 10
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
AC Input Specifications ................................................. 12
Switching Characteristics .............................................. 13
AC Timing Definitions .................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Document Number: 38-07337 Rev. *I
Package Drawing and Dimension ................................. 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 3 of 19
CY7B995 RoboClock®
Pinouts
4F1
sOE#
PD#/DIV
PE/HD
VDDQ4
VDDQ4
4Q1
4Q0
VSS
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
1F1
2F0
VSS
TES
T
2F1
REF
FS
VDD
3F0
3F1
4F0
Figure 1. 44-pin TQFP pinout (Top View)
44 43 42 41 40 39 38 37 36 35 34
CY7B995
1F0
32
DS1
31
DS0
30
LOCK
29
28
VDDQ1
VDDQ1
27
1Q0
26
24
1Q1
VSS
VSS
23
VSS
25
VSS
2Q1
2Q0
VDDQ1
VDD
FB
VDDQ3
VDDQ3
3Q0
3Q1
VSS
12 13 14 15 16 17 18 19 20 21 22
Document Number: 38-07337 Rev. *I
33
Page 4 of 19
CY7B995 RoboClock®
Pin Definitions
44-pin TQFP Package
I/O [1]
Pin
Name
Type
Description
39
REF
I
17
FB
I
LVTTL
Feedback Input.
37
TEST
I
3-Level
When MID or HIGH, disables PLL[2]. REF goes to all outputs. Set LOW
for normal operation.
2
sOE#
I, PD
LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set sOE#
LOW for normal operation.
4
PE/HD
I, PU
3-Level
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength. When LOW/HIGH, the outputs are synchronized with
the negative/positive edge of the reference clock respectively. When at
MID level, the output drive strength is increased and the outputs
synchronize with the positive edge of the reference clock. See Table 9
on page 7.
34, 33, 36, 35,
43, 42, 1, 44
nF[1:0]
I
3-Level
Selects Frequency and Phase of the Outputs. See Table 3, Table 4,
Table 5, Table 7, and Table 8 on page 7.
41
FS
I
3-Level
Selects VCO Operating Frequency Range. See Table 6 on page 7.
26, 27, 20, 21,
13, 14, 7, 8
nQ[1:0]
O
LVTTL
Four banks of two outputs. See Table 5 on page 6 for frequency
settings.
32, 31
DS[1:0]
I
3-Level
Selects Feedback Divider. See Table 2 on page 6.
3
PD#/DIV
I, PU
3-Level
Power down and Reference Divider Control. When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See Table
1 on page 6 for settings.
30
LOCK
O
LVTTL
PLL Lock Indication Signal. HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
5,6
VDDQ4 [3]
PWR
Power
Power supply for Bank 4 Output Buffers. See Table 10 on page 7 for
supply level constraints.
15,16
VDDQ3 [3]
PWR
Power
Power supply for Bank 3 Output Buffers. See Table 10 on page 7 for
supply level constraints.
19,28,29
VDDQ1 [3]
PWR
Power
Power supply for Bank 1 and Bank 2 Output Buffers. See Table 10
on page 7 for supply level constraints.
18,40
VDD[3]
PWR
Power
Power supply for the Internal Circuitry. See Table 10 on page 7 for
supply level constraints.
9–12, 22–25,
38
VSS
PWR
Power
Ground
LVTTL/LVCMOS Reference Clock Input.
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
3. A bypass capacitor (0.1F) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic is cancelled by the lead inductance of the traces.
Document Number: 38-07337 Rev. *I
Page 5 of 19
CY7B995 RoboClock®
Device Configuration
controlled by 3F[1:0] and 4F[1:0] as indicated in Table 3 and
Table 4, respectively.
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 2, and the reference input divider is controlled by the
3-level PD#/DIV pin as indicated in Table 1.
Table 3. Output Divider Settings – Bank 3
3F[1:0]
Table 1. Reference Divider Settings
PD#/DIV
R–Reference Divider
H
1
M
2
L[4]
N/A
LL
2
HH
4
Other[5]
1
Table 4. Output Divider Settings – Bank 4
Table 2. Feedback Divider Settings
Input
DS[1:0] N-Feedback
Divider
K - Bank3 Output Divider
Permitted Output Divider
Connected to FB
1 or 2
4F[1:0]
M- Bank4 Output Divider
LL
2
Other[5]
1
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in Table 5.
LL
2
LM
3
1
LH
4
1, 2 or 4
ML
5
1 or 2
Configuration
FB Input
Connected to
MM
1
1, 2 or 4
MH
6
1 or 2
HL
8
1 or 2
HM
10
1
HH
12
1
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
Table 5. Output Frequency Settings
Output Frequency
1Q[0:1] and
2Q[0:1][6]
3Q[0:1]
4Q[0:1]
1Qn or 2Qn
(N / R) x FREF (N / R) x
(N / R) x
(1 / K) x FREF (1 / M) x FREF
3Qn
(N / R) x K x (N / R) x FREF (N / R) x
FREF
(K / M) x FREF
4Qn
(N / R) x M x (N / R) x
(N / R) x FREF
FREF
(M / K) x FREF
Notes
4. When PD#/DIV = LOW, the device enters power down mode.
5. These states are used to program the phase of the respective banks. See Table 7 and Table 8.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference
frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO frequency, and is
within the range specified by FS pin. See Table 6.
Document Number: 38-07337 Rev. *I
Page 6 of 19
CY7B995 RoboClock®
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that
corresponds to each FS level is given in Table 6.
Table 6. Frequency Range Select
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 9. Refer to the AC Timing Definitions section for a
description of input-to-output and output-to-output phase
relationships.
FS
PLL Frequency Range
Table 9. PE/HD Settings
L
24 to 50 MHz
M
48 to 100 MHz
L
Negative
Low Drive
H
96 to 200 MHz
M
Positive
High Drive
H
Positive
Low Drive
PE/HD Synchronization
Selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the tU value is: tU = 1 / (fNOM × MF)
Output Drive Strength [9]
where MF is a multiplication factor which is determined by the FS
setting as indicated in Table 7.
The CY7B995 features split power supply buses for Banks 1 and
2, Bank 3 and Bank 4, which enables the user to obtain both
3.3 V and 2.5 V output signals from one device. The core power
supply (VDD) must be set at a level that is equal to or higher than
any of the output power supplies.
Table 7. MF Calculation
Table 10. Power Supply Constraints
FS
MF
fNOM at which tU is 1.0 ns (MHz)
VDD
L
32
31.25
3.3 V
M
16
62.5
2.5 V
H
8
125
VDDQ1[10]
VDDQ3[10]
VDDQ4[10]
3.3 V or 2.5 V 3.3 V or 2.5 V 3.3 V or 2.5 V
2.5 V
2.5 V
2.5 V
Governing Agencies
Table 8. Output Skew Settings
nF[1:0]
Skew
(1Q[0:1],2Q[0:1])
Skew
(3Q[0:1])
Skew
(4Q[0:1])
LL[7]
–4tU
Divide By 2
Divide By 2
LM
–3tU
–6tU
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
The following agencies provide specifications that apply to the
CY7B995. The agency name and relevant specification is listed
below.
Table 11. Governing Agencies and Specifications
Agency Name
JEDEC
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jiter Specs)
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1tU
+2tU
+2tU
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1
(Therma Theta JC)
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide By 4
Inverted[8]
Notes
7. LL disables outputs if TEST = MID and sOE# = HIGH.
8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
9. Please refer to “DC Parameters” section for IOH/IOL specifications.
10. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3 V, VDDQ1 = 3.3 V, VDDQ3 = 2.5 V
and VDDQ4 = 2.5 V.
Document Number: 38-07337 Rev. *I
Page 7 of 19
CY7B995 RoboClock®
Absolute Maximum Conditions
Parameter
Description
Condition
Max
Unit
2.25
2.75
V
VDD
Operating Voltage
VDD
Operating Voltage
Functional @ 3.3 V ± 10%
2.97
3.63
V
VIN(MIN)
Input Voltage
Relative to VSS
VSS – 0.3
–
V
VIN(MAX)
Input Voltage
Relative to VDD
–
VDD + 0.3
V
VREF(MAX)
Reference Input Voltage
VDD = 3.3 V
–
5.5
V
VREF(MAX)
Reference Input Voltage
VDD = 2.5 V
–
4.6
V
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
–
155
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
42
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
74
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
@1/8 in.
MSL
Moisture Sensitivity Level
FIT
Failure in Time
Document Number: 38-07337 Rev. *I
Functional @ 2.5 V ± 5%
Min
V–0
1
Manufacturing Testing
10
ppm
Page 8 of 19
CY7B995 RoboClock®
DC Specifications at 2.5 V
Parameter
Description
Condition
VDD
2.5 V Operating Voltage
2.5 V ± 5%
VIL
Input LOW Voltage
REF, FB, and sOE# Inputs
VIH
Input HIGH Voltage
VIHH
[11]
Input HIGH Voltage
3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV,
PE/HD). (These pins are normally wired to VDD, GND, or
unconnected)
VIMM[11]
Input MID Voltage
VILL[11]
Input LOW Voltage
IIL
Input Leakage Current
I3
3-Level Input DC Current HIGH, VIN = VDD
LOW, VIN = VSS
Max
Unit
2.375
2.625
V
–
0.7
V
1.7
–
V
VDD – –0.4
–
V
VDD/2 – 0.2 VDD/2
+ 0.2
VIN = VDD/GND,VDD = Max; (REF and FB Inputs)
MID, VIN = VDD/2
Min
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
V
–
0.4
V
–5
5
A
–
200
A
–50
50
A
–200
–
A
–25
–
A
IPU
Input Pull-Up Current
VIN = VSS, VDD = Max
IPD
Input Pull-Down Current
VIN = VDD, VDD = Max, (sOE#)
–
100
A
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 20 mA (PE/HD = MID),(nQ[0:1])
–
0.4
V
IOL = 2 mA (LOCK)
–
0.4
V
VOH
Output HIGH Voltage
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
2.0
–
V
IOH = –20 mA (PE/HD = MID),(nQ[0:1])
2.0
–
V
IOH = –2 mA (LOCK)
2.0
–
V
–
2
mA
10(typ.)
25
A
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW,
Outputs Not Loaded
IDDPD
Power down Current
PD#/DIV, sOE# = LOW
Test,nF[1:0],DS[1:0] = HIGH; VDD = Max
IDD
Dynamic Supply Current
At 100 MHz
CIN
Input Pin Capacitance
150
mA
4
pF
Note
11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document Number: 38-07337 Rev. *I
Page 9 of 19
CY7B995 RoboClock®
DC Specifications at 3.3 V
Parameter
Description
Condition
VDD
3.3 V Operating Voltage
3.3 V ± 10%
VIL
Input LOW Voltage
REF, FB and sOE# Inputs
VIH
Input HIGH Voltage
VIHH
[12]
Input HIGH Voltage
Min
Max
Unit
2.97
3.63
V
–
0.8
V
2.0
–
V
3-Level Inputs
VDD – –0.6
–
(TEST, FS, nF[1:0], DS[1:0],PD#/DIV, PE/HD); (These pins
VDD/2 – 0.3 VDD/2 +
are normally wired to VDD,GND or unconected
0.3
VIMM[12]
Input MID Voltage
VILL[12]
Input LOW Voltage
IIL
Input Leakage Current
VIN = VDD/GND,VDD = Max
(REF and FB inputs)
I3
3-Level Input DC Current
HIGH, VIN = VDD
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs,
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
V
V
–
0.6
V
–5
5
A
–
200
A
–50
50
A
–200
–
A
–25
–
A
IPU
Input Pull Up Current
VIN = VSS, VDD = Max
IPD
Input Pull Down Current
VIN = VDD, VDD = Max, (sOE#)
–
100
A
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
VOH
Output HIGH Voltage
IOL = 24 mA (PE/HD = MID),(nQ[0:1])
–
0.4
V
IOL = 2 mA (LOCK)
–
0.4
V
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
2.4
–
V
IOH = –24 mA (PE/HD = MID),(nQ[0:1])
2.4
–
V
IOH = –2 mA (LOCK)
2.4
–
V
–
2
mA
10(typ.)
25
A
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID,
REF = LOW, sOE# = LOW,
Outputs Not Loaded
IDDPD
Power Down Current
PD#/DIV, sOE# = LOW, Test,nF[1:0],DS[1:0] = HIGH,
VDD = Max
IDD
Dynamic Supply Current
At 100 MHz
CIN
Input Pin Capacitance
230
mA
4
pF
Note
12. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document Number: 38-07337 Rev. *I
Page 10 of 19
CY7B995 RoboClock®
Thermal Resistance
Parameter [13]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
44-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
54
°C/W
10
°C/W
AC Test Loads and Waveforms
Figure 2. For Lock Output and all other Outputs
VDDQ
Output

20pF
Output

For Lock Output
20pF
For All Other Outputs
Figure 3. 3.3V LVTTL and 2.5V LVTTL Output Waveforms
tORISE
tPWH
2.0V
tORISE
tOFALL
tOFALL
tPWH
1.7V
VTH =1.25V
VTH =1.5V
tPWL
0.8V
tPWL
0.7V
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 4. 3.3 V LVTTL and 2.5 V LVTTL Input Test Waveforms
 1 ns
 1ns
 1ns
3.0V
2.0V
VTH =1.5V
0.8V
0V
3.3V LVTTL INPUT TEST WAVEFORM
 1ns
2.5V
1.7V
VTH =1.25V
0.7V
0V
2.5V LVTTL INPUT TEST WAVEFORM
Note
13. These parameters are guaranteed by design and are not tested.
Document Number: 38-07337 Rev. *I
Page 11 of 19
CY7B995 RoboClock®
AC Input Specifications
Parameter
Description
Condition
Min
Max
Unit
TR,TF
Input Rise/Fall Time
0.8 V – 2.0 V
–
10
ns/V
TPWC
Input Clock Pulse
HIGH or LOW
2
–
ns
TDCIN
Input Duty Cycle
FREF
Reference Input
Frequency[14]
10
90
%
FS = LOW
2
50
MHz
FS = MID
4
100
FS = HIGH
8
200
Note
14. If PD#/DIV is in HIGH level (R-reference divider = 1). Reference Input Frequency = FREF. IF PD#/DIV is in MID level (R-reference divider = 2). Reference Input
Frequency = FREFx2.
Document Number: 38-07337 Rev. *I
Page 12 of 19
CY7B995 RoboClock®
Switching Characteristics
Parameter
Description
Condition
FOR
Output frequency range
VCOLR
VCO Lock Range
VCOLBW
VCO Loop Bandwidth
tSKEWPR
Matched-Pair Skew[15]
Skew between the earliest and the latest output
transitions within the same bank.
tSKEW0
Output-Output Skew[15]
Min
Type
Max
Unit
6
–
200
MHz
200
–
400
MHz
0.25
–
3.5
MHz
–
–
100
ps
Skew between the earliest and the latest output
transitions among all outputs at 0tU.
–
–
200
ps
tSKEW1
Skew between the earliest and the latest output
transitions among all outputs for which the same
phase delay has been selected.
–
–
200
ps
tSKEW2
Skew between the nominal output rising edge to the
inverted output falling edge.
–
–
500
ps
tSKEW3
Skew between non-inverted outputs running at
different frequencies.
–
–
500
ps
Skew between nominal to inverted outputs running at
different frequencies.
–
–
500
ps
Skew between nominal outputs at different power
supply levels.
–
–
650
ps
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ, VDD, temp,
air flow, frequency, etc.).
–
–
750
ps
–250
–
+250
ps
Fout < 100 MHz, Measured at VDD/2.
48
–
52
%
Fout > 100 MHz, Measured at VDD/2.
45
–
55
tSKEW4
Output-Output Skew[15]
tSKEW5
tPART
Part-Part Skew
tPD0
Ref to FB Propagation
Delay[16]
tODCV
Output Duty Cycle
tPWH
Output High Time
Deviation from 50%
Measured at 2.0 V for VDD = 3.3 V and at 1.7 V for
VDD = 2.5 V.
–
–
1.5
ns
tPWL
Output Low Time
Deviation from 50%
Measured at 0.8 V for VDD = 3.3 V and at 0.7 V for
VDD = 2.5 V.
–
–
2.0
ns
tR/tF
Output Rise/Fall Time
Measured at 0.8 V–2.0 V for VDD = 3.3 V and
0.7 V–1.7 V for VDD = 2.5 V.
0.15
–
1.5
ns
tLOCK
PLL Lock Time[17, 18]
tCCJ
Cycle-Cycle Jitter
–
–
0.5
ms
Divide by one output frequency, FS = L, FB = divide
by any.
–
45
100
ps
Divide by one output frequency, FS = M/H, FB = divide
by any.
–
55
150
ps
Notes
15. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
16. tPD is measured at 1.5 V for VDD = 3.3 V and at 1.25 V for VDD = 2.5 V with REF rise/fall times of 0.5 ns between 0.8 V–2.0 V.
17. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
18. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document Number: 38-07337 Rev. *I
Page 13 of 19
CY7B995 RoboClock®
AC Timing Definitions
Figure 5. Timing Definition
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEW0,1
tSKEWPR
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
DIVIDE BY 2 OUTPUT
tSKEW1,3,4
tSKEW1,3,4
DIVIDE BY 4 OUTPUT
With PE HIGH (LOW), the REF rising (falling) edges are aligned
to the FB rising (falling) edges. Also, when PE is HIGH (LOW),
all divided outputs’ rising (falling) edges are aligned to the rising
(falling) edges of the undivided, non-inverted outputs.
Regardless of PE setting, divide-by-4 outputs’ rising edges align
to the divide-by-2 outputs’ rising edges.
degrees phase aligned to the REF input rising edges (as set
randomly at power-up). If the divided outputs are required as
rising-edge (falling-edge) aligned to the REF input’s rising
(falling) edge, set the PE pin HIGH (LOW) and connect the
lowest frequency divided output to the FB input pin. This setup
provides a consistent input-output and output-output phase
relationship.
In cases where a non-divided output is connected to the FB input
pin, the divided output rising edges can be either 0 or 180
Document Number: 38-07337 Rev. *I
Page 14 of 19
CY7B995 RoboClock®
Ordering Information
Part Number
Package Type
Product Flow
Status
Pb-free
CY7B995AXI
44-pin TQFP
Industrial, –40 C to 85 C
Active
CY7B995AXIT
44-pin TQFP – Tape and Reel
Industrial, –40 C to 85 C
Active
Ordering Code Definitions
CY 7B995 A
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
A = 44-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07337 Rev. *I
Page 15 of 19
CY7B995 RoboClock®
Package Drawing and Dimension
Figure 6. 44-pin TQFP (10 × 10 × 1.0 mm) Package Outline, 51-85155
51-85155 *D
Document Number: 38-07337 Rev. *I
Page 16 of 19
CY7B995 RoboClock®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
ESD
Electrostatic Discharge
°C
degree Celsius
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
Hz
hertz
LVTTL
Low Voltage Transistor-Transistor Logic
PLL
Phase Locked Loop
TQFP
Thin Quad Flat Pack
VCO
Voltage-Controlled Oscillator
Document Number: 38-07337 Rev. *I
Symbol
Unit of Measure
kHz
kilohertz
MHz
megahertz
µA
microampere
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond

ohm
ppm
parts per million
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 17 of 19
CY7B995 RoboClock®
Document History Page
Document Title: CY7B995 RoboClock®, 2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07337
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
122626
01/10/03
RGL
New data sheet.
*A
205743
See ECN
RGL
Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29
from VDD to VDDQ1
Added pin 1 indicator in the Pin Configuration Drawing
*B
362760
See ECN
RGL
Added description on the AC Timing Waveforms
Added typical value for cycle-to-cycle jitter
*C
389237
See ECN
RGL
Added Lead-free devices
*D
1562063
See ECN
PYG /
AESA
Added Status column to Ordering Information table
*E
2892312
03/15/2010
CXQ
Added Table of Contents
Removed part numbers CY7B995AC, CY7B995ACT, CY7B995AI and
CY7B995AIT in ordering information table.
Updated package diagram (Figure 6)
Added Sales, Solutions, and Legal Information
*F
3162976
02/04/2011
CXQ
Added Ordering Code Definitions under Ordering Information.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*G
4312848
03/18/2014
CINM
Updated Package Drawing and Dimension:
spec 51-85155 – Changed revision from *B to *D.
Updated to new template.
Completing Sunset Review.
*H
4570146
11/14/2014
CINM
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*I
5257087
05/03/2016
PSR
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07337 Rev. *I
Page 18 of 19
CY7B995 RoboClock®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
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cypress.com/clocks
Interface
Lighting & Power Control
cypress.com/interface
cypress.com/powerpsoc
Memory
PSoC
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USB Controllers
Wireless/RF
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2003-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07337 Rev. *I
RoboClock is a registered trademark of Cypress Semiconductor Corporation.
Revised May 3, 2016
Page 19 of 19