Revised January 2004 MM74HC597 8-Bit Shift Registers with Input Latches General Description Features This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. ■ 8-bit parallel storage register inputs The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. the shift register also has direct load (from storage) and clear inputs. ■ Wide operating voltage range: 2V–6V ■ Shift register has direct overriding load and clear ■ Guaranteed shift frequency: DC to 30 MHz ■ Low quiescent current: 80 µA maximum The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number Package Number Package Description MM74HC597M (Note 1) M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC597SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC597N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD SCLR ↑ X X X ↑ X L H No clock Function Data Loaded to input latches Data loaded from inputs to shift register Data transferred from X L H edge input latches to shift register Invalid logic, state of X X L L shift register indeterminate X X H L Shift register cleared X ↑ H H when signals removed Top View © 2004 Fairchild Semiconductor Corporation DS005343 Shift register clocked Qn = Qn−1, Q 0 = SER www.fairchildsemi.com MM74HC597 8-Bit Shift Registers with Input Latches January 1988 MM74HC597 Functional Block Diagram (Positive Logic) Timing Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (VIN, VOUT) Operating Temperature Range (TA) 600 mW 500 mW Symbol VIH VIL VOH Parameter Conditions 0 VCC V −40 +85 °C 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 3: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics V Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units 6 (tr, tf) VCC = 2.0V Power Dissipation (PD) S.O. Package only Max 2 Input Rise or Fall Times −65°C to +150°C (Note 4) Min DC Input or Output Voltage ±70 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 5) TA = 25°C VCC Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 (Note 6) 6.0V 1.8 1.8 1.8 Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 Units V V V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA V 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 |IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8.0 80 160 µA V VIN = VIH or VIL IIN Maximum Input Current VIN = VCC or GND ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA V Note 5: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Note 6: VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89. 3 www.fairchildsemi.com MM74HC597 Absolute Maximum Ratings(Note 2) MM74HC597 AC Electrical Characteristics Symbol fMAX VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Parameter Conditions Maximum Operating Frequency of SCK tPHL Maximum Propagation tPLH Delay from SCK to QH tPHL Maximum Propagation tPLH Delay from SLOAD to QH tPHL Maximum propagation tPLH Delay from RCK to QH tPHL Maximum Propagation SLOAD = logic “0” Delay from SCLR to QH tREM Minimum Removal Time, SCLR to SCK tS Minimum Setup Time from RCK to SCK tS Minimum Setup Time from SER to SCK tS Guaranteed Typ Units Limit 50 30 MHz 20 30 ns 20 30 ns 25 45 ns 20 30 ns 10 20 ns 30 40 ns 10 20 ns 10 20 ns −2 0 ns 10 16 ns Minimum Setup Time from inputs A thru H to RCK tH Minimum Hold Time tW Minimum Pulse Width SCK, RCK, SCLR SLOAD AC Electrical Characteristics Symbol fMAX Parameter VCC = 2.0–6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Conditions VCC TA = 25°C TA=−40 to 85°C TA=−55 to 125°C Typ Guaranteed Limits Maximum Operating 2.0V 10 6.0 4.8 4.0 Frequency 4.5V 45 30 24 20 6.0V 50 35 28 24 tPHL Maximum Propagation 2.0V 62 175 220 263 tPLH Delay from SCK to QH 4.5V 20 35 44 53 6.0V 18 30 38 45 tPHL Maximum Propagation 2.0V 65 175 220 263 tPLH Delay from SLOAD to QH 4.5V 20 35 44 53 6.0V 18 30 38 45 2.0V 120 205 255 310 4.5V 30 41 51 62 6.0V 28 35 43 53 Maximum Propagatin 2.0V 66 175 220 263 Delay from SCLR to QH 4.5V 20 35 44 53 6.0V 18 30 38 45 tPHL Maximum Propagation tPLH Delay from RCK to QH tPHL tREM tS tS SLOAD = Logic “0” Minimum Removal Time 2.0V 100 125 150 SCLR to SCK 4.5V 20 25 30 6.0V 17 21 25 Minimum Setup Time 2.0V 200 250 300 from RCK to SCK 4.5V 40 50 60 6.0V 34 42 50 Minimum Setup Time 2.0V 100 125 150 from SER to SCK 4.5V 20 25 30 6.0V 17 21 25 www.fairchildsemi.com 4 Units MHz ns ns ns ns ns ns ns Symbol tS tH tW tr, tf tTHL, tTLH tTHL, tTLH CPD Parameter (Continued) Conditions TA = 25°C VCC 2.0V 100 125 150 from Inputs A thru H 4.5V 20 25 30 to RCK 6.0V 17 21 25 Minimum Hold Time 2.0V 0 0 0 4.5V 0 0 0 6.0V 0 0 0 Minimum Pulse Width 2.0V 30 80 100 120 SCK, RCK, SCLR, SLOAD 4.5V 9 16 20 24 6.0V 8 14 18 20 Maximum Input Rise and 2.0V 1000 1000 1000 Fall Time 4.5V 500 500 500 6.0V 400 400 400 Maximum Output 2.0V 30 75 95 110 Rise and Fall Time 4.5V 10 15 19 22 6.0V 8 13 16 19 110 Maximum Output 2.0V 75 95 Rise and Fall Time 4.5V 15 19 22 6.0V 13 16 19 Power Dissipation 87 Maximum Input Capacitance COUT Maximum Output Capacitance Units Guaranteed Limits Minimum Setup Time Capacitance, Outputs (Note 7) CIN TA=−40 to 85°C TA=−55 to 125°C Typ ns ns ns ns ns ns pF 5 10 10 10 pF 15 20 20 20 pF Note 7: CPD determines the no load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 2 5 www.fairchildsemi.com MM74HC597 AC Electrical Characteristics MM74HC597 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 MM74HC597 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com MM74HC597 8-Bit Shift Registers with Input Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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