TA1360AFG TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1360AFG YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV The TA1360AFG integrates an analog component signal (YCbCr/YPbPr) processor and sync processor in a 80-pin QFP plastic package. The IC is ideal for digital TVs, progressive TVs, and double scan TVs. The luminance block and the color difference block incorporate the high performance signal processing circuits. The sync processor block supports 525I/60, 625I/50, 525P/60, 625P/50, 1125I/50, 1125I/60, 750P/60, (750P/50), PAL100 Hz, NTSC120 Hz, and SVGA/60(VESA). The TA1360AFG incorporates the I2C bus. The device can control various functions via the bus line. Weight: 1.6 g (typ.) Features Luminance Block • Black stretch circuit and DC restoration rate correction circuit • Dynamic γ correction circuit (gray scale correction) • SRT (LTI) • Y group delay correction (shoot balance correction) • High-bright color circuit • Color detail enhancer (CDE) • White pulse limiter (WPL) • VSM output Color difference Block • Fresh color correction • Dynamic Y/C correction circuit • Color SRT (CTI) • Color γ circuit • Green stretch • Blue stretch Text Block • OSD blending SW • ACB (only black level) • Two analog RGB inputs Synchronization Block • Horizontal sync (15.75 k, 28.125 k, 31.5 k, 33.75 k, 37.9 k, 45 kHz) • Vertical sync (525I/P, 625I/P, 750P, 1125I/P, PAL 100 Hz/NTSC 120 Hz • 2- and 3-level sync separator circuit • HD/VD input (positive and negative polarities) • Copy guard • Vertical blanking 1 2003-01-21 TA1360AFG 68 Y/C VCC 75 Cr2/Pr2 IN Y1 IN 27 Cb2/Pb2 IN I2L GND 31 Y2 IN I2L VDD 38 Cb1/Pb1 IN DEF/DAC GND 45 Cr1/Pr1 IN DEF/DAC VCC Block Diagram 67 66 63 61 60 CLAMP CLAMP CP1 Y/C GND 65 SW YHDPbPr/YCbCrĺ YUV CONVERT U V Y BLACK UVĺ IQ STRETCH CONVERTER BLACK LEVEL FRESH CORECTION COLOR RGB VCC 16 RGB GND 10 SCL 30 2 SDA 28 DAC2 23 (ACB PLUSE) I CBUS DECODER SW IQĺ UV CONVERTER DYNAMIC γ SW DC REST DAC2 DAC1 (SYNC OUT) 34 SYNC OUT SW DAC1 CP OUT 47 SCP IN 49 H-OUT 37 H-FREQ SW1 55 H-FREQ SW2 41 EXT BPP CP/BPP H FREQUENCY SW AFC FILTER 44 SRT GROUP DELAY + CORRECTION TINT H C/D CP2 HVCO CLAMP PULSE DL/ COLOR SRT CP SW H-AFC COLOR SUBCONTRAST UNI-COLOR UNICOLOR FBP/BLK V-BPP LIGHT DET LIGHT AREA 64 DET FILTER 74 APL FILTER SHARPNESS CONTROL Y DETAIL CONTROL G-Y MATRIX V FREQUENCY SW R-Y H-BLK + ABCL AMP V-BLK HI-BRIGHT COLOR G-Y Yout-γ HALF TONE /C MUTE HALF TONE /Y MUTE 58 COLOR LIMITER HPF VSM AMP COLOR PEAK DETECT V-CLP WP BLUE VSM MUTE CLAMP VD IN SW R OUT 12 CLAMP OSD AMP Y RGB MATRIX CP2 BLK CP2 DRIVE MIXER SW/ BLUE BACK OSD ACL SW BLUE STRETCH CP2 B OUT 14 SW S/H RGB BRIGHTNESS CLAMP 57 VSM FILTER 77 VSM OUT 18 ANALOG OSD R IN 19 ANALOG OSD G IN 21 ANALOG OSD B IN OR 80 YS1 (ANALOG OSD) CUT OFF IK 78 ABCL IN WPS COLOR γ EXT V-BLK HD IN SW BRIGHTNESS B-Y ACB PULSE CLAMP PULSE HD POLARITY CLAMP WPL V C/D SYNC SEPA RELATIVE PHASE/ AMPLITUDE 2 × fH H-RAMP VP OUT RGB OUT 71 DARK AREA DET FILTER APL DETECT CP2 G OUT 13 DARK DET CP2 H-BPP V INTEGRAL VD IN 52 70 BPH FILTER CDE + H CURVE 40 CORRECTION FBP IN 39 + CP1 H CURVE CORRECTION HD IN 50 GREEN STRETCH EXT CP HORIZONTAL PHASE SYNC IN 53 SHARPNESS DELAY LINE H DUTY HVCO 42 VP OUT 35 BPP SW Y/C LEVEL COMP BLACK PEAK DETECT YM SW CLAMP 1 YS2 (ANALOG OSD) 2 G S/H B S/H 25 26 2 79 YM/PMUTE/BLK R S/H 24 YS3 (ANALOG RGB) 7 ANALOG B IN 6 ANALOG G IN 4 ANALOG R IN 8 IK IN RGB CONTRAST 2003-01-21 TA1360AFG 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 YS1 (ANALOG OSD) YM/PMUTE/BLK ABCL IN VSM OUT NC Y/C VCC APL FILTER NC NC DARK AREA DET FILTER BPH FILTER NC Y1 IN Cb1/Pb1 IN Cr1/Pr1 IN Y/C GND Pin Assignment 1 YS2 (ANALOG OSD) 2 YS3 (ANALOG RGB) 3 NC LIGHT AREA 64 DET FILTER Y2 IN 63 NC 62 4 R S/H Cb2/Pb2 IN 61 5 NC Cr2/Pr2 IN 60 6 G S/H NC 59 7 B S/H COLOR LIMITER 58 8 IK IN VSM FILTER 57 9 NC NC 56 10 RGB GND H-FREQ SW1 55 11 NC NC 54 12 R OUT SYNC IN 53 TA1360AFG 13 G OUT VD IN 52 14 B OUT NC 51 15 NC HD IN 50 16 RGB VCC SCP IN 49 17 NC NC 48 18 ANALOG OSD R IN CP OUT 47 19 ANALOG OSD G IN NC 46 20 NC DEF/DAC VCC 45 21 ANALOG OSD B IN AFC FILTER 44 22 NC NC 43 23 DAC2 (ACB PULSE) I2L GND SDA NC SCL I2L VDD NC NC DAC1 (SYNC OUT) VP OUT NC H-OUT DEF/DAC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 3 H-FREQUENCY SW2 41 H COURVE CORRECTION ANALOG B IN 25 24 ANALOG R IN FBP IN ANALOG G IN HVCO 42 39 40 2003-01-21 TA1360AFG Pin Functions Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit Switches internal RGB and OSD input signals. The blend ratio of internal RGB and OSD signals can be adjusted according to applying voltage to pins YS1 and YS2. YS2 (analog OSD) VSM output is muted when YS1 or YS2 pin is set to High. YS2 YS1 80 YS1 (analog OSD) 300 Ω 1 80 Blend ratio Int RGB: OSD RGB L L 10:0 H L 7:3 L H 5:5 H H 0:10 0 to 0.5 V : Internal 1.1 V to 1.7 V : VSM Mute 50 kΩ 1 16 2.9 V to 9 V : OSD, VSM Mute 10 16 YS3 (analog RGB) 2 VSM output is muted when analog RGB is selected. 300 Ω 0 to 0.5 V 300 Ω 1.5 V to 9 V : Analog RGB, VSM Mute This pin is not used. 3 50 kΩ 2 Switches internal RGB and external analog RGB input. : Internal 10 NC Connect to GND. 16 R S/H S/H (sample-and-hold) pin. G S/H 7 B S/H In ACB Mode, connect 2.2-µF capacitor. In CUT-OFF Mode, connect 0.01-µF capacitor. 1 kΩ 5 kΩ DC 3V 6 500 Ω 4 6 7 3 pF 4 10 This pin is not used. 5 NC Connect to GND. 16 1 Vp-p (typ.) R Inputs feedback signal from CRT. (BLK level should be 0 to 3 V.) 8 IK IN When ACB function is not used, connect this pin to RGB VCC pin. 1 kΩ 8 G B 0~3 V or RGB VCC 10 This pin is not used. 9 NC Connect to GND. 10 RGB GND 11 NC GND pin for text/RGB block This pin is not used. Connect to GND. 4 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 12 100 Ω 16 R OUT Outputs R/G/B signal. G OUT 14 B OUT Recommended output amplitude: 100 IRE = 2.3 Vp-p Conditions: 12 13 14 200 Ω UNI-COLOR = max SUB-CONT = Cent 2.5 mA 13 100 IRE: 2.3 Vp-p Y IN = 0.7 Vp-p 10 This pin is not used. 15 NC Connect to GND. VCC pin for text/RGB block. 16 RGB VCC 17 NC See “Maximum Ratings” about the supply voltage. This pin is not used. Connect to GND. 16 18 19 21 ANALOG OSD R IN ANALOG OSD G IN Inputs analog OSD signal via clamp capacitor. 1 kΩ 18 19 21 100 IRE: 0.7 Vp-p (not including sync) 1 kΩ 1 kΩ ANALOG OSD B IN 10 20 This pin is not used. NC 22 Connect to GND. 16 DC or ACB PULSE 23 DAC2 (ACB pulse) Outputs 1-bit DAC or pulse over ACB period. 500 Ω 23 Open-collector output. 10 16 24 ANALOG R IN 25 ANALOG G IN 26 ANALOG B IN Inputs analog R/G/B signal via clamp capacitor. 1 kΩ 24 25 26 100 IRE: 0.7 Vp-p (not including sync) 1 kΩ 1 kΩ 10 27 I2L GND GND pin for I2L block 5 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 45 SDA SDA pin for I2C BUS 50 Ω 28 5 kΩ SDA 2.25 V 28 ACK 38 27 This pin is not used. 29 NC Connect to GND. 45 SCL SCL pin for I2C BUS 5 kΩ 30 SCL 2.25 V 30 38 27 VDD pin for I2L block. Connects 2 V (typ.). 31 I2L VDD 32 Supply power via zener diode through resistor from pin 45. (See “Application Circuit”) This pin is not used. NC 33 Connect to GND. 45 34 DAC1 (SYNC OUT) Outputs 1-bit DAC or separated SYNC. 34 DC or SYNC OUT 500 Ω Open-collector output. 27 38 35 VP OUT Applying current to this pin, performs external blanking by OR-ing with internal blanking. 35 200 Ω 5V 0V Note: Changing H-position varies VP output width. Use the start phase only for VP output. 27 Start phase 38 This pin is not used. 36 VP output: 200 µA 45 Outputs vertical pulse. NC Connect to GND. 6 V-BLK input current: 780 µA to 1 mA 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 45 37 H-OUT Horizontal output pin. Open-collector output. 5 kΩ 37 38 38 DEF/DAC GND GND pin for DEF/DAC block 2.25 V 45 max: 9 V Inputs FBP for horizontal AFC. 39 FBP IN Sets H-BLK width. H-AFC threshold : 5.3 V BLK threshold : 2.3 V 20 kΩ 39 5V 30 kΩ 500 Ω 38 H CURVE CORRECTION 50 kΩ Adjusts screen curve at high voltage fluctuation. Input AC component of high voltage fluctuation. 1 kΩ 40 DC 25 kΩ When not used, connect 0.01-µF capacitor between this pin and GND. 6.5 V 130 kΩ 40 65 kΩ 45 38 1 kΩ 45 H-FREQ SW2 60 kΩ 60 kΩ 15 kΩ 41 Leave this pin open when horizontal frequency is switched by Bus controlling. Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) 60 kΩ Switches horizontal frequency (Switch 2). 1 kΩ 41 30 kΩ 20 pF When this IC is used for CRT, frequency of horizontal output (pin 37) is controlled according to voltage of this pin. DC voltage that is generated by dividing resistor of DEF VCC (pin 45) should be used to control this pin. 7.5 V 4.5 V At pin 22 control, horizontal frequency and input voltage value 0 to 1.0 V : 37 k/45 kHz 2.0 V to 4.0 V : 33 kHz 5.0 V to 7.0 V : 31 kHz 8.0 V to 9.0 V : 28 k/15 kHz 16 kΩ 1.5 V At BUS control (horizontal frequency) : output voltage value 28 k/15 kHz : DC 9 V 31 kHz : DC 6 V 33 kHz : DC 3 V 37 k/45 kHz : DC 0 V 38 42 2 kΩ Connects ceramic oscillator for horizontal oscillation. HVCO Use Murata “CSBLA503KECZF30”. 1 kΩ 45 42 1 kΩ 10 kΩ 38 This pin is not used. 43 NC Connect to GND. 7 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 45 300 Ω 30 kΩ Connects filter for detecting AFC. VCO DC 6.3 V AFC FILTER 7.5 kΩ 44 44 38 VCC pin for DEF/DAC block. 45 DEF/DAC VCC 46 NC See “Maximum Ratings” about the supply voltage. This pin is not used. Connect to GND. 45 5V CP OUT 47 200 Ω 2.5 kΩ 47 Outputs internal clamp pulse (CP). 0V 38 This pin is not used. 48 NC Connect to GND. 45 SCP IN Inputs SCP from up converter. Input signals are clamp pulse (CP) and black peak detection stop pulse (BPP). 2.2 V to 2.8 V : BPP 5 kΩ 49 4.2 V to 9 V : CP 50 kΩ 49 38 45 Threshold : 0.75 V 0V HD IN 50 1 kΩ or 50 kΩ 50 Inputs horizontal sync HD signal. Inputs positive- or negative-polarity signals. Threshold : 0.75 V 38 0V This pin is not used. 51 NC Connect to GND. 45 Threshold : 0.75 V 0V VD IN 52 1 kΩ or 45 kΩ 52 Inputs vertical sync VD signal. Inputs positive- or negative-polarity signals. 38 Threshold : 0.75 V 0V 8 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit White 100%: 1 Vp-p 45 1 kΩ Inputs Y signal with sync signal via clamp capacitor. or 53 1 kΩ SYNC IN 1 kΩ 60 kΩ 53 38 This pin is not used. 54 NC Connect to GND. Switches horizontal frequency (Switch 1). 45 1 kΩ 55 This pin is not used. 56 DEF VCC or DEF GND 30 kΩ When this IC is used for CRT, connect this pin to DEF VCC (pin 45) or DEF GND (pin 38). If it is not necessary to control this pin on CRT, connect this pin directly to DEF VCC or DEF GND on the PCB. NC 57 Connects VSM output filter. 16 DC Please connect 0.01-µF capacitor between this pin and GND. 200 Ω 77 1 kΩ VSM FILTER 200 Ω 1 kΩ Connect to GND. 57 38 1.6 mA H-FREQ SW1 Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) 50 kΩ 55 50 µA Leave this pin open when horizontal frequency is switched by Bus controlling. 65 7 µA 16 58 COLOR LIMITER Connects filter for detecting color limit. 5 kΩ 58 DC 65 This pin is not used. 59 NC Connect to GND. 9 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 60 Cr2/Pr2 IN Inputs Cr2/Pr2 signal via clamp capacitor. 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 61 Cb2/Pb2 IN Inputs Cb2/Pb2 signal via clamp capacitor. 700 mVp-p at 100% color bar for Cb1/Pb1 16 60 61 63 1 Vp-p (including sync) at 100% color bar 1 kΩ 1 kΩ 5 kΩ 63 Y2 IN Inputs Y2 signal via clamp capacitor. or 65 This pin is not used. 62 NC Connect to GND. 75 Connects filter for detecting light area. 5 kΩ 64 Voltage of this pin controls dynamic γ circuit gain for light area. DC 1 kΩ 1 kΩ LIGHT AREA DET FILTER 100 kΩ 64 65 65 Y/C GND GND pin for Y/C block 66 Cr1/Pr1 IN Inputs Cr1/Pr1 signal via clamp capacitor. 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 67 Cb1/Pb1 IN Inputs Cb1/Pb1 signal via clamp capacitor. 700 mVp-p at 100% color bar for Cb1/Pb1 16 66 67 68 1 Vp-p (including sync) at 100% color bar 1 kΩ 1 kΩ 5 kΩ 68 Y1 IN Inputs Y1 signal via clamp capacitor. 65 This pin is not used. 69 NC Connect to GND. 10 or 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 1 kΩ 75 Voltage of this pin controls black stretch gain. 200 Ω 70 DC 5V Leaving Y open and setting the test circuit SW 2 = C enable to monitor H/V-BPP (black-stretch-stop pulse) width. 1 kΩ BPH FILTER 1 kΩ 70 4 kΩ Connects filter for detecting black peak. 65 75 5 kΩ 71 DC 1 kΩ 1 kΩ 100 kΩ 71 Connects filter for detecting dark area. DARK AREA DET Voltage of this pin controls FILTER dynamic γ circuit gain for dark area. 65 72 This pin is not used. NC 73 Connect to GND. 75 40 kΩ Connects filter for correcting DC restoration rate. 74 APL FILTER 74 1 kΩ Leaving this pin open enables to monitor Y signal after black stretch and dynamic γ. 1 kΩ 65 VCC pin for Y/C block. 75 Y/C VCC 76 NC See “Maximum Ratings” about the supply voltage. This pin is not used. Connect to GND. 77 VSM OUT Outputs Y signal for VSM that passed through HPF circuit (first differential circuit). See pin 57. Output signals are muted according to pins 1, 2, and 80. 7.05 V 16 Inputs ABL and ACL signals. 78 ABCL IN Sets gain and start point of ABL and dynamic ABL signal according to bus controlling. 30 kΩ 5 kΩ DC 78 10 11 2003-01-21 TA1360AFG Pin No. Pin Name Function Input Signal/Output Signal Interface Circuit 16 YM/P-MUTE/BLK 0 to 0.5 V Enables picture mute and blanking. : Internal 1.2 V to 1.8 V : Half Tone 2.7 V to 4.0 V : P-Mute 7 V to 9 V 10 kΩ 79 300 Ω 79 80 kΩ High-speed halftone switch for internal RGB signal. : Blanking 10 12 2003-01-21 TA1360AFG Bus Control Map Write Data Slave Address: 88H Sub-Add D7 00 D6 H-FREQ1 D5 D4 D3 D2 D1 D0 H-DUTY YUV-SW DAC1 DAC2 SYNC-SW H-FREQ2 1000 0000 CLP-PHS 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 01 HORIZONTAL POSITION 02 ACB-MODE 03 HBP-PHS1 TEST VERTICAL FREQUENCY COMPRESSION-BLK PHASE-1 COMPRESSION-BLK PHASE-2 P-MODE1 UNI-COLOR 06 07 SYNC SEP-LEVEL V-BLK PHASE 04 05 SCP-SW BRIGHTNESS OSD-ACL COLOR Preset 08 TINT HBP-PHS2 1000 0000 09 PICTURE SHARPNESS BLS γ 1000 0000 0A RGB BRIGHTNESS DCRR-SW 1000 0000 1000 0000 Y-OUT γ 1000 0000 0B HI BRT RGB CONTRAST 0C SUB CONTRAST WPS YUV MODE 0D DRIVE GAIN1 DR-R 1000 0000 0E DRIVE GAIN2 DR-B/G 1000 0000 0F R CUT OFF 1000 0000 10 G CUT OFF 1000 0000 11 B CUT OFF 1000 0000 1000 0000 12 R-Y/B-Y GAIN 13 R-Y/B-Y PHASE G-Y/B-Y GAIN 14 COLOR SRT TRAN 15 C.D.E. C FREQ G-Y/B-Y PHASE Y/C GAIN COMP 1000 0000 CLT 1000 0000 H-SHIFT 1000 0000 COLOR γ GREEN STRETCH BL STRETCH GAIN FLESH 16 VSM PHASE VSM GAIN APACON PEAK FREQ 1000 0000 17 DC REST POINT DC REST RATE DC REST LIMIT 1000 0000 18 BLACK STRETCH POINT 1000 0000 1000 0000 P-MODE2 1000 0000 ABL GAIN RGB OUT MODE 1000 0000 STATIC γ GAIN-1 STATIC γ GAIN-2 1000 0000 19 APL VS BSP B.L.C. B.D.L SRT-GAIN 1A D-ABL POINT 1B WPL-LEVEL D-ABL GAIN ABL POINT 1C DYNC γ GAIN 1D OSD BRIGHT BS-AREA BS-CHAR1 OSD CONTRAST BL STRETCH POINT Y/C-DL1 DYNC γ AREA 1000 0000 1E Y DETAIL CONTROL BS-CHAR2 WP BLUE POINT 1000 0000 1F Y GROUP DELAY CORRECTION Y/C-DL2 WP BLUE GAIN 1000 0000 Read Data Slave Address: 89H 0 D7 D6 D5 D4 D3 D2 D1 D0 POR IK-IN RGB-OUT YUV-IN H-OUT VP-OUT RGB-IN SYNC-IN 13 2003-01-21 TA1360AFG Bus Control Features Write Mode Resister Name H-FREQ1/2 H-DUTY YUV-SW Description Switches horizontal oscillation frequency. (See the appendix 1) Switches horizontal output duty. 33.75 kHz 41% 0: 41% 1: 47% Switches YUV input. 0: INPUT-1 (Y1/Cb1/Cr1) Preset Value 1: INPUT-2 (Y2/Cb2/Cr2) INPUT-1 Switches DAC controlling output. DAC 1 0: OPEN (high) 1: ON (low) Controls 1-bit DAC of open-collector when TEST is 00. OPEN Outputs H/C-SYNC from pin 34 when TEST is 01. Switches DAC controlling output. DAC 2 0: ON (low), 1: OPEN (high) Controls 1-bit DAC of open-collector when TEST is 00. ON Outputs ACB reference pulse from pin 23 when TEST is 01. SYNC-SW Switches sync input. 0: Selects HD/VD input. 1: Selects SYNC input. HD/VD Adjusts horizontal picture position (phase). HORIZONTAL POSITION 0000000: −12.5% 1111111: +12.5% CENTER Note: VP output width (pin 35) varies with a change of horizontal position. Switches clamp pulse phase. 0: 0.7-µs (2.5%) width, 1.1-µs (3.8%) delay from HD stop phase. CLP-PHS 1: 0.7-µs (2.4%) width, 0.2-µs (0.7%) delay from HD stop phase 1.1-µs delay when no signal, 0.8-µs (2.7%) width that is 1.2-µs (4.2%) delay from FBP start phase. Also switches CP phase of CP-OUT (pin 47). Sets ACB mode; Sets converged reference level. ACB MODE 00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE), 10: ACB ON (10 IRE) 11: ACB ON (20 IRE) SCP-SW SCP (sand castle pulse) Switches modes. 0: Internal Mode 1: External input Mode ACB ON (10 IRE) Internal Mode Switches phase of black-stretch-detection stop pulse. HBP-PHS1 = 0 and HBP-PHS2 = 0: FBP ± 3% HBP-PHS1 = 0 and HBP-PHS2 = 1: FBP ± 8% HBP-PHS1/2 HBP-PHS1 = 1 and HBP-PHS2 = 0: FBP ± 13% ±3% HBP-PHS1 = 1 and HBP-PHS2 = 1: FBP ± 18% Leaving Y open and setting the test circuit SW2 to C enable to monitor H/V-BPP (black-stretch-detection stop pulse) width through pin 70. SYNC SEP-LEVEL Switches Sync SEP-level. 00: 16% 01: 24% 10: 32% 11: 40% (At 1125I/60) 16% Test Mode: Controls 1-bit DAC of open-collector when TEST is 00. TEST Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST 00 is 01. Do not set TEST to 10/11 for that is shipment TEST Mode. 14 2003-01-21 TA1360AFG Resister Name Description Preset Value Switches vertical BLK stop phase. V-BLK PHASE 00000: 16 H~ 11110: 46 H (1 H/STEP) 11111: Internal H/V-BLK OFF 32 H Please set ACB Mode to OFF when internal H/V-BLK is OFF (11111). V-FREQUENCY Vertical free-run frequency: Sets V pull-in range. (See Appendix 2.) 1281 H COMPRESSION-BLK PHASE-1/2 Compression BLK phase: Sets BLK for upper and lower parts of screen. (See Appendix 3.) CENTER, OFF P-MODE1/2 Picture Mode: Sets picture mute, halftone, blue background, and Y mute. (See Appendix 4.) P-MUTE 1 UNI-COLOR BRIGHTNESS OSD-ACL Unicolor adjustment: 0000000: −16dB~ 1111111: 0dB Brightness adjustment: 00000000: −40 IRE 11111111: +40 IRE OSD-ACL; min CENTER ON 0: OFF 1: ON Color adjustment: COLOR 0000000: COLOR MUTE, C-MUTE 0000001: −20dB or more 1111111: +4dB TINT Tint adjustment: 0000000: −32 deg~ 1111111: +32 deg ±0 deg Sharpness adjustment: PICTURE-SHARPNESS 0000000: −10dB or more 1000000: +10dB CENTER 1111111: +17.5dB (at peak FREQ) BLSγ RGB-BRIGHTNESS DCRR-SW HI BRT RGB-CONTRAST SUB-CONTRAST WPS Blue stretch γ correction: B-axis correction 0: OFF 1: ON RGB brightness: 0000000; −20 IRE~ 1111111; +20 IRE Switches DC restoration rate. 0: 100% or higher 1: 100%or lower High-bright color: RGB contrast: 0000000: −16.5dB 1111111: 0dB Sub-contrast: 100% or higher min CENTER 11111: +2.5dB WPS level: 0: 110 IRE CENTER ON 0: OFF 1: ON 00000: −3.3dB OFF 110 IRE 1: 130 IRE Y/color-difference input Mode: YUV MODE 0: Y/Cb/Cr, 1: Y/Pb/Pr Y/Cb/Cr (Remarks) Y/Cb/Cr: ITU-R BT 601 Y/Pb/Pr: ITU-R BT 709 (1125/60/2:1) Y-outγ DRIVE GAIN1/2 DR-R DR-B/G Ｙ-out gamma control: OFF 0: OFF 1: ON Drive gain 1/2; 0000000: −5dB 1111111: +3dB Switches RGB drive gain base. (See Appendix 5.) 15 CENTER R 2003-01-21 TA1360AFG Resister Name Description Preset Value R/G/B cutoff: 1) At ACB-OFF RGB-OUT R/G/B CUT OFF 00000000: 1.9 V 11111111: 2.9 V CENTER 2) At ACB-ON SENS-IN 00000000: 0.5 Vp-p 11111111: 1.5 Vp-p R-Y/B-Y GAIN R-Y/B-Y PHASE G-Y/B-Y GAIN G-Y/B-Y PHASE COLOR SRT TRAN C FREQ GREEN STRETCH COLOR γ CLT CDE Y/C GAIN COMP Switches R-Y/B-Y relative amplitude: CENTER 0000: min (0.45) 1111: max (0.9) Switches R-Y/B-Y relative phase: min 0000: min (90 deg) 1111: max (111.5 deg) Switches G-Y/B-Y relative amplitude: CENTER 0000: min (0.25) 1111: max (0.48) Switches G-Y/B-Y relative phase: min 0000: min (232 deg) 1111: max (254 deg) Color SRT transient: Color-difference transient improvement 00: C-SRT OFF~ 11: max Color SRT peak frequency: 0: 4.5 MHz 4.5 MHz 1: 5.8 MHz Green stretch: OFF 00: OFF~ 11: max (+3dB) Color γ correction point 00: OFF, CENTER 01: 0.23 Vp-p, 10: 0.40 Vp-p, 11: 0.58 Vp-p Color limiter level: OFF 1.65 Vp-p 0: 1.65 Vp-p, 1: 2 Vp-p Color detail enhancer: CENTER 00: min 11: max Dynamic Y/C compensation: Operated when luminance level is made up according to dynamic Yγ. OFF 00: OFF~ 11: max BL STRETCH GAIN FLESH H-SHIFT VSM-PHASE VSM GAIN APACON PEAK f0 DC REST POINT DC REST RATE DC REST LIMIT Blue stretch gain: B-axis correction OFF 00: OFF 11: max (+6.4dB) Flesh color: Skin tone color correction OFF 0: OFF 1: ON (Lead-in angle: ±33.7 deg) Shifts a center of horizontal picture position (phase): 0: OFF 1: ON（FBP shifts 6.7% against HD） VSM phase: 000: −37.5 ns 101: normal CENTER 111: +15 ns VSM gain: 000: OFF 001: 0 dB~ 111: +16dB (VSM gain is limitted 1.4 Vp-p) APACON peak frequency: 00: 13.5 MHz 01: 9.5 MHz 10: 7.2 MHz DC restoration rate correction point: 000: 0% 111: 49% DC restoration correction rate: 11: 4.5 MHz OFF 13.5 MHz CENTER min 000: 100% 111: 135% (70%) DC restoration rate correction limit point: 00: 67% 01: 77％ OFF 10: 80% 11: 80% 16 min 2003-01-21 TA1360AFG Resister Name BLACK STRETCH POINT APL VS BSP B.L.C B.D.L. BS-AREA SRT-GAIN WPL-LEVEL D-ABL POINT D-ABL GAIN BL STRETCH POINT ABL POINT ABL GAIN RGB-OUT MODE Description Black stretch start point 1: 000: OFF 001: 25 IRE~ 111: 55 IRE Black stretch start point 2: 00: 0 IRE 11: 46 IRE up (at APL 100%) Black level automatic correction: Up to 6.5 IRE. (Black stretch takes priority.) 0: OFF 1: ON Switches black detection level: 0: 3 IRE CENTER 0 IRE OFF 3 IRE 1: 0 IRE Black stretch area reinforcement: ON 0: ON 1: OFF SRT gain; Y transient improvement (LTI) 00000: min 11111: max White letters improvement amplitude; 000: min (21 IRE) ~ 110: max (102 IRE) 111: OFF Dynamic ABL detection voltage CENTER min CENTER 00: min 11: max Dynamic ABL sensitivity min 00: min 11: max Blue stretch point; B-axis correction min 00: min (28 IRE) 11: max (60 IRE) ABL detection voltage CENTER 000: min 111: max ABL sensitivity min 000: min 111: max RGB output mode; RGB output mode SW for test and adjustment 00: Normal Preset Value 01: R only 10: G only 11: B only Normal Dynamic Yγ gain vs dark area; dynamic γ-correction according to dark area. DYNCγ GAIN 00:min~ 11: max (Maximum gain is +6dB included Static Yγ gain for dark area.) CENTER Black stretch characteristic swich BS-CHAR1/2 BS-CHAR1 = 0 and BS-CHAR2 = 0: OFF BS-CHAR1 = 0 and BS-CHAR2 = 1: min BS-CHAR1 = 1 and BS-CHAR2 = 0: mid BS-CHAR1 = 1 and BS-CHAR2 = 1: max OFF Static Yγ dark area gain; γ correction for dark area STATICγ GAIN-1 000: OFF 001: min (−5dB) ~ 11: max (+2.4dB) OFF Note: When STATIC γ GAIN-1 is 000(OFF), set DYNC γ GAIN to min (00), STATIC γ GAIN-2 to OFF (11), and DYNC γ AREA to min (000). Static Yγ light area gain; γ correction for light area STATICγ GAIN-2 00: max (−8.8dB)~ 11: OFF max When 00~10 is set, light area static Yγ and light dynamic Yγ according to light area is operated. OSD BRIGHT OSD-CONTRAST OSD brightness: 00: 5 IRE 01: 0 IRE 10: −5 IRE OSD contrast: 00: min (−9.5dB) 11: max (0dB) 17 11: −10 IRE −5 IRE min 2003-01-21 TA1360AFG Resister Name Description Preset Value Adjusts Y/C phase; adjusts the phase Y before passing through matrix circuit. Y/C DL1/2 Y/C DL2 = 0 and Y/C DL1 = 0: −10 ns, Y/C DL2 = 0 and Y/C DL1 = 1: −5 ns −10 ns Y/C DL2 = 1 and Y/C DL1 = 0: 0 ns, Y/C DL2 = 1 and Y/C DL1 = 1: +5 ns DYNCγAREA Y DETAIL CONTROL WP BLUE POINT Dynamic γ dark area detection sensitivity; switches detection sensitivity of dynamic Yγ of dark area. min 000: min~ 111: max Controls Y detail; corrects sharpness of 5.0-MHz peak frequency. 0000:min (trap) 1111: max（+6dB） White peak blue point; 000: OFF 001: min (42 IRE) ~ 111: max (106 IRE) CENTER OFF Y group delay correction; shoot balance correction. Y-GROUP DELAY CORRECTION 0000: Pre-shoot gain is lowered. (Overshoot gain is raised.) CENTER 1111: Overshoot gain is lowered. (Pre-shoot gain is raised.) WP BLUE GAIN White peak blue gain. 000: min (+3dB) 111: max (+10dB) 18 min 2003-01-21 TA1360AFG Appendix 1: Horizontal Frequency Pin Voltages (V) Pin 55 DEF GND (0~1.0) DEF VCC (8.0~9.0) Bus Data H-Frequency (kHz) Pin 41 00-D0 00-D7 00-D6 DEF VCC (8.0~9.0) 0 0 0 28.125 6.0 (5.0~7.0) 0 0 1 31.5 3.0 (2.0~4.0) 0 1 0 33.75 DEF GND (0~1.0) 0 1 1 37.9 DEF VCC (8.0~9.0) 1 0 0 15.75 6.0 (5.0~7.0) 1 0 1 31.5 3.0 (2.0~4.0) 1 1 0 33.75 DEF GND (0~1.0) 1 1 1 45 Note 1: Controlling pins prevails over BUS control. When the TA1360F is used for CRT, control horizontal oscillation frequency by pins 41 and 55. (See the pin descriptions for details.) Note 2: Horizontal output frequency may not be switched at once but may takes two steps if switching pins 41 and 55 is controlled at the same time. Switching horizontal output frequency may cause deterioration of the horizontal transistor. Thus, be sure to take account of applications, included software. Appendix 2; Vertical Frequency V-BPP Data V Pull-in Range 000 48~1281 H 1100 H 1125P/30 Hz (33.75 kHz) 001 48~849 H 730 H 750P/60 Hz (45 kHz) (750P/50Hz(37.5 kHz)) 010 48~725 H 600 H 625P/50 Hz (31.5 kHz) SVGA/60 Hz(37.9 kHz) 011 48~660 H 545 H 100 48~613 H 500 H 525P/60 Hz (31.5 kHz) 101 48~363 H 290 H PAL/SECAM/50 Hz (15.625 kHz), 100 Hz (31.5 kHz) 110 48~307 H 240 H NTSC/60 Hz (15.734 kHz), 120 Hz (31.5 kHz) 111 VP-OUT HI Start Phase Stop Phase V-BLK P. (C.BLK P.) +20 H 19 Example of Format/V (H)-Frequency 1125I/50 Hz (28.125 kHz) 1125I/60 Hz (33.75 kHz) 2003-01-21 TA1360AFG Appendix 3; Compression-BLK Phase V-Frequency Phase-1 (start phase) * 000 1088 H~1116 H 001 720 H~748 H 010 592 H~620 H 011 528 H~556 H 100 488 H~516 H 101 280 H~308 H 110 224 H~252 H 111 Phase-2 (stop phase) 50~78 H (0000: C-BLK2 OFF) C-BLK OFF *: C-BLK1 = 1111: C-BLK1 OFF Appendix 4; P-Mode 05-D7 1A-D1 1A-D0 MODE Description P-Mute and halftone the main signal by pin YM. 0 0 0 NORMAL 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-mute process is executed on Y of main signal by BUS. 0 0 1 Y-MUTE Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 0 1 0 YM 1 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal. Analog RGB-IN > P-Mute Blue background process is executed on main signal by BUS. 0 1 1 BB Insert P-Mute by pin YM, analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2 Analog RGB-IN > P-Mute Full-screen-mute process is executed on main signal by BUS. 1 0 0 P-MUTE 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 1 0 1 YM 2 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal P-Mute > Analog RGB-IN Full-screen-mute process is executed on main signal and analog RGB-IN by BUS. 1 1 0 P-MUTE 2 Insert OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN P-Mute and halftone process is executed on the main signal by pin YM. 1 1 1 NORMAL 2 Analog RGB-IN is inserted by Ys3, and OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN Output priority; (000)~(100): Main signal < BB < P-MUTE < RGB-IN < OSD-IN (101)~(111): Main signal < BB < RGB-IN < P-MUTE < OSD-IN 20 2003-01-21 TA1360AFG Appendix 5; DR-R, DR-B/G DR-R DR-B/G Reference Axis Drive Gain1 Drive Gain2 0 0 R G B 0 1 R G B 1 0 G R B 1 1 B G R Read Function Signal Function Power-on reset: POR 0: RESISTER PRESET 1: Normal After power on, 0 is returned at first read; 1, at second and subsequent reads. IK-IN Detects IK input; detects input through pin 8. 0: NG (no signal) 1: OK (signal detected) Detects RGB-OUT self-check; detects output of pins 12, 13, 14. RGB-OUT 0: NG (no signal) 1: OK (signal detected) Detects signal when all three outputs hsve signals. Small signals are not detected. Detects YUV-IN self-check; detects input of pins 60, 61 63 or pins 66, 67, 68. YUV-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. H-OUT VP-OUT Detects H-OUT self-check; detects output of pin 37. 0: NG (no signal) 1: OK (signal detected) Detects VP-OUT self-check; detects output of pin 35. 0: NG (no signal) 1: OK (signal detected) Detects RGB-IN self-check; detects input of pins 24, 25, 26. RGB-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. SYNC-IN Detects SYNC-IN self-check; detects input of pin 53. 0: NG (no signal), 1: OK (signal detected) 21 2003-01-21 TA1360AFG How to Transmit/Receive Via I2C Bus Slave Address: 88H A6 A5 A4 A3 A2 A1 A0 W/R 1 0 0 0 1 0 0 0/1 Start and Stop Conditions SDA SCL S P Start condition Stop condition Bit Transfer SDA SCL SDA must not be changed SDA may be changed Acknowledgement SDA from transmitter High impedance at bit 9 SDA from receiver Low impedance only at bit 9 SCL from master 1 8 9 S Clock pulse for acknowledgement 22 2003-01-21 TA1360AFG Data Transmit Format 1 S Slave address 7 bit MSB S: Start condition 0 A Sub address 8 bit A MSB A: Acknowledgement Transmit data 9 bit A P MSB P: Stop condition Data Transmit Format 2 S Slave address 0 A Sub address ･･････ A Transmit data 1 Sub address A A ･･････ Transmit data n A P Data Receive Format S Slave address 7 bit MSB 1 A Transmit data 1 8 bit A Receive data 2 A P MSB To receive data, the master transmitter changes to the receiver immediately after the first acknowledgement. The slave receiver changes to the transmitter. The stop condition is always created by the master. Details are provided in the Philips I2C specifications. Optional Data Transmit Format S Slave address 7 bit MSB 0 A 1 MSB Sub address 7 bit A Transmit data 1 8 bit MSB ････ Transmit data n 8 bit A P MSB In this way, sub addresses are automatically incremented from the specified sub address and data are set. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 23 2003-01-21 TA1360AFG Maximum Ratings (Ta = 25°C) Characteristics Supply voltage Input pin signal voltage Power dissipation Symbol Rating Unit VCCmax 12 V einmax 9 Vp-p 2604 mW 20.8 mW/°C PD (Note 3) Power dissipation reduction rate depending on temperature 1/θja Operating temperature Topr Storage temperature Tstg Supply voltage (pins 16, 45 and 75) −20 to 65 −20 to 70 °C −55 to 150 °C min 8.7 8.5 typ. 9.0 8.8 max 9.3 9.1 V Note 3: See the following Figure A. (With device mounted on a PCB whose dimensions are 114.3 mm × 76.2 mm × 1.6 mm and whose surface is 20% copper. Mount the device on a PCB of at least these dimensions and whose surface is at least 20% copper.) When using in −25 to 70°C of operating temperature, set the IC’s power supply voltage (pins 16, 45, 75) to 8.8 V (±0.3 V). When designing a set, make sure that the IC can radiate heat because the TA1360AFG has low thermal capacity. Note that the power dissipation varies greatly according to conditions of a board. Power dissipation PD (mW) 2604 1771 1667 0 0 25 65 70 150 Ambient temperature Ta (°C) Figure A Power Dissipation Reduction Curve 24 2003-01-21 TA1360AFG Note 4: Power supply sequence At power-on, power should be supplied to the power supply pins according to the following sequence: 2 1. Pin 31 (I L VDD) 2. Pin 45 (DEF/DAC VCC) 3. Pins 16 and 75 (YC VCC/RGB VCC) Supply power to pin 37 via zener diode through resistor from pin 45. (See “Application Circuit”.) BUS preset value is become undefined and caused malfunction of the IC unless supplying power to all supply pins or follow the power supply sequence described above. When the frequency of horizontal output (pin 37) became undefined, horizontal transistor may be damaged. When the TA1360F is used for CRT, control horizontal oscillation frequency by pins 41 and 55. V DEF/DAC VCC Horizontal output 6.0 V (typ.) POR release voltage (BUS operation) 4.6 V (typ.) I2L VDD Logic operation 1.3 V (typ.) t Figure B Timing chart that indicates the timing from power-on till horizontal output. (At Ta = 25 C°°) 25 2003-01-21 TA1360AFG Operating Conditions Characteristics Description Pin 16, 45, 75 Supply voltage (VCC) Min Typ. Max Topr = −20 to 65°C (Note 5) 8.7 9.0 9.3 Topr = −20 to 70°C (Note 5) 8.5 8.8 9.1 Unit V Pin 31 1.8 2.0 2.2 Y input level Pins 63, 68: 100% color bar, including sync (Picture period amplitude, 0.7 Vp-p) 1.0 Color-difference input level Pins 60, 61 66, 67: 100% color bar, not including sync 0.7 HD/VD input level Pins 50, 52 2.0 5.0 VCC V SYNC input level Pin 53: 100% color bar, including sync 0.9 1.0 1.1 Vp-p SCP input level Pin 49 CP 4.2 5.0 VCC BPP 2.2 2.5 2.8 At 28 k/31 k/33 k/37 kHz 0 0 1.0 At 15 k/31 k/33 k/45 kHz 8.0 VCC VCC 28.125 kHz or 15.75 kHz 8.0 VCC VCC 31.5 kHz 5.0 6.0 7.0 33.75 kHz 2.0 3.0 4.0 0 0 1.0 H-AFC 6.5 7.0 VCC H-BLK 3.0 3.5 4.0 Vp-p Pin 55 Horizontal frequency switching voltage V Pin 41 37.9 kHz or 45 kHz FBP input level Pin 39 FBP input width Pin 39 0.16 0.3 H-OUT input current Pin 37 9.0 15.0 DAC input current Pins 23, 34 0.3 1.0 SCL/SDA pull-up voltage Pins 28, 30 3.3 5.0 VCC V SDA input current Pin 28 2 mA Analog RGB input level Pins 24, 25, 26: White 100% 0.7 Analog OSD input level Pins 18, 19, 21: White 100% 0.7 YS3 switching voltage Pin 2 1.5 5.0 VCC OSD 2.9 5.0 YS1/2 switching voltage Pins 1, 80 VCC VSM MUTE 1.1 1.5 1.7 BLK 7.0 VCC VCC P-MUTE 2.7 3.5 4.0 HALF TONE 1.2 1.5 1.8 0.78 1 H mA Vp-p V YM switching voltage External V-BLK input current Pin 79 Pin 35 mA Note 5: See “Maximum Ratings” about Topr. Electrical Characteristics (unless otherwise specified, VCC = 9 V/2 V, Ta = 25°C) Current Dissipation Symbol Test Circuit Min Typ. Max DEF/DAC VCC (9 V) ICC1 19.2 24.0 28.2 RGB VCC (9 V) ICC2 48.8 61.0 67.8 I L VDD (2 V) ICC3 21.3 25.0 29.4 Y/C VCC (9 V) ICC4 36.8 46.0 51.1 Pin Name 2 26 Unit mA 2003-01-21 TA1360AFG Pin Voltage Test Condition (1) (2) BUS = Preset SW71 = B, SW70 = B, SW68 = C, SW67 = B, SW66 = B, SW64 = B, SW63 = B, SW60 to 61 = B, SW53 = B, SW44 = ON, SW40 = B, SW39 = A, SW37 = A, SW24 to 26 = A, SW21 = A, SW18~19 = A, SW77 = OFF, SW74 = ON Pin No. Pin Name Symbol Test Circuit Min Typ. Max 1 YS2 V1 0.1 0.2 2 YS3 V2 0.1 0.2 4 R S/H V4 4.2 5.2 6.2 6 G S/H V6 4.2 5.2 6.2 7 B S/H V7 4.2 5.2 6.2 18 ANALOG OSD R IN V18 3.65 3.95 4.25 19 ANALOG OSD G IN V19 3.65 3.95 4.25 21 ANALOG OSD B IN V21 3.65 3.95 4.25 24 ANALOG R IN V24 3.65 3.95 4.25 25 ANALOG G IN V25 3.65 3.95 4.25 26 ANALOG B IN V26 3.65 3.95 4.25 40 H CURVE CORRECTION V40 2.2 2.5 2.8 42 HVCO V42 4.4 5.0 5.6 44 AFC FILTER V44 5.4 6.2 7.0 49 CP IN V49 0 0.3 50 HD IN V50 0 0.3 52 VD IN V52 0 0.3 53 SYNC IN V53 1.8 2.1 2.4 57 VSM FILTER V57 7.5 7.7 7.9 58 COLOR LIMITER V58 6.65 6.9 7.15 60 Cr/Pr2 IN V60 4.7 5.0 5.3 61 Cb/Pb2 IN V61 4.7 5.0 5.3 63 Y2 IN V63 4.7 5.0 5.3 64 LIGHT AREA DET FILTER V64 0.09 0.15 66 Cr/Pr1 IN V66 4.7 5.0 5.3 67 Cb/Pb1 IN V67 4.7 5.0 5.3 68 Y1 IN V68 4.7 5.0 5.3 70 BPH FILTER V70 5.5 5.8 6.1 71 DARK AREA DET FILTER V71 0.09 0.15 74 APL FILTER V74 4.8 5.0 5.2 77 VSM OUT V77 4.1 4.3 4.5 78 ABCL IN V78 6.1 6.35 6.6 79 YM V79 0.1 0.2 80 YS1 V80 0.1 0.2 27 Unit V 2003-01-21 TA1360AFG Picture Quality (Sharpness) Block Characteristics Y input dynamic range Black detection level shift Black stretch amp maximum gain Black stretch start point 1 Black stretch start point 2 Black stretch characteristic switch Black stretch area reinforcement current D.ABL detection voltage D.ABL sensitivity Black level correction Dark area Yγ correction point Dark area dynamic Yγ gain Dark area static Yγ gain Light area Yγ correction point Light area dynamic Yγ gain Light area static Yγ gain Dark area detection sensitivity DC restoration rate DC restoration point DC restoration limit Symbol Test Circuit Test Condition Min Typ. Max Unit DRY 0.7 1.0 1.5 Vp-p VB −15 10 15 VB3 35 45 55 2.4 2.8 3.2 20 25 35 50 55 60 0 5 10 14 21 30 (Note P01) mV GBS PBST1 PBST2 PBS1 PBS2 PBSC1 26 28 30 PBSC2 −8 −6 −4 PBSC3 26 28 30 PBSC4 −5.5 −3 −1 PBSC5 26 28 30 PBSC6 −3.5 −2 −0.5 IBSA 13 18 23 DV01 80 120 160 DV10 240 280 320 DV11 380 420 460 SDAMIN 0.01 0.02 SDAMAX 0.25 0.28 0.31 BLC (Note P09) 4.5 6.5 8.5 IRE PDGP (Note P10) 25 28 33 IRE GDDGMAX (Note P11) 5.5 6 6.5 dB GDSGMIN GDSGMAX LPG GLDG GLSGMIN GLSGMAX DAMIN DACEN DAMAX (Note P02) (Note P03) IRE (Note P04) (Note P05) (Note P06) (Note P07) (Note P08) dB IRE IRE µA mV V/V −6.5 −5 −4 2 2.4 2.6 (Note P13) 64 74 80 IRE (Note P14) 1.1 1.7 2.3 dB 0.3 0.6 0.9 1.4 1.7 2.3 0.25 0.3 0.37 0.88 0.98 1.08 0.95 1.05 1.15 ADT100 0.9 1.1 1.2 ADT135 1.2 1.35 1.5 ADT65 0.55 0.70 0.85 VDT0 −5 0 5 VDT1 47 49 55 PDTL60 64 67 70 PDTL75 74 77 80 PDTL87 74 80 82 PDTL100 74 80 82 (Note P12) (Note P15) (Note P16) (Note P17) (Note P18) dB V times % (Note P19) 28 dB % 2003-01-21 TA1360AFG Characteristics Sharpness control peak frequency DC fluctuation at switching sharpness control peak frequency Sharpness control range Sharpness control center characteristic 2T pulse response SRT control VSM peak frequency VSM gain VSM mute threshold voltage VSM limit Y input to R output delay time Y delay time switch Y group delay correction Symbol Test Circuit FAP00 FAP01 FAP10 FAP11 VRDC GMAX00 Test Condition Min Typ. Max 10.5 13.5 17 7 9.5 12 5 7.2 7.8 3.5 4.5 6.3 0.01 0.02 15 17.5 19 GMIN00 −4 −0.6 2.5 GMAX01 15 17.5 19 GMIN01 −5 −0.3 2.5 GMAX10 15 17.5 19 GMIN10 −7 −2.5 1.5 GMAX11 15 17.5 19 GMIN11 −12 −5 0 GCEN00 7 10 13 GCEN01 7 10 13 GCEN10 7 10 13 MHz (Note P20) (Note P21) dB GCEN11 7 10 13 TSRT00 0.9 1.6 2.7 TSRT01 3.5 4.8 7.1 TSRT10 6.7 8.5 11.3 TSRT11 11.5 12.5 15.5 FVSM 19 19.5 25.5 GV000 −40 −35 GV001 −2 −1.2 −0.4 GV010 3.7 4.6 5.5 GV011 7.1 8.2 9.3 GV100 8.9 10.5 12.1 GV101 11.4 12.6 13.8 GV110 13.5 14.4 15.3 GV111 14.8 15.7 16.6 VSR1 0.62 0.78 0.85 VSR2 0.62 0.78 0.85 VSR580 0.62 0.78 0.85 VLU 0.55 0.66 0.75 VLD 0.55 0.66 0.75 TYR 110 125 140 YDLA 3 5 10 YDLB 7 10 15 YDLC 10 15 25 GAMIN −4 −2.5 −1 GBMIN 2.5 3 3.5 GAMAX 1 1.7 2.4 GBMAX −5 −4 −2 (Note P23) dB (Note P24) Pins 1, 2, 80 (Note P26) MHz dB (Note P25) V dB (Note P22) V Vp-p (Note P27) 29 Unit ns ns dB 2003-01-21 TA1360AFG Characteristics Color detail enhancer Y detail frequency Y detail control range Symbol Test Circuit GCDE00 GCDE01 GCDE10 GCDE11 FYD GYDMAX GYDCEN GYDMIN Test Condition (Note P28) (Note P29) 30 Min Typ. Max 9 10 11 9 10 11 9 10 11 9 10 11 4 5 6 11 13 15 8 10 12 3 5 7 Unit dB MHz dB 2003-01-21 TA1360AFG Color Difference Block 1: YUV input and matrix Characteristics Color difference input dynamic range Color difference tint control characteristic Color SRT peak frequency Color SRT gain Cb1 input to B output delay time Cr1 input to R output delay time Dynamic Y/C compensation YUV gain Symbol Test Circuit DRB DRR TRMAX Test Condition Min Typ. Max 0.7 0.9 1.0 0.7 0.9 1.0 25 29 33 −37 −33 −29 27 31 35 Unit Vp-p TRMIN TBMAX TBMIN −36 −32 −28 FB00 3.6 4.5 5.4 FB01 4.6 5.8 7.0 FR00 3.6 4.5 5.4 FR01 4.6 5.8 7.0 GSB00CEN 1.5 2.8 4.1 GSB00MAX 2.9 4.2 5.5 GSB01CEN 2.0 3.3 4.6 GSB01MAX 3.5 4.8 6.1 GSR00CEN 3.4 4.7 6.0 GSR00MAX 5.4 6.7 7.0 GSR01CEN 3.1 4.4 5.7 GSR01MAX 5.2 6.5 7.8 TB 130 155 185 ns 130 155 185 ns 1.8 2.25 2.7 −1.65 −1.2 −0.75 1.8 2.25 2.7 MHz (Note S01) dB TR GCBDY1 GCBDY2 GCRDY1 GCRDY2 −1.65 −1.2 −0.75 GY00 2.4 3.4 4.4 GY01 2.4 3.4 4.4 GCBB 9.5 11.0 12.5 GPBB 9.9 11.4 12.9 GPBR −18.0 −16.0 −14.0 GCRR 9.5 11.0 12.5 GPRB −15.0 −13.5 −12.0 GPRR 10.0 11.5 13.0 (Note S02) (Note S03) 31 ° dB dB 2003-01-21 TA1360AFG Characteristics Green stretch Symbol Test Circuit GrA01 Test Condition Min Typ. Max 0.98 1 1.02 GrA10 0.95 1 1.05 GrA11 0.93 1 1.07 GrB01 1.01 1.05 1.10 GrB10 1.05 1.1 1.15 GrB11 1.12 1.19 1.26 GrC01 1.10 1.14 1.18 GrC10 1.23 1.27 1.31 GrC11 1.35 1.42 1.49 GrD01 1.09 1.13 1.17 GrD10 1.21 1.25 1.29 GrD11 1.32 1.39 1.46 GrE01 0.98 1 1.02 GrE10 0.95 1 1.05 GrE11 0.93 1 1.07 (Note S04) 32 Unit times 2003-01-21 TA1360AFG Color Difference Block 2 Characteristics Color difference contrast adjustment characteristic Color adjustment characteristic R-Y relative phase and amplitude G-Y relative phase and amplitude Color difference halftone characteristic Color γ characteristic Color limiter characteristic High-bright color gain Symbol Test Circuit ∆VuCY ∆vcCY+ ∆vcCY− θRMAX Test Condition Min Typ. Max Unit 14.5 16.0 17.5 dB 3.0 4.0 5.0 −35 −22 −17 109 111.5 114 θRCNT 98.5 101 103.5 θRMIN 88 90 92 VR/VBMAX 0.86 0.90 0.94 VR/VBCNT 0.65 0.69 0.73 VR/VBMIN 0.42 0.45 0.49 θGMAX 251 254 257 θGCNT 244 247 250 θGMIN 229 232 235 VG/vBMAX 0.43 0.48 0.53 VG/vBCNT 0.33 0.37 0.41 VG/vBMIN 0.22 0.25 0.28 GHTRY 0.47 0.50 0.53 GHTGY 0.47 0.50 0.53 GHTBY 0.47 0.50 0.53 Vγ1 0.09 0.23 0.37 Vγ2 0.26 0.40 0.54 Vγ3 0.44 0.58 0.72 ∆γ 0.60 0.70 0.80 CLT0 1.45 1.65 1.85 CLT1 1.80 2.00 2.20 HBC1 0.02 0.04 0.06 (Note A01) (Note A02) (Note A03) dB ° times ° times times Vp-p (Note A04) (Note A05) (Note A06) 33 Vp-p times 2003-01-21 TA1360AFG Text Block Symbol Test Circuit GR GG GB GG/R GB/R GfR GfG GfB Frequency characteristic (Cb1/Cr1in~R/G/B out) GfCb GfCr Unicolor adjustment characteristic ∆Vu VbrMAX VbrCNT VbrMIN Vwps1 Vwps2 Vbps N12 N13 Characteristics AC gain (Y1in~R/G/B out) AC gain axis difference Frequency characteristic (Y1in~R/G/B out) Brightness adjustment characteristic White peak slice level Black peak slice level RGB output S/N Halftone characteristic Halftone on voltage V-BLK pulse output level H-BLK pulse output level BLK pulse delay time Sub-contrast variable range RGB output voltage 3-axis difference (Note T01) At −3dB, sharpness characteristic is flat (Note T02) (Note T03) Min Typ. Max 3.08 3.45 3.90 3.08 3.45 3.90 3.08 3.45 3.90 0.94 1.00 1.06 0.94 1.00 1.06 30 60 30 60 30 60 10 12.5 10 12.5 15.0 16.0 17.0 4.10 4.45 4.80 3.05 3.40 3.75 1.95 2.30 2.65 2.20 2.32 2.44 2.59 2.74 2.89 (Note T05) 1.15 1.35 1.45 (Note T06) −52 −46 −52 −46 N14 −52 −46 0.45 0.50 0.55 GHT2 0.45 0.50 0.55 VHT 0.65 0.85 1.05 VVR 0.30 0.80 1.30 VVG 0.30 0.80 1.30 VVB 0.30 0.80 1.30 VHR 0.30 0.80 1.30 VHG 0.30 0.80 1.30 VHB 0.30 0.80 1.30 tdON 0.00 0.30 tdOFF 0.08 0.30 ∆vsu+ 1.95 2.45 2.95 ∆vsu− −3.8 −3.3 −2.8 CUT+ 0.42 0.47 0.52 CUT− 0.42 0.47 0.52 ∆V#12 2.05 2.30 2.55 ∆V#13 2.05 2.30 2.55 ∆V#14 2.05 2.30 2.55 ∆VOUT 0 150 (Note T07) Pin 79 (Note T08) 34 Unit times MHz MHz dB V Vp-p (Note T04) GHT1 Cut-off voltage variable range RGB output voltage Test Condition V dB times V V V µs dB V V mV 2003-01-21 TA1360AFG Characteristics Drive adjustment variable range Output voltage at P-mute P-mute ON voltage Output voltage at blue background Input impedance of #78 ACL characteristic ABL point ABL gain Symbol Test Circuit DRR1+ Test Condition Min Typ. Max 2.5 3.0 3.5 DRR1− −5.5 −5.0 −4.5 DRR2+ 2.5 3.0 3.5 Unit DRR2− −5.5 −5.0 −4.5 DRG1+ 2.5 3.0 3.5 DRG1− −5.5 −5.0 −4.5 DRG2+ 2.5 3.0 3.5 DRG2− −5.5 −5.0 −4.5 DRG3+ 2.5 3.0 3.5 DRG3− −5.5 −5.0 −4.5 DRB1+ 2.5 3.0 3.5 DRB1− −5.5 −5.0 −4.5 DRB2+ 2.5 3.0 3.5 DRB2− −5.5 −5.0 −4.5 DRB3+ 2.5 3.0 3.5 DRB3− −5.5 −5.0 −4.5 MURD 1.7 1.85 2.0 MUGD 1.7 1.85 2.0 MUBD 1.7 1.85 2.0 VMUTE 1.90 2.15 2.40 BBR 1.0 1.2 1.4 BBG 1.0 1.2 1.4 BBB 1.1 1.25 1.4 Vp-p Zin 24 30 36 kΩ ACL1 −6.5 −4.5 −2.5 ACL2 −15.0 −13.5 −11.0 ABLP1 −0.21 −0.16 −0.11 ABLP2 −0.28 −0.23 −0.18 ABLP3 −0.37 −0.32 −0.27 ABLP4 −0.45 −0.40 −0.35 ABLP5 −0.54 −0.49 −0.44 ABLP6 −0.62 −0.57 −0.52 ABLP7 −0.70 −0.65 −0.60 ABLP8 −0.75 −0.70 −0.65 ABLG1 −0.06 −0.02 0.00 ABLG2 −0.17 −0.12 −0.07 ABLG3 −0.34 −0.29 −0.24 ABLG4 −0.52 −0.47 −0.42 ABLG5 −0.68 −0.63 −0.59 ABLG6 −0.85 −0.80 −0.75 ABLG7 −1.01 −0.96 −0.91 ABLG8 −1.09 −1.04 −0.99 (Note T09) Pin 79 V V V (Note T10) (Note T11) (Note T12) (Note T13) 35 dB dB V V 2003-01-21 TA1360AFG Characteristics RGB output mode Y-OUT γ characteristic White-peak blue characteristic Forced BLK input threshold voltage ACB insertion pulse phase and amplitude IK input amplitude IK input cover range Symbol Test Circuit V12R Test Condition Min Typ. Max 2.15 2.40 2.65 V13R 0.30 0.80 1.30 V14R 0.30 0.80 1.30 V12G 0.30 0.80 1.30 V13G 2.15 2.40 2.65 V14G 0.30 0.80 1.30 V12B 0.30 0.80 1.30 V13B 0.30 0.80 1.30 V14B 2.15 2.40 2.65 γ1 56 66 76 γ2 72 82 92 ∆1 0.49 1.24 1.99 ∆2 −1.67 −0.92 −0.17 ∆3 −4.59 −3.84 −3.09 BSPmin 37 42 47 BSPcnt 72 77 82 BSPmax 101 106 111 BSGmin 2.1 3.1 4.1 BSGcnt 6.4 7.4 8.4 BSGmax VBLKIN θACBR (Note T14) Unit V IRE (Note T15) dB IRE (Note T16) 9 10 11 5.1 5.6 6.1 1 θACBG 2 θACBB 3 VACB1R 0.15 0.20 0.25 VACB1G 0.15 0.20 0.25 VACB1B 0.15 0.20 0.25 VACB2R 0.27 0.32 0.37 VACB2G 0.27 0.32 0.37 VACB2B 0.27 0.32 0.37 VACB3R 0.52 0.57 0.62 VACB3G 0.52 0.57 0.62 VACB3B 0.52 0.57 0.62 IKR 0.73 0.93 1.13 IKG 0.73 0.93 1.13 Pin 79 dB V H (Note T17) (Note T18) IKB 0.73 0.93 1.13 DIKin+ 3.00 3.30 3.60 DIKin− −0.50 −0.30 −0.10 (Note T19) 36 Vp-p Vp-p V 2003-01-21 TA1360AFG Characteristics Analog RGB gain Analog RGB gain 3-axis difference Analog RGB frequency characteristic Analog RGB input dynamic range Analog RGB white peak slice level Analog RGB black peak limit level RGB contrast adjustment characteristic Analog RGB bright adjustment characteristic Analog RGB mode switching voltage Analog RGB mode switching transfer characteristic Text ACL characteristic Analog OSD gain Analog OSD gain 3-axis difference Analog OSD frequency characteristic Analog OSD input dynamic range Symbol Test Circuit GTXR GTXG GTXB GTXG/R GTXB/R GfTXR GfTXG GfTXB Test Condition (Note T20) Min Typ. Max 3.03 3.40 3.83 3.03 3.40 3.83 3.03 3.40 3.83 0.94 1.00 1.06 0.94 1.00 1.06 30 35 30 35 30 35 DR24 0.80 1.20 1.50 DR25 0.80 1.20 1.50 DR26 0.80 1.20 1.50 TXVWPSR 2.45 2.70 2.95 TXVWPSG 2.45 2.70 2.95 TXVWPSB 2.45 2.70 2.95 VBPSR 1.15 1.30 1.45 VBPSG 1.15 1.30 1.45 VBPSB 1.15 1.30 1.45 ∆vuTXR 15.5 16.5 18.5 ∆vuTXG 15.5 16.5 18.5 At −3dB (Note T21) (Note T22) (Note T23) ∆vuTXB 15.5 16.5 18.5 VbrTXmax 3.0 3.2 3.4 VbrTXcnt 2.6 2.8 3.0 VbrTXmin 2.1 2.3 2.5 VTXON 0.65 0.85 1.05 τRYS 15 50 tPRYS 20 50 ∆tRYS 0 10 τFYS 10 50 tPRYS 30 50 ∆tRYS 0 10 TXACL1 −6.7 −4.7 −2.7 TXACL2 −16.5 −14.5 −12.5 GOSDR 2.95 3.30 3.70 GOSDG 2.95 3.30 3.70 GOSDB 2.95 3.30 3.70 GOSDG/R GOSDB/R GfOSDR GfOSDG GfOSDB (Note T24) Pin 2 (Note T25) (Note T26) (Note T27) 0.94 1.00 1.06 1.00 1.06 35 40 35 40 35 40 DR18 0.80 1.20 1.50 DR19 0.80 1.20 1.50 DR21 0.80 1.20 1.50 At −3dB 37 times MHz Vp-p Vp-p V dB V V ns 0.94 Unit dB times MHz Vp-p 2003-01-21 TA1360AFG Characteristics Analog OSD input white peak slice level Analog OSD black peak limit level OSD contrast adjustment characteristic Analog OSD bright adjustment characteristic Analog OSD mode switching voltage Analog OSD mode switching transfer characteristic OSD ACL characteristic Symbol Test Circuit OSDVWPSR OSDVWPSG OSDVWPSB Test Condition (Note T28) Min Typ. Max 2.45 2.70 2.95 2.45 2.70 2.95 2.45 2.70 2.95 1.30 1.45 1.60 1.30 1.45 1.60 OSDVBPSR OSDVBPSG OSDVBPSB 1.30 1.45 1.60 VUOSDR11 0.58 0.64 0.71 VUOSDG11 0.58 0.64 0.71 VUOSDB11 0.58 0.64 0.71 VUOSDR10 0.47 0.53 0.59 VUOSDG10 0.47 0.53 0.59 VUOSDB10 0.47 0.53 0.59 VUOSDR01 0.31 0.37 0.45 VUOSDG01 0.31 0.37 0.45 VUOSDB01 0.31 0.37 0.45 VUOSDR00 0.19 0.22 0.24 VUOSDG00 0.19 0.22 0.24 VUOSDB00 0.19 0.22 0.24 VbrOSD0 2.20 2.40 2.60 VbrOSD1 2.05 2.25 2.45 VbrOSD2 1.95 2.15 2.35 VbrOSD3 1.80 2.00 2.20 (Note T29) Unit Vp-p V Vp-p (Note T30) V (Note T31) VOSDON1 Pin 80 2.05 2.30 2.55 VOSDON2 Pin 1 2.05 2.30 2.55 V τRYS1 15 50 tPRYS1 20 50 ∆tPRYS1 0 10 τFYS1 10 50 tPRYS1 30 50 ∆tPRYS1 0 10 τRYS2 15 50 tPRYS2 20 50 ∆tPRYS2 0 10 τFYS2 10 50 tPRYS2 30 50 (Note T32) ns ∆tPRYS2 0 10 OSDACL1 0.00 OSDACL2 0.00 OSDACL3 −6.7 −4.7 −2.7 OSDACL4 −16.5 −14.5 −12.5 (Note T33) 38 dB 2003-01-21 TA1360AFG Characteristics Test Circuit α41TV1 Min Typ. Max −7 −6 −5 α42TV1 −7 −6 −5 α43TV1 −7 −6 −5 α41TV2 −4 −3 −2 α42TV2 −4 −3 −2 α43TV2 −4 −3 −2 α41TV3 −55 −50 α42TV3 −55 −50 α43TV3 −55 −50 α41OSD1 −6.5 −5.5 −4.5 α42OSD1 −6.5 −5.5 −4.5 α43OSD1 −6.5 −5.5 −4.5 α41OSD2 −12.0 −10.5 −9.0 α42OSD2 −12.0 −10.5 −9.0 α43OSD2 −12.0 −10.5 −9.0 α41OSD3 −40 −30 α42OSD3 −40 −30 α43OSD3 −40 −30 Y → RGB input VV → A −50 −45 Y → OSD input VV → O −55 −45 RGB input → Y VA → V −50 −45 RGB input → OSD input VA → O −50 −45 OSD input → Y VO → V −45 −40 OSD input → RGB input VO → A −50 −45 RGB input in three axes −50 −40 OSD input in three axes −50 −40 BLPmin 23 28 33 BLPmax 55 60 65 BLGmin 2.4 2.9 3.4 BLGmax 5.4 6.4 7.4 BLγ1 84 89 94 BLγ2 89 94 99 93 98 103 98 103 108 16 21 25 51 56 61 97 102 107 OSD blending characteristic Input crosstalk Symbol Blue stretch point/gain Blue stretch γ correction White letters improvement BLγ3 BLγ4 WPL1 WPL2 WPL3 Test Condition (Note T34) Input: Signal 1 (fo = 4 MHz, Amplitude 0.7 Vp-p) Input: Signal 1 (fo = 1 MHz, Amplitude 0.7 Vp-p) Unit dB dB IRE (Note T35) dB (Note T36) (Note T37) 39 IRE Vp-p 2003-01-21 TA1360AFG Sync Block Characteristics Symbol Test Circuit SPH HDPH HDDUTY1 HDDUTY2 HDDUTY3 HDDUTY4 Min Typ. Max Unit (Note HA01) 0.55 0.65 0.75 µs (Note HA02) 0.58 0.68 0.78 µs 0.5 2.0 62 67 72 99.5 98 47.5 52.5 57.5 VthS00 10 16 22 VthS01 18 24 30 VthS10 26 32 38 VthS11 34 40 46 VthHD 0.65 0.75 0.85 ∆HSFT− 11 12.5 14 ∆HSFT+ 11 12.5 14 Horizontal picture position (phase) shift switching amount HSFT 5.2 6.7 9.2 % Curve correction variable amount ∆H#40 2.9 3.4 3.9 % CPS0 3.1 3.8 4.5 CPW0 2.0 2.5 3.0 CPV0 4.7 5.0 5.3 CPS1 0 0.7 1.5 CPW1 1.9 2.4 2.9 CPV1 4.7 5.0 5.3 CPS2 3.2 4.2 5.2 CPW2 2.2 2.7 3.2 Sync input horizontal sync phase HD input horizontal sync phase Polarity detecting rage Sync input threshold amplitude HD input threshold voltage Horizontal picture position (phase) adjustment variable range Clamp pulse phase/width/level Test Condition (Note HA03) % % (Note HA04) (Note HA05) (Note HA06) (Note HA07) Vp-p % % V % (Note HA08) V % CPV2 4.7 5.0 5.3 HBPS00a 1.2 3.0 5.9 HBPS00b 1.2 3.0 5.9 HBPS01a 6.0 8.0 11.0 HBPS01b 6.0 8.0 11.0 HBPs10a 10.0 13.0 15.0 HBPs10b 10.0 13.0 15.0 HBPs11a 16.0 18.0 21.0 HBPs11b 16.0 18.0 21.0 FBP threshold VthFBP 4.8 5.3 5.8 V HVCO oscillation start voltage VVCO Pin 42: Monitor, VCC voltage 3.0 4.0 5.0 V H-OUT start voltage VHON Pin 37: Monitor, VCC voltage 5.0 6.0 7.0 V H-OUT stop voltage VHOFF Pin 37: Monitor, VCC voltage 4.3 5.3 6.3 V THA 38 41 43 THB 44 47 49 Black peak detection pulse phase H-OUT pulse duty (Note HA09) (Note HA10) % (Note HB01) 40 V % 2003-01-21 TA1360AFG Characteristics Horizontal free-run frequency Horizontal oscillation frequency variable range Horizontal oscillation control sensitivity Min Typ. Max 15.59 15.75 15.91 F28K 27.90 28.125 28.35 F31K 31.19 31.5 31.82 F33K 33.41 33.75 34.09 F37K 37.60 37.9 38.40 F45K 44.52 45.0 45.48 F15KMIN 14.78 15.08 15.38 F15KMAX 16.37 16.70 17.03 F28KMIN 26.00 26.90 27.80 F28KMAX 28.90 29.70 30.60 F31KMIN 29.47 30.06 30.65 F31KMAX 32.72 33.39 34.06 F33KMIN 31.41 31.94 32.57 F33KMAX 34.91 35.62 36.33 F37KMIN 36.50 37.30 38.20 F37KMAX 40.20 41.10 42.10 F45KMIN 43.20 44.00 44.80 F45KMAX 47.85 48.65 49.45 BH15K 176 220 264 BH28K 320 400 480 BH31K 352 440 528 376 470 564 (Note HB02) Hz/0.1 V (Note HB04) 390 480 570 BH45K 520 650 780 VHOH 4.8 5.1 5.2 VHOL 0.1 0.3 VfHSW1 1.7 2.0 2.3 VfHSW2L 1.3 1.5 1.7 VfHSW2M 4.3 4.5 4.7 VfHSW2H 7.3 7.5 7.7 VDAC1H TEST = (00), DAC1 = (0) 8.5 9.0 VDAC1L TEST = (00), DAC1 = (1) 0.3 0.7 VDAC2H TEST = (00), DAC2 = (1) 8.5 9.0 VDAC2L TEST = (00), DAC2 = (0) 0.3 0.7 VPW 4 4.5 5 000 VPt0 1278 1281 1284 001 VPt1 846 849 852 010 VPt2 722 725 728 011 VPt3 657 660 663 100 VPt4 610 613 616 101 VPt5 360 363 366 110 VPt6 304 307 310 TVPULL 47 48 49 Pin 41 DAC switch voltage DAC2 VP output pulse width (Note HB05) kHz V V (Note V01) (Note V02) 41 Unit kHz (Note HB03) BH37K DAC1 Vertical minimum pull-in range F15K Test Condition Pin 55 Vertical free-run (maximum pull-in range) Test Circuit BH33K H-OUT output voltage Horizontal oscillation frequency control voltage threshold Symbol V H H H 2003-01-21 TA1360AFG Characteristics 000 001 010 Vertical black peak detection pulse 011 100 101 110 Vertical blanking end phase High VP output voltage Low Symbol Test Circuit VBPP0E VBPP0S VBPP1E 51 52 53 001 010 Compression BLK 1 (start phase) 011 100 101 110 Min Typ. Max 51 52 53 Unit 1099.5 1100.5 1101.5 VBPP1S 729.5 730.5 731.5 VBPP2E 49.5 50.5 51.5 VBPP2S 599.5 600.5 601.5 VBPP3E 49.5 50.5 51.5 VBPP3S 544.5 545.5 546.5 VBPP4E 51 52 53 VBPP4S 499.5 500.5 501.5 VBPP5E 51 52 53 VBPP5S 289.5 290.5 291.5 VBPP6E 51 52 53 VBPP6S 239.5 240.5 241.5 VBLKMIN 15 16 17 VBLKMAX 45 46 47 VVPH 4.6 5.0 5.4 VVPL 0.1 0.5 15.75 kHz 10.0 11.6 13.4 28.125 kHz 5.4 6.4 8.8 31.5 kHz 4.8 5.8 7.6 33.75 kHz 4.4 5.4 7.2 37.9 kHz 3.9 4.8 6.6 45 kHz 3.1 4.1 5.9 CBLK1000min 1087 1088 1089 CBLK1000max 1117 1118 1119 CBLK1001min 719 720 721 CBLK1001max 749 750 751 CBLK1010min 591 592 593 CBLK1010max 621 622 623 CBLK1011min 527 528 529 CBLK1011max 557 558 559 CBLK1100min 487 488 489 CBLK1100max 517 518 519 CBLK1101min 279 280 281 CBLK1101max 309 310 311 CBLK1110min 223 224 225 CBLK1110max 253 254 255 SYNC input to VP output delay time 000 Test Condition (Note V03) H (Note V04) pin 35 voltage 42 H V µs H 2003-01-21 TA1360AFG Characteristics 000 001 010 Compression BLK 2 (end phase) 011 100 101 110 External V-BLK input current Symbol Test Circuit CBLK2000min Test Condition Min Typ. Max 49 50 51 CBLK2000max 77 78 79 CBLK2001min 49 50 51 CBLK2001max 77 78 79 CBLK2010min 49 50 51 CBLK2010max 77 78 79 CBLK2011min 49 50 51 CBLK2011max 77 78 79 CBLK2100min 49 50 51 CBLK2100max 77 78 79 CBLK2101min 49 50 51 CBLK2101max 77 78 79 CBLK2110min 49 50 51 CBLK2110max 77 78 79 IEXTBLK 520 625 780 Pin 35 input current 43 Unit H µA 2003-01-21 TA1360AFG Test Condition for Picture Quality (Sharpness) Block Common Test Condition for Picture Quality (Sharpness) Block 1. 2. 3. 4. Note No. SW67 = SW66 = B, SW63 = B, SW60 to SW61 = B, SW44 = ON, SW40 = B, SW18 to SW26 = A, SW77 = OPEN Send bus control data as preset values, turn ACB operation switching to ACB OFF (00), select Sync input (1), turn P-MODE to Normal 1(000), WPL-LEVEL to max (111), and change subaddress (1C) to (03). Input sync signal, which is in sync with input signal for testing except “Sweep”, to #53 (Sync input). “H-Freq.” should be the same frequency as the one of #53. Set Y/color difference input mode to (0), sync separator level to 20 % (01), and vertical free-running frequency to 307H (110). Characteristics SW71 P01 Black detection level shift B Test Conditions SW Mode SW70 SW68 SW64 C C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS to #68, and monitor #70 and #74. 2. Set black stretch point 1 to OFF (000), and black detection level to 0 IRE (1). 3. Increase PS voltage from 4.95 V in steps of 1 mV. At the moment when #70 picture period (High) drops to Low level, monitor DC difference on #74 VB. 4. Set black detection level to 3 IRE (0). 5. Repeat the step 3 above and monitor DC difference, VB3 on #74. #74 waveform VB, VB3 #70 waveform P02 Black stretch amp maximum gain B A A B OPEN 1. Set SW70 to A (maximum gain), and input 500-kHz sine wave to TPA. 2. Adjust signal amplitude to 0.1 Vp-p on #68. 3. Set black stretch point 1 to OFF (000), and measure #74 amplitude VA. 4. Set black stretch point 1 to 001 (black stretch ON), and measure #74 amplitude VB. 5. Calculate GBS using a following equation. GBS = 20 × log (VB ÷ VA) [dB] 44 2003-01-21 TA1360AFG Note No. Characteristics SW71 P03 Black stretch start point 1 A Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Set SW70 to A (maximum gain), and black stretch point 1 to OFF (000). Apply 0 V to #71. 2. Connect external power supply PS to #68, increase voltage from V3, and plot #74 voltage change S1. The #74 voltage is set as V0 when V3 is applied, and as V100 when V3 + 0.7 V is applied. 3. Set black stretch point 1 to minimum (001), increase PS voltage from V3, and then plot #74 voltage change S2. 4. Set black stretch point to maximum (111), repeat 3 above, then plot #74 voltage change S3. 5. Determine intersection points of S1, S2 (VBST1), and S3 (VBST2) as shown in the figure below. Also calculate PBST1 and PBST2 using following equations. VZ [V] = V100 [V] − V0 [V] PBST1 [(IRE)] = [(VBST1 [V] − V74 [V]) ÷ VZ] × 100 (IRE) PBST2 [(IRE)] = [(VBST2 [V] − V74 [V]) ÷ VZ] × 100 (IRE) #74 S3 VBST2 S1 VBST1 S2 V74 #68 45 2003-01-21 TA1360AFG Note No. Characteristics SW71 P04 Black stretch start point 2 A Test Conditions SW Mode SW70 SW68 SW64 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set black stretch point 1 to OFF (000), apply 0 V to #71, input TG7 LINEARITY to TPA, adjust amplitude on #68 as shown in the figure below, set unicolor to center (1000000), and measure amplitude of #12 (R OUT), VP12. 2. Set black stretch point 1 to 001 (black stretch ON), connect external power supply PS to #74, and monitor #12 (R OUT). 3. Set black stretch start point 2 data to minimum (00). When PS is V74 (APL 0%), and V74 + 1.0 V (APL 100%), determine black stretch start point difference ∆V00 as shown in the figure below. (Monitor input waveform and output waveform with an oscilloscope, adjust the both waveforms to have the same amplitude (gradient), and compare them to determine the bend point of the output.) 4. Set black stretchstart point 2 data to maximum (11), determine black stretch start point difference ∆V11. 5. Calculate following equations. PBS1 = (∆V00/VP12) × 100 PBS2 = (∆V11/VP12) × 100 LINEARITY APL 100% 0.7 Vp-p ∆V*** APL 0% 0.3 Vp-p #68 waveform (linearity) 46 #12 (R OUT) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P05 Black stretch characteristic switch A Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Set SW70 to A (maximum gain), black stretch point 1 (18) to maximum (E0), subaddress (1C) data to (00) and (1E) data to (08). 2. Apply 0 V to #71 and connect external power supply PS to #68. Set PS to V68 + 0.7 V, and adjust unicolor so that DC level of #12 is +1.0 V. Plot voltage change S4 of #12 (voltage in picture period). 3. Determine intersection points (VBSC1 and VBSC2) of S2 and S4 obtained from the plot in black stretch start point 1. Then calculate PBSC1 and PBSC2 using following equation. 4. Set black stretch characteristic switch subaddress data (1C)/(1E) to (20)/(00) and (20)/(08) respectively. As described in steps 2 and 3, determine intersection points (VBSC3, VBSC4, VBSC5 and VBSC6) and calculate PBSC3, PBSC4, PBSC5 and PBSC6. PBSC* = (VBSC* [V] − V12 [V]) ÷ 1.0 × 100 [(IRE)] #12 VBSC2 V12 V68 S2 V68 + 0.7 V #68 VBSC1 S4 Black stretch characteristic switch ON 47 2003-01-21 TA1360AFG Note No. Characteristics SW71 P06 Black stretch area reinforcement current B Test Conditions SW Mode SW70 SW68 SW64 C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Connect external power supply PS1 to #68. 2. Leave SW70 open, put an ammeter between SW70A and #70, connect external power supply PS2 to SW70A, set PS1 to 5.7 V, and set PS2 to 5 V. 3. Measure current value IBSA0 and IBSA1 when bus data of black stretch area reinforcement [18] is set to ON [80] and OFF [81]. Calculate IBSA using the following equation. IBSA = IBSA0−IBSA1 SW70 A µ Ａmmeter P07 D.ABL detection voltage B A C B OPEN PS2 5V 1. Set D.ABL sensitivity to maximum (11), and black stretch point 1 to OFF (000). 2. Connect external power supply PS to #78 and decrease voltage from 6.5 V. 3. Repeat 2 when D.ABL detection voltage is changed to 00, 01, 10, and 11. At the moment when #74 picture period changes to Low, measure respective PS voltages V00, V01, V10, and V11. 4. Calculate voltage differences between V00 and V01 (DV01), between V00 and V10 (DV10), and between V00 and V11 (DV11) DV*** = V00 − V01 (V10, V11) #74 undetected #74 detected #70 waveform 48 2003-01-21 TA1360AFG Note No. Characteristics SW71 P08 D.ABL sensitivity B Test Conditions SW Mode SW70 SW68 SW64 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set black stretch point 1 to OFF (000), and connect external power supply to #78. 2. Set D.ABL detection voltage to minimum (00). Interrelation between #78 voltage and #74 voltage when D.ABL sensitivity is set to minimum (00) and maximum (11) can be plotted as figure shown below. 3. Measure gradients SDAMIN and SDAMAX using the figure below. SDAMIN = ∆Y/∆X SDAMAX = ∆Y/∆X #74 10% ∆Y 100% 10% ∆X 49 #78 2003-01-21 TA1360AFG Note No. Characteristics SW71 P09 Black level correction B Test Conditions SW Mode SW70 SW68 SW64 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Set black stretch point 1[18] to OFF (00). 2. Input signal of 0.7-V picture period amplitude to #68, and measure #12 picture period amplitude VB [V]. 3. Set black level correction [18] to ON [04], determine DC change VBLC [V], and calculate BLC [V] using the following equation BLC = (VBLC/VB)] × 100 [(IRE)] #12 VBLC VB Black level correction OFF Black level correction ON 50 2003-01-21 TA1360AFG Note No. Characteristics SW71 P10 Dynamic Yγ correction point A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, PS2 to TP1, and set PS2 to 0 V. 2. Set dark area dynamic Yγ gain VS dark area to MIN (00), static Yγ gain1 to OFF (000). 3. Increase PS1 from V68 [V] to V68 [V] + 0.7 V and plot voltage change of #12 picture period. Take 0 for V68 [V] when the change is plotted. (V68 is pin voltage of pin 68) 4. Set dark area dynamic Yγ gain VS dark area max (11), static Yγ gain1 to max (111) and PS2 to 1.2 V. 5. Increase PS1 from V68 [V] to V68 [V] + 0.7 V and plot voltage change of #12 picture period. 6. Measure VDGP by the following figure, and PDGP using the following equation. DGP = (VDGP [V] − V68 [V])/0.7 [V] × 100 #12 voltage [V] ON OFF V68 51 VDGP #68 voltage [V] V68 + 0.7V (100 IRE) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P11 Dark area dynamic Yγ gain A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area dynamic Yγ gain [1C] to MIN [03], and dark area static Yγ gain [1C] to 0dB [17]. 3. Set PS1 to V68 [V], and measure #12 picture period voltage VDDGV68 [V]. Set PS1 VDGP [V], and measure #12 picture period voltage VDDGMIN [V]. 4. Set dark area dynamic Yγ gain [1C] to MAX [D7], PS2 to 1.2 V, measure voltage VDDGMAX [V] of #12 picture period when PS1 is VDGP [V], and calculate the following equations. VDDGMAX − VDDGMIN = A VDDGMIN − VDDGV68 = B GDDGMAX = 20 log [B/(B-A)] [dB] #12 voltage [V] OFF VDDGMAX ON VDDGMAX − VDDGMIN = A VDDGMIN VDDGV68 52 V68 VDGP VDDGMIN − VDDGV68 = B #68 voltage [V] V68 + 0.7 V (100IRE) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P12 Dark area static Yγ gain A Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area dynamic Yγ gain [1C] to MIN [03], and dark area static Yγ gain [1C] to OFF [03]. 3. Set PS1 to V68 [V], and measure #12 picture period voltage VSGOFF1 [V]. 4. Set PS1 to VDGP [V], and measure #12 picture period voltage VSGOFF2 [V]. 5. Set dark area static Yγ gain [1C] to MAX [1F], PS1 to VDGP [V], measure #12 picture period voltage VSGMAX, and calculate GDSGMAX using the following equations. VSGMAX − VSGOFF2 = A VSGOFF2 − VSGOFF1 = B GDSGMAX = 20 × log [B/(B - A)] [dB] #12 voltage [V] OFF VSGMAX ON VSGMAX − VSOFF2 = A VSGOFF2 VSGOFF1 V68 VDGP #68 voltage [V] V68 + 0.7 V (100IRE) 6. Set dark area static Yγ gain [1C] to MIN [07], PS1 to VDGP [V], measure #12 picture period voltage VSGMIN, and calculate GDSGMIN using the following equation. GDSGMIN = 20 × log [(VSGMIN − VSGOFF1)/(VSGOFF2 − VSGOFF1)] [dB] #12 voltage [V] OFF VSGOFF2 VSGMIN VSGOFF1 53 ON V68 VDGP VSGOFF2 − VSGOFF1 VSGMIN − VSGOFF1 #68 voltage [V] V68 + 0.7 V (100IRE) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P13 Light area Yγ correction point A Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area static Yγ gain [1C] to 0dB [17], and bright area static Yγ gain [1C] to 0dB [17]. 3. Increase PS1 from V68 [V] to V68 [V] + 0.7 [V], and plot the voltage change of #12 picture period. Take 0 for V68 [V] when the change is plotted. (V68 is pin voltage of pin 68) 4. Set light area static Yγ gain [1C] to MAX [04]. 5. Increase PS1 from V68 [V] to V68 [V] + 0.7 [V], and plot the voltage change of #12 picture period. 6. Measure VLGP using the following figure, and PLGP using the following equation. LGP = (VLGP [V] − V68 [V])/0.7 [V] × 100 (IRE) #12 voltage [V] ON OFF V68 54 VLGP #68 voltage V68 + 0.7 V (100IRE) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P14 Light area dynamic Yγ gain A Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 1.2 V. 2. Set dark area static Yγ gain [1C] to 0dB [17], and light area static Yγ gain [1C] to 0dB [17]. 3. Set PS1 to V68 [V], and measure #12 picture period voltage VLDGOFF1. 4. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2. 5. Set light area static Yγ gain [1C] to MAX [14], PS2 to 0 V, PS1 to VLGP [V], determine #12 picture period voltage VLDGMAX [V] using the following equations. VLDGMAX − VLDGOFF2 = A VLDGOFF2 − VLDGOFF1 = B GLDG = 20 × log [B/(B − A)] #12 voltage [V] VLDGMAX VLDGMAX − VLDGOFF2 = A ON VLDGOFF2 VLDGOFF2 − VLDGOFF1 = B OFF VLDGOFF1 55 V68 VLGP V68 + 0.7 V (100IRE) #68 voltage 2003-01-21 TA1360AFG Note No. Characteristics SW71 P15 Light area static Yγ gain B Test Conditions SW Mode SW70 SW68 SW64 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Connect external power supply PS1 to #68, external power supply PS2 to TP7, and set PS2 to 0 V. 2. Set dark area static Yγ gain [1C] to 0dB [17], and light area static Yγ gain [1C] to 0dB [17]. 3. Set PS1 to V68 [V], and measure #12 picture period voltage VLSGOFF1 [V]. 4. Set PS1 to VLGP [V], and measure #12 picture period voltage VLDGOFF2 [V]. 5. Set light area static Yγ gain [1C] to MAX [14], PS1 to VLGP [V], measure #12 picture period voltage VlSGMAX, and calculate GLASGMAX [dB] using the following equations. VLSGMAX − VLSGOFF2 = A VLSGOFF2 − VLSGOFF1 = B GLSGMAX = 20 × log [B/(B − A)] [dB] #12 voltage [V] VLSGMAX VLSGMAX − VLDGOFF2 = A ON VLSGOFF2 VLSGOFF2 − VLSGOFF1 = B OFF VLSGOFF1 6. V68 VLGP #68 voltage [V] V68 + 0.7 V (100IRE) Set light area static Yγ gain [1C] to MIN [16], PS1 to VLGP [V], measure #12 picture period voltage VLSGMIN, and calculate GLASGMIN [dB] using the following equations. VLSGMIN − VLSGOFF2 = C VLSGOFF2 − VLSGOFF1 = B GLSGMIN = 20 × log [B/(B − C)] [dB] #12 voltage [V] VLSGMIN VLSGMIN − VLDGOFF2 = C ON VLSGOFF2 − VLSGOFF1 = B OFF VLSGOFF1 56 V68 VLGP #68 voltage [V] V68 + 0.7 V (100IRE) 2003-01-21 TA1360AFG Note No. Characteristics SW71 P16 Dark area detection sensitivity A Test Conditions SW Mode SW70 SW68 SW64 B A A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 OPEN 1. Input the signal whose picture period amplitude is 0.18 V to #68 as shown in the figure below. 2. Measure #71 pin voltage DAMIN, DACEN, and DAMAX [V] when dark area detection sensitivity [1D] is set to MIN [00], CEN [04] and MAX [07]. #68 0.18 V #71 DAMIN･CEN･MAX [V] 57 2003-01-21 TA1360AFG Note No. Characteristics SW71 P17 DC restoration rate correction gain B Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #68. 2. Monitor DC level of #12 picture period. Set PS1 to V68 + 0.7 V, and adjust uncolor so that DC level is + 0.7. 3. Set DC restoration correction rate to minimum (000), and measure VDT1 and VDT2 of V68 [V] and V68 + 0.1 V as shown in the figure below. 4. Set #68 to V68 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT3. 5. Set DC restoration correction rate SW to less than 100 % (1), #68 to V68 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT4. 6. Calculate ADT100, ADT135, and ADT65 using following equations. ADT100 = (VDT2 [V] − VDT1 [V]) ÷ 0.1 [V] ADT135 = (VDT3 [V] − VDT1 [V]) ÷ 0.1 [V] ADT65 = 1 − ( (VDT2 [V] − VDT4 [V]) ÷ 0.1 [V]) V68 [V] Picture period V68 + 0.1 V 58 #12 waveform VDT1 VDT2 VDT3 VDT4 2003-01-21 TA1360AFG Note No. Characteristics SW71 P18 DC restoration rate correction point B Test Conditions SW Mode SW70 SW68 SW64 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #68. 2. Monitor DC level of #12 picture period. Set PS1 to V68 + 0.7 V, and adjust unicolor so that DC level is + 1.0. 3. Set DC restoration correction rate to minimum (000), and increase PS1 from V68. Plot relation between #74 (DC voltage) and #12 (voltage in picture period). 4. Set DC restoration correction rate to maximum (111), and increase PS1 from V68. Plot relation between #74 and #12. 5. Set DC restoration correction rate to maximum (111), DC restoration rate correction point (111), and increase PS1 from V68. Plot relation between #74 and #12. 6. Determine VDT0, and VDT1 using the following equations. VDT0 = [(VSP0 − V74)/1 V] × 100% VDT1 = [(VSP1 − V74)/1 V] × 100% #12 DC restoration rate correction point 000 DC restoration rate correction point 111 DC restoration correction rate 000 VSP0 VSP1 VPC 59 #74 2003-01-21 TA1360AFG Note No. Characteristics SW71 P19 DC restoration rate correction limit point B Test Conditions SW Mode SW70 SW68 SW64 B B C Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set unicolor to maximum (1111111), DC restoration rate correction point to minimum (000), and connect external power supply PS1 to #74. 2. Set DC restoration correction rate to maximum (111). 3. Increase PS from 5 V. Monitor #12, and plot DC restoration correction amount. 4. Repeat the step 3 above by changing data at DC restoration rate correction limit point. Measure the value using the figure below. Calculate PDTL60, PDTL75, PDTL87, and PDTL100 using following equations. PDTL60 = [(VL60 − V74)/1.0] × 100% PDTL75 = [(VL75 − V74)/1.0] × 100% PDTL87 = [(VL87 − V74)/1.0] × 100% PDTL100 = [(VL100 − V74)/1.0] × 100% #12 100% (00) 87% (01) 73% (10) 60% (11) VL60 VL75 60 VL100 VL87 #74 2003-01-21 TA1360AFG Note No. Characteristics SW71 P20 DC fluctuation at switching sharpness control peak frequency B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set unicolor [05] to MAX [7F], SRT gain [19] to MIN [00], and CDE [15] to CEN [80]. Input setup signal (0.2 Vp-p) to TPA as shown in the figure below. 2. Set sharpness [09] to MIN [00] and MAX [80]. Monitor #43, measure DC level VRDCMIN and VRDCMAX [V]. Calculate VRDC [V] using the following equation. VRDC = VRDCMIN − VRDCMAX [V] #68 0.2 V #12 VRDC* 61 2003-01-21 TA1360AFG Note No. Characteristics SW71 P21 Sharpness control range B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Input sine wave to TPA. (The frequency is variable.) 2. Set #68 amplitude to 20 mVp-p. 3. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). 4. Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12. 5. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. 6. Set picture sharpness to maximum (1111111). Set input frequency to FAP00, measure the amplitude VMAX00, and calculate GMAX00 using the following equations. 7. Set picture sharpness to minimum (0000000). Set input frequency to FAP00, measure the amplitude VMIN00, and calculate GMIN00 using the following equations. 8. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VMAX01/VMIN01 and calculate GMAX01/GMIN01. 9. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VMAX10/VMIN10 and calculate GMAX10/GMIN10. 10. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VMAX11/VMIN11 and calculate GMAX11/GMIN11. GMAX*** = 20 × log (VMAX*** ÷ V100) GMIN*** = 20 × log (VMIN*** ÷ V100) [dB] [dB] Note: When a spectrum analyzer is used, measure gain for low frequency. 62 2003-01-21 TA1360AFG Note No. Characteristics SW71 P22 Sharpness control center characteristic B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Input sine wave to TPA. (The frequency is variable.) 2. Set the amplitude of #68 to 20 mVp-p. 3. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). 4. Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #12. 5. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. 6. Set picture sharpness to center (1000000). Set input frequency to FAP00, measure #12 amplitude VCEN00, and calculate GCEN00 using the following equations. 7. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VCEN01 and calculate GCEN01. 8. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VCEN10 and calculate GCEN10. 9. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VCEN11 and calculate GCEN11. GCEN*** = 20 × log (VCEN*** ÷ V100) [dB] Note: When a spectrum analyzer is used, measure gain for low frequency. 63 2003-01-21 TA1360AFG Note No. Characteristics SW71 P23 2T pulse response SRT control B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. 2. Input 2T pulse (0.7 Vp-p) signal to TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10) picture sharpness control to center (1000000). Set APACON peak frequency to13.5 M (00), and monitor #12. 3. Measure TSRTMIN00 and VSRTMIN00 as shown in the figure below. 4. Set SRT-GAIN to maximum (11111), and measure TSRTMAX00 and VSRTMAX00. 5. Set APACON peak frequency to 9.5 M (01). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN01/VSRTMIN01 and TSRTMAX01/ VSRTMAX01. 6. Set APACON peak frequency to 6.4 M (10). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN10/VSRTMIN10 and TSRTMAX10/ VSRTMAX10. 7. Set APACON peak frequency to 4.5 M (11). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN11/VSRTMIN11 and TSRTMAX11/VSRTMAX11. 8. Calculate the following equations. TSRT00 = 20 × log [((VSRTMAX00/TSRTMAX00)/(VSRTMIN00/TSRTMIN00)) TSRT01 = 20 × log [(VSRTMAX01/TSRTMAX01)/(VSRTMIN01/TSRTMIN01)] TSRT10 = 20 × log [(VSRTMAX10/TSRTMAX10)/(VSRTMIN10/TSRTMIN10)] TSRT11 = 20 × log [(VSRTMAX11/TSRTMAX11)/(VSRTMIN11/TSRTMIN11)] T*** 20% V*** 100% 20% 64 2003-01-21 TA1360AFG Note No. Characteristics SW71 P24 VSM gain B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Input sine wave of FVSM frequency to TPA. Set #68 amplitude to 0.02 Vp-p. 2. Turn on SW77 and change VSM gain from minimum (001) to maximum (111). Measure #77 amplitude, V001, V011, V100, V101, V110, and V111. Set input amplitude to 0.7 Vp-p, and VSM gain to OFF (000). Measure TP77 amplitude V000. 3. Calculate the following equations. GV000 = 20 × log (V000/0.7) [dB] GV001 = 20 × log (V001/0.02) [dB] GV010 = 20 × log (V010/0.02) [dB] GV011 = 20 × log (V011/0.02) [dB] GV100 = 20 × log (V100/0.02) [dB] GV101 = 20 × log (V101/0.02) [dB] GV110 = 20 × log (V110/0.02) [dB] GV111 = 20 × log (V111/0.02) [dB] P25 VSM limit B B B A ON 1. Input sine wave of frequency FVSM to TPA. 2. Set VSM gain to 111, and #68 amplitude to 0.7 Vp-p. 3. Turn on SW77 and measure TP77 amplitude VLU and VLD [Vp-p] as shown in the figure below. VLU VLD 65 2003-01-21 TA1360AFG Note No. Characteristics SW71 P26 Y delay time switching B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and input 2T pulse signal (approximately 0.7 V (p-p)) to TPA. 2. Set picture sharpness to center (1000000). 3. Monitor #68 and #12 as shown in the figure below. Measure YDL00 that is the time difference between signals #68 and #12. 4. Set Y/C-DL1 to +5 ns (1), and measure YDL01 as shown in the figure below. 5. Set Y/C-DL1 to 0 ns (0), Y/C-DL2 to +10 ns (1) and measure YDL10 as shown in the figure below. 6. Set Y/C-DL1 to +5 ns (1), Y/C-DL2 to +10 ns (1) and measure YDL11 as shown in the figure below. 7. 2T pulse Approximately 0.7 Vp-p #12 #68 50% Determine YDLA, YDLB, and YDLC using the following equations. YDLA = YDL01 − YDL00 50% YDLB = YDL10 − YDL00 YDLC = YDL11 − YDL00 YDL00 YDL01 YDL10 YDL11 66 2003-01-21 TA1360AFG Note No. Characteristics SW71 P27 Y group delay correction B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Input Multi Burst signal (4.2-MHz frequency, 0.1 Vp-p at #68) of A signal in TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and Color detail enhancer (CDE) to minimum (00000). 2. Set sharpness to flat (DEC [30]), APACON peak frequency to 4.5 M (11), and monitor #12. 3. Sine wave signal A input becomes like signal B on #12 as shown in the figure on the right. Measure SA and SB. 4. When group delay correction is set to minimum (0000), signal A becomes like signal C on #12. Measure SAMIN and SBMIN. 5. When group delay correction is set to maximum (1111), signal A becomes like signal D on #12. Measure SAMAX and SBMAX. 6. Calculate the following equations. GAMIN = 20 × log (SAMIN/SA) [dB] GBMIN = 20 × log (SBMIN/SB) [dB] Signal A SA Signal B SB Signal C SAMIN GAMAX = 20 × log (SAMAX/SA) [dB] SBMIN GBMAX = 20 × log (SBMAX/SB) [dB] SAMAX Signal D SBMAX Note: Sine wave input starts and ends within the picture period such as a burst signal. The wave is not continuous. 67 2003-01-21 TA1360AFG Note No. Characteristics SW71 P28 Color detail enhancer (CDE) B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), color to center (1000000), and color limiter level to 2 Vp (1). Input SWEEP signal to TPA so that #68 amplitude is 20 mVp-p. Set SW67 to A, and input signal as shown in the figure below (#67 amplitude is 0.2 Vp-p) to TP67. 2. Set picture sharpness to center (1000000), Y detail control to center (1000), and monitor #14 with a spectrum analyzer. 3. When CDE is at minimum (00), set low frequency area to 0dB, and determine peak level GCDEMIN. 4. When CDE is at maximum (11), set low frequency area to 0dB, and determine peak level GCDEMAX. 5. Calculate the following equation. GCDE00 = GCDEMAX00 − GCDEMIN00 6. When APACON peak frequency is 13.5 M (00), 9.5 M (01), 6.4 M (10), and 4.5 M (11), calculate GCDE00, GCDE01, GCDE10, and GCDE11 respectively using above equation. Output gain [dB] max 0.2 Vp-p min 0dB BLK period picture period Input frequency [MHz] 68 2003-01-21 TA1360AFG Note No. Characteristics SW71 P29 Y detail control range B Test Conditions SW Mode SW70 SW68 SW64 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW74 ON 1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10), and APACON peak frequency to 4.5 M (11). Input SWEEP signal to TPA. 2. Set #68 amplitude to 20mVp-p. 3. Set picture sharpness to center (1000000), Y detail control to maximum (1111), and monitor #12 with a spectrum analyzer. 4. Set low frequency area to 0dB, and measure each peak level GYDMAX. 5. Set Y detail control to center (1000), and measure peak level GYDCEN. 6. Set Y detail control to minimum (0000), and measure peak level GYDMIN. 69 2003-01-21 TA1360AFG Test Conditions for Color Difference Block 1: YUV input and matrix Common Test Condition for Color Difference Block 1: YUV input and matrix 1. 2. 3. 4. Note No. SW71 = B, SW70 = B, SW44 = ON, SW18 to SW26 = A, SW77 = OPEN, SW74 = OPEN Transfer BUS control data with preset values. Turn ACB operation switching to ACB OFF (0), and turn high blight color OFF (0). Input sync signal [must be sync with input signal for testing except Sweep.] to #53 (sync input), and set SYNC-IN-SW to 1. Characteristics SW68 S01 Color SRT gain Test Conditions SW Mode SW67 SW66 Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW64 C A A B SW63 SW61 SW60 ― B B B ― 1. Set Y mute ON (P-MODE: Y-MUTE, 001), brightness to center (10000000), color to center (1000000), unicolor to maximum (1111111). 2. Input 2T pulse signal to TP67 so that #67 amplitude is 423 mVp-p. 3. Monitor #14 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SB00MIN, SB00CEN, and SB00MAX as shown in the figure below. Set SB00MIN to 0dB, calculate GSB00CEN = 20 × log (SB00CEN/SB00MIN) and GSB00MAX = 20 × log (SB00MAX/SSB00MIN). 4. When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSB01CEN and GSB01MAX. 5. Input 2T pulse signal to TP66 so that #66 amplitude is 300 mVp-p. 6. Monitor #12 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SR00MIN, SR00CEN, and SR00MAX as shown in the figure below. Set SR00MIN to 0dB, calculate GSB00CEN = 20 × log (SB00CEN/SB00MIN) and GSB00MAX = 20 × log (SB00MAX/SSB00MIN). T*** When color SRT peak is 7. 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSR01CEN and GSR01MAX. Gradient S*** = V***/T*** 20% V*** 100% 20% 70 2003-01-21 TA1360AFG Note No. Characteristics SW68 S02 Dynamic Y/C compensation Test Conditions SW Mode SW67 SW66 C A A SW63 SW61 SW60 B B B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW64 B 1. SW74 2. OPEN Input 100-kHz sync signal to TP67, and set #67 amplitude to 0.2 Vp-p. Set Y mute OFF (P-MODE: Normal 1, 000), brightness to center (1000000), color to center (1000000), unicolor to maximum (1111111), and Y/C Gain Comp to minimum (00). Set black stretch point 1 to OFF (000), dark area static Yγ gain to minimum (00), light area static Yγ gain to maximum (11), and SW1 to B. Apply 5.16 V to #68 from external power supply PS1. 3. Monitor #14 output waveform, and measure amplitude VBDY0. 4. Set Y/C Gain Comp to maximum (11). Set SW1 to B. Set black stretch point 1 to OFF (000), dark area static Yγ gain to maximum (11), light area static Yγ gain to maximum (00), and monitor #14 amplitude VBDY1. 5. Set Y/C Gain Comp to maximum (11). Switch SW1 to A, and TPI to GND. Set black stretch point 1 to maximum (111), dark area static Yγ gain to minimum (00), bright area static Yγ gain to maximum (11), and monitor #14 amplitude VBDY2. 6. Calculate the following equations. GCBDY1 = 20 × log (VBDY1/VBDY0), GCBDY2 = 20 × log (VBDY2/VBDY0) 7. Input 100-kHz sync signal to TP5, and repeat the procedure above. Calculate the following equations. GCRDY1 = 20 × log (VRDY1/VRDY0), GCRDY2 = 20 × log (VRDY2/VBDY0) 71 2003-01-21 TA1360AFG Note No. Characteristics SW68 S03 YUV gain Test Conditions SW Mode SW67 SW66 Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW64 A/C A/B A/B B SW8 SW9 SW10 SW56 B B B OPEN 1. Set picture mute to OFF (P-MODE: Normal 1, 000), brightness to maximum (11111111), color to center (1000000), and unicolor to maximum (1111111). 2. Set SW68 to A. Set SW67 and SW66 to B, and input 100-kHz sine wave to TPA. Set #68 amplitude to 0.2 Vp-p. 3. Set SW74 open. Measure #74 amplitude VY00 and VY01 when Y/color difference input mode is set to Y/Cb/Cr (0) and Y/Pb/Pr (1). 4. Set SW68 to C, SW67 to A, and SW66 to B. Input 100-kHz sine wave to TP67, and set #67 amplitude to 0.2 Vp-p. 5. Measure #14 amplitude VB00 when Y/color difference input mode is set to Y/Cb/Cr (0). 6. Measure #14 and #12 amplitude VBB01 and VBR01 when Y/color difference input mode is set to Y/Pb/Pr (1). 7. Set SW68 to C, SW67 to B, and SW66 to A. Input 100-kHz sine wave to TP66, and set #66 amplitude to 0.2 Vp-p. 8. Measure #12 amplitude VR00 when Y/color difference input mode is set to Y/Cb/Cr (0). 9. Measure #14 and #12 amplitude VRB01 and VRR01 when Y/color difference input mode is set to Y/Pb/Pr (1). 10. Calculate the following equations. GY00 = 20 × log (VY00/0.2), GY01 = 20 × log (VY01/0.2) GCBB = 20 × log (VB00/0.2), GPBB = 20 × log (VBB01/0.2), GPBR = 20 × log (VBR01/0.2) GCRR = 20 × log (VR00/02), GPRB = 20 × log (VRB01/0.2), GPRR = 20 × log (VRR01/0.2) 72 2003-01-21 TA1360AFG Note No. Characteristics SW68 S04 Green stretch Test Conditions SW Mode SW67 SW66 C A A SW26 SW25 SW24 A A A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW64 1. SW21 2. Input signal B as shown in the figure below from TP67 (Cb/Pb1 input), and signal A from TP66 (Cr/Pr input). Set brightness [06] to maximum (FF). A 3. Measure amplitudes A, B, C, D, and E at #13 (Gout) as shown in the figure below. (A00 to E00) Set green stretch [14] data to (08), and repeat the step 3 above. (A01 to E01) SW19 SW18 4. A A 5. Set green stretch [14] data to (10), and repeat the step 3 above. (A10 to E10) 6. Set green stretch [14] data to (18), and repeat the step 3 above. (A11 to E11) 7. Green stretch gain is calculated by the following equations A01 A00 B01 GrB01= B00 C01 GrC01 = C00 D01 GrD01 = D00 E01 GrE01= E00 A10 A00 B10 GrB10 = B00 C10 GrC10 = C00 D10 GrD10 = D00 E10 GrE10 = E00 GrA01 = GrA10 = A11 A00 B11 GrB11 = B00 C11 GrC11 = C00 D11 GrD11 = D00 E11 GrE11= E00 GrA11= 0.05 Vp-p ±0 Vp-p −0.05 Vp-p Signal A −0.087 Vp-p −0.1 Vp-p ±0 Vp-p Signal B −0.07 Vp-p −0.122 Vp-p −0.122 Vp-p −0.14 Vp-p B C A Pin 13 73 150° 180° D 210° 240° E 270° 2003-01-21 TA1360AFG Test Conditions for Color Difference Block 2 Common Test Conditions for Color Difference Block 2 1. 2. 3. Note No. SW71 = B, SW70 = B, SW61 to SW63 = B, SW44 = ON, SW40 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78) Characteristics SW68 A01 Color difference contrast adjustment characteristic C SW67 SW66 Test Conditions SW Mode SW26 SW25 SW24 Test Method SW21 SW19 SW18 A A A A A 1. Set brightness to maximum, and subaddress (12) data to (F0). or or 2. Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.23 Vp-p) from pin 66. B B 3. Change unicolor data to maximum (7F), center (40), and minimum (00), and measure pin 12 picture period amplitude VuCYMAX, VuCYCNT, and VuCYMIN respectively. 4. Determine unicolor amplitude ratio between maximum and minimum in decibels. (∆VuCY) 5. Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.2 Vp-p) from pin 67, and measure pin 14. A A A 74 2003-01-21 TA1360AFG Note No. A02 Characteristics Color adjustment characteristic SW68 SW67 SW66 C A A or B A03 Color difference halftone characteristic C Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Set brightness to maximum, and subaddress (12) data to (F0). or 2. Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.115 Vp-p) from pin 66. B 3. Change color data to maximum (7F), center (40), and minimum (01), and measure pin 12 picture period amplitudes VCCYMAX、VCCYCNT, and VCCYMIN respectively. 4. Calculate amplitude ratios of maximum and minimum against color center in decibels. (∆VCCY) 5. Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.1Vp-p) from pin 67 and measure pin 14. A A 1. Input signal 3 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 66. or or 2. Measure pin 12 output picture period amplitude vHTARY. B B 3. Apply 1.5 V to pin 79 from external power supply. A A A A A 75 A 4. Measure pin 12 output picture period amplitude vHTBRY. 5. Calculate GHTRY = vHTBRY/vHTARY 6. Repeat the steps 1 to 5 above and measure pin 13. Calculate GHTGY = vHTBGY/vHTAGY 7. Repeat the steps 1 to 5 above and measure pin 67. Calculate GHTBY = vHTBBY/vHTABY. 2003-01-21 TA1360AFG Note No. A04 Characteristics Color γ characteristic SW68 SW67 SW66 C B A Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 2 from pin 66. 2. Increase signal 2 amplitude A. Determine gamma correction point Vγ1, Vγ2, and Vγ3 of subaddress data (14). Set subaddress (14) data as follows: (01) − γOFF (03) −γ1ON (05) −γ2ON (07) −γ3ON Measure #12 output signal amplitude levels and chart a characteristic diagram. 3. Determine Vγ where γ starts applying and gradient ∆ at γ ON when linearity at γ OFF is 1. #12 output amplitude γOFF Vγ γON #66 input amplitude 76 2003-01-21 TA1360AFG Note No. A05 A06 Characteristics SW68 SW67 SW66 Color limiter characteristic C B A High-bright color gain C B A Test Conditions SW Mode SW26 SW25 SW24 A A A A A A Test Method SW21 SW19 SW18 A A A A A 77 A 1. Input signal 2 (picture period amplitude = 0.56 Vp-p) from pin 67. 2. Set subaddress (14) to (00)/(01), and measure pin 12 output signal picture period amplitude, CLT0/CLT1. 1. Input signal 2 (picture period amplitude = 0.28 Vp-p) from pin 67. 2. 3. Adjust color so that pin 14 output picture period amplitude is 1.2 Vp-p. Set subaddress (0B) data to (80) and measure pin 14 output signal picture period amplitude v14. 4. Calculate the following equation. HBC1 = (1.2 − v14)/1.2 2003-01-21 TA1360AFG Test Conditions for Text Block Common Test Conditions for Text Block 1. 2. 3. SW71 = B, SW70 = B, SW60 to SW64 = B, SW44 = ON, SW40 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78) Note Characteristics No. T01 AC gain SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. 2. Measure pins 12, 13, and 14 picture period amplitude, V12, V13, and V14. 3. Calculate AC gain using the following equations. GR = V12/0.2 GG = V13/0.2 GB = V14/0.2 T02 T03 Unicolor adjustment characteristic Brightness adjustment characteristic A A B B B B A A A A A A A A A A A A 78 1. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. 2. Change unicolor data to maximum (7F), center (40), and minimum (00) and measure pin 12 picture period amplitude, VuMAX, VuCNT, and VuMIN respectively. 3. Calculate amplitude ratio of VuMAX and VuMIN in decibels (∆Vu) 1. 2. Input signal 2 from pin 68 and adjust pin 12 picture period output amplitude to 1 Vp-p. Change brightness data to maximum (7F), center (80), and minimum (00) and measure pin 12 voltages, VbrMAX, VbrCNT, and VbrMIN respectively. 2003-01-21 TA1360AFG Note Characteristics No. T04 T05 T06 White peak slice level SW68 SW67 SW66 C B B Black peak slice level C RGB output S/N C B B B B Test Conditions SW Mode SW26 SW25 SW24 A A A A A A A A A Test Method SW21 SW19 SW18 A A A A A A A A A 1. Set subcontrast to maximum. 2. Apply external power supply to pin 68 and gradually increase voltage from 5.8 V. 3. When picture period of pin 12 is clipped, measure pin 12 picture period amplitude voltage, Vwps1. 4. Change subaddress (0C) data to (FC) and repeat the steps 1 to 3 above. (Vwps2) 1. Apply external power supply to pin 68 and gradually decrease voltage from 5.8 V. 2. When picture periods are clipped, measure pins 14, 13, and 12 voltage, Vbps. 1. Adjust brightness data so that picture period voltage of pin 14 is 2.4 V. 2. Set color data to minimum. 3. Measure noise levels n14-, n13-, and n12-Vp-p in picture period of pin 14, 13, and 12 with an oscilloscope. 4. Calculate S/N. N14 = −20 × log [2.3/(0.2 × n14)] N13 = −20 × log [2.3/(0.2 × n13)] N12 = −20 × log [2.3/(0.2 × n12)] T07 Halftone characteristic A B B A A A A A A 79 1. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. 2. Measure pin 14 picture period amplitude v14A. 3. Apply 1.5 V to pin 79 from external power supply. 4. Measure pin 14 picture period amplitude v14B 5. Calculate the following equation. GHT1 = v14B/v14A 6. Stop applying voltage to pin 79. Set subaddress (1A) to data (E2) and measure pin 14-picture period amplitude, v14C. 7. Calculate the following equation. GHT2 = v414C/v14A 2003-01-21 TA1360AFG Note Characteristics No. T08 BLK pulse delay time SW68 SW67 SW66 C B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Apply signal shown in the figure (A) below to pin 39 (BLK input), and measure tdON and tdOFF of output signals from pins 12, 13, and 14 shown in the figure (B) below. 63.5 µs (A) Appling signal to pin 39 tdON tdOFF (B) Output signal from pins 12, 13, and 14 80 2003-01-21 TA1360AFG Note Characteristics No. T09 Drive adjustment variable range SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. 2. Measure picture period amplitude of pin 13 when subaddress (0D) data is changed to maximum (FE), center (80), and minimum (00). 3. Use picture period amplitude at center as the base. Determine amplitude ratio DRG1+ and DRG1− at maximum and minimum in decibels. 4. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 14, DRB1+ and DRB1− in decibels when subaddress (0E) data is changed. 5. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 13, DRG2+ and DRG2− in decibels when subaddress (0E) center data is set to (81) used as the base. 6. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DRB2+ and DRB2− in decibels when subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). 7. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DRR1+ and DRR2− in decibels when subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01). 8. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 14, DRB3+ and DRB3− in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed. 9. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 13, DRG3+ and DRG3− in decibels when subaddress (0E) data is set to (81), and subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01). 10. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 12, DRR2+ and DRR2− in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). T10 #78 input impedance C B B A A A A A A 1. Connect external power supply, an ammeter, and a voltmeter to pin 78. Adjust voltage so that current value is set to zero. 2. Measure the current when voltage of pin 78 is increased by 0.2V. (lin) 3. Calculate the following equation.Ｚin53 = 0.2 V/Iin (Ω) 78 − A + Ammeter (µA) 81 V Voltmeter 2003-01-21 TA1360AFG Note Characteristics No. T11 ACL characteristic SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 68. 2. Measure pin 12 picture period amplitude, vACL1. 3. Apply “DC voltage of pin 78 − 0.8 V” to pin 78 from external power supply and measure pin 12-picture period amplitude, vACL2. 4. Apply “DC voltage of pin 78 − 1.3 V” to pin 78 from external power supply and measure pin 12-picture period amplitude, vACL3. 5. Calculate the following equations. ACL1 = −20 × log (vACL2/vACL1) ACL2 = −20 × log (vACL3/vACL1) T12 ABL point C B B A A A A A A 1. Measure DC voltage of pin 78, VABL1. 2. Set subaddress (1B) data to (1C). 3. Apply external voltage to pin 78, and decrease voltage from 6.5 V. When voltage of pin 12 starts changing, measure pin 78 voltage, VABL2. 4. Change subaddress (1B) data to (3C), (5C), (7C), (9C), (BC), (DC), and (FC) under the status of the step 3 above. Measure pin 78 voltage: VABL3, VABL4, VABL5, VABL6, VABL7, VABL8, and VABL9. 5. ABLP1 = VABL2 − VABL1 ABLP5 = VABL6 − VABL1 ABLP2 = VABL3 − VABL1 ABLP6 = VABL7 − VABL1 ABLP3 = VABL4 − VABL1 ABLP7 = VABL8 − VABL1 ABLP4 = VABL5 − VABL1 ABLP8 = VABL9 − VABL1 82 2003-01-21 TA1360AFG Note Characteristics No. T13 ABL gain SW68 SW67 SW66 C B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Apply 6.5-V external voltage to pin 78. 2. Set subaddress (1B) data to (00). 3. Set brightness data to maximum. 4. Apply 4.5-V external voltage to pin 78. 5. Change subaddress (1B) data to (00), (04), (08), (0C), (10), (14), (18), and (1C). Repeat the step 3 above, and measure VABL11, VABL12, VABL13, VABL14, VABL15, VABL16, VABL17, and VABL18. 6. ABLG1 = VABL11 − VABL10 ABLG2 = VABL12 − VABL10 ABLG3 = VABL13 − VABL10 ABLG4 = VABL14 − VABL10 ABLG5 = VABL15 − VABL10 ABLG6 = VABL16 − VABL10 ABLG7 = VABL17 − VABL10 ABLG8 = VABL18 − VABL10 T14 RGB output mode C B B A A A A A A 83 1. Adjust brightness data so that picture period voltage of pin 12 is 2.4 V. 2. Set subaddress (1B) data to (01). 3. Measure pins 12, 13, and 14 picture period voltage, V12R, V13R, and V14R. 4. Set subaddress (1B) data to (02), and repeat the step 3 above. Measure pins 12, 13, and 14 picture period voltage, V12G, V13G, and V14G. 5. Set subaddress (1B) data to (03), and repeat the step 3 above. Measure pins 12, 13, and 14 picture period voltage, V12B, V13B, and V14B. 2003-01-21 TA1360AFG Note Characteristics No. T15 Y-OUT γ characteristic SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input RAMP waveform from pin 68. Adjust input amplitude so that picture period amplitude of pin 12 is 2.3 Vp-p. 2. Set subaddress (0C) data to (81). 3. Adjust input amplitude so that picture period amplitude of pin 12 is 2.3 Vp-p. 4. Monitor pin 12. According to the figure below, determine Y-OUT γ correction start points γ1 and γ2. Also determine ratios of gradients at Y-OUT ON to Y-OUT OFF in decibel. (∆1, ∆2, and ∆3) Output amplitude (Y-OUT) 100 IRE ∆3 γ2 ∆2 γ1 2.3 Vp-p ∆1 Note: Solid line indicates gamma OFF. Dotted line indicates gamma ON. Input amplitude 84 2003-01-21 TA1360AFG Note Characteristics No. T16 White-peak blue characteristic SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input 0.7-Vp-p RAMP signal from pin 68. 2. Set subcontrast data to maximum. 3. Set subaddress (1F) data to (04). 4. Set subaddress (1E) data to (01), and monitor pin 14. Determine blue stretch start point BSPmin using the figure below. 5. Repeat the step 4 above by changing subaddress (1E) data to (04) and (07). Determine blue stretch start point BSPCNT and BSPmax. 6. Set subaddress (1E) data to (04). 7. Monitor pin 14 and calculate ratio of blue stretch ON gradient in relative to blue stretch OFF gradient in decibel (BSGCNT) using the figure below. 8. Repeat the step 7 above by changing subaddress (1F) data to (00) and (07). Calculate gradient ratio in decibel (BSGmin and BSGmax). Note: Calculate white-peak blue start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. ON Output (Output from pin 14) OFF Start point Input amplitude 85 2003-01-21 TA1360AFG Note Characteristics No. T17 ACB insertion pulse phase and amplitude SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive 2. gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set brightness data to 108. Measure pins 4, 6, and 7 voltage. Apply measured voltages from external power supply. 3. Set subaddress (02) data to (40). 4. Use output signals from pins 12, 13, and 14, and measure ACB insertion pulse phase as shown in the Figure 1. or C Note: Take picture period following FBP input fall after V・BLK ends as phase 1H. After next H･ BLK, count the phase as 2H, 3H, and so on. ACB insertion pulse V･BLK period Figure 1: RGB Output 1H 2H 3H 4H Figure 2: FBP Input (#39) 86 5. Monitor pins 12, 13, and 14. Measure ACB insertion pulse amplitudes (level from picture period amplitude at quiescent.): VACB1R, VACB1G, and VACB2B. 6. Set subaddress (02) data to (80), and repeat the step 5 above: VACB2R, VACB2G, and VACB2B. 7. Set subaddress (02) data to (C0), and repeat the step 5 above: VACB3R, VACB3G, and VACB3B. 2003-01-21 TA1360AFG Note Characteristics No. T18 IK input amplitude SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive 2. gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set subaddress (02) data to (40). 3. Measure voltage amplitude of pin-8 input signal in ACB insertion period. or C 1H = IKR T19 T20 T21 IK input cover range Analog RGB gain Analog RGB white peak slice level C A A B B B B B B A A A A A A or or or B B B A A A A A A A A A A A A 87 2H = IKG 3H = IKB 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive 2. gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Set subaddress (02) data to (40). 3. Measure pin 8 DC voltage in V･BLK period. (#8VBLK) 4. Apply the current externally to pin 8. 5. Measure DC voltage of pin 8 in V･BLK period when pin-12 picture period voltage begins to be decreased. (#8VBLK+) 6. Apply current outward from pin 8. 7. Measure DC voltage of pin 8 in V･BLK period when pin-12 picture period voltage begins to be increased. (#8VBLK−) 8. DIKin+ = (#8VBLK+) − (#8VBLK) DIKin− = (#8VBLK−) + (#8VBLK) 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive 2. gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. Apply 5-V external voltage to pin 2. 3. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. 4. Measure pin 12 picture period amplitude, v12R. 5. Repeat the steps 3 and 4 above with the following pins: Input from pin 25, and measure output from pin 13 (v13G). Input from pin 26, and measure output from pin 14 (v14B). 6 Calculate the following equations. GTXR = v12R/0.2 GTXG = v13G/0.2 GTXB = v14B/0.2 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pin 2. 3. Set RGB contrast data to maximum (7F). 4. Input signal 2 to pin 24. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. 5. Repeat the steps 3 and 4 above with following pins: Input from pin 25 and measure output from pin 13. Input from pin 26 and measure output pin 14. 2003-01-21 TA1360AFG Note Characteristics No. T22 T23 T24 T25 Analog RGB black peak limit level RGB contrast adjustment characteristic Analog RGB brightness adjustment characteristic Analog RGB mode switching transfer characteristic SW68 SW67 SW66 A B B A A C B B B B B B Test Conditions SW Mode SW26 SW25 SW24 A A A A A A or or or B B B A A A or or or B B B A A A Test Method SW21 SW19 SW18 A A A A A A A A A A A A 88 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pin 2. 3. Set RGB contrast data to maximum (7F). 4. Input signal 2 to pin 24. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. 5. Repeat the step 4 above with the following pins: Input from pin 25 and measure output from pin 13. Input from pin 26 and measure output pin 14. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pin 2. 3. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. 4. RGB contrast data to maximum (7F), center (40), and minimum (00). Measure pin 12 picture period amplitudes VuTXR (maximum, center, and minimum) respectively. 5. Calculate amplitude ratio of maximum and minimum in decibels. 6. Repeat the steps 4 and 5 above with the following pins: Input from pin 25 and measure pin 13. Input from pin 26 and measure pin 14. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Input signal 2 from pins 26, 25, and 24. 3. Apply 5-V external voltage to pin 2. 4. Adjust amplitude A of signal 2 so that picture period amplitude of pin 12 is 0.5 Vp-p. 5. Change RGB brightness data to maximum (FE), center (80), and minimum (00). Measure pins 12, 13, and 14 picture period voltage VbrTX (maximum, center, and minimum) respectively. 1. Set RGB brightness data to maximum (FE). 2. Input signal 4 (signal amplitude = 1.5 Vp-p) from pin 2. 3. Measure input/output transfer characteristics using pin 12 according to the figure T-2. 4. Repeat the steps 2 and 3 above with the following pins: Input from pin 25 and measure pin 13. Input from pin 24 and measure pin 14. 5. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above. 2003-01-21 TA1360AFG Note Characteristics No. T26 Text ACL characteristic SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A B Test Method SW21 SW19 SW18 A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pin 2. 3. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 24. 4. Measure pin 12 picture period amplitude, vTXACL1. 5. Apply “pin 78 DC voltage − 0.8 V” to pin 78 from external power supply, and measure pin 12-picture period amplitude, vTXACL2. 6. Apply “pin 78 DC voltage − 1.3 V” to pin 78 from external power supply, and measure pin 12-picture period amplitude, vTXACL3. 7. TXACL1 = −20 × log (vTXACL2/vTXACL1) TXACL2 = −20 × log (vTXACL3/vTXACL1) T27 T28 T29 Analog OSD gain Analog OSD input white peak slice level Analog OSD black peak limit level A A A B B B B B B A A A A A A A A A A A A or or or B B B A A A A A A 89 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pins 1 and 80. 3. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. 4. Measure pin 12 picture period amplitude, v12R. 5. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21 and measure pin 14. (v13G and v14B) 6. Calculate the following equations. GOSDR = v12R/0.2 GOSDG = v13G/0.2 GOSDB = v14B/0.2 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pins 1 and 80. 3. Input signal 2 from pin 18. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. 4. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21, and measure pin 14. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pins 1 and 80. 3. Input signal 2 from pin 18. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 12 is clipped. 4. Repeat the step 3 above with the following pins: Input from pin 19, and measure pin 13. Input from pin 21, and measure pin 14. 2003-01-21 TA1360AFG Note Characteristics No. T30 T31 OSD contrast adjustment characteristic Analog OSD brightness adjustment characteristic SW68 SW67 SW66 A B B C B B Test Conditions SW Mode SW26 SW25 SW24 A A A A A A Test Method SW21 SW19 SW18 A A A or or or B B B A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pins 1 and 80. 3. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. 4. Change OSD contrast data to (11), (10), (01), and (00). Measure pin 12 picture period amplitude VuOSDR (11), (10), (01), and (00) respectively. 5. Repeat the steps 3 and 4 above with the following pins: Input from pin 19, and measure pin 13, VuOSDG (11), (10), (01), and (00). Input from pin 21, and measure pin 14, VuOSDB (11), (10), (01), and (00). 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Apply 5-V external voltage to pins 1 and 80. 3. Change OSD brightness data (subaddress 1D) to (38), (78), (B8), and (F8), and measure picture period voltage of pins 12, 13, and 14 respectively. Data (38) = VbrOSD0 Data (78) = VbrOSD1 Data (B8) = VbrOSD2 Data (F8) = VbrOSD3 T32 Analog OSD mode switching transfer characteristic C B B A A A A A A 90 1. Set OSD brightness data to maximum (11). 2. Input signal 4 (signal amplitude = 4.5 Vp-p) from pin 1. 3. Measure input/output transfer characteristics using pin 12 according to the figure T-2. 4. Repeat the steps 2 and 3 above, and measure pins 13 and 14. 5. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above. 6. Repeat the steps 1 to 5 above with the following pin. Input signal 4 (signal amplitude 4.5 Vp-p) from pin 80. 2003-01-21 TA1360AFG Note Characteristics No. T33 OSD ACL characteristic SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A B 91 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. Control drive gain adjustment data so that pins 14 and 13 picture period amplitude equals that of pin 12. 2. Set subaddress (07) data to (01). 3. Apply 5-V external voltage to pins 1 and 80. 4. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 18. 5. Measure pin 12 picture period amplitude, vOSDACL1. 6. Apply “pin 78 DC voltage − 0.8 V” to pin 78 from external power supply, and measure pin 12-picture period amplitude, vOSDACL2. 7. Apply “pin 78 DC voltage − 1.3 V” to pin 78 from external power supply, and measure pin 12-picture period amplitude, vOSDACL3. 8. OSDACL1 = −20 × log (vOSDACL2/vOSDACL1) OSDACL2 = −20 × log (vOSDACL3/vOSDACL1) 9. OSDACL3、OSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8 above to measure OSDACL3 and OSDACL4. 2003-01-21 TA1360AFG Note Characteristics No. T34 OSD blending characteristic SW68 SW67 SW66 A B B ↓ C Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A B 1. ↓ ↓ ↓ 2. Measure pins 14, 13, and 12 picture period amplitude, v14a, v13a, and v12a. B 3. Apply 5-V external voltage to pin 80. 4. Measure pins 14, 13, and 12 picture period amplitude, v14b, v13b, and v12b. 5. Calculate v14b amplitude in relation to v14a, v13b amplitude in relation to v13a, and v12b amplitude in relation to v12a in decibel: α14TV1, α13TV1, and α12TV1. 6. Apply 5-V external voltage to pin 1, and repeat the steps 3 to 5 above: α14TV2, α13TV2, and α12TV2. 7. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 3 to 5 above: α14TV3, α13TV3, and α12TV3. 8. Set SW68 to C. Set SW21, 19, and 18 to B. 9. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pins 21, 19, and 18. B B Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 68. 10. Apply 5-V external voltage to pins 1 and 80. 11. Measure pins 14, 13, and 12 picture period amplitude, v14c, v13c, and v12c. 12. Apply 5-V external voltage to pin 1. 13. Measure pins 14, 13, and 12 picture period amplitude, v14d, v13d, and v12d. 14. Calculate v14d amplitude in relation to v14c, v13d amplitude in relation to v13c, and v12d amplitude in relation to v12c in decibel: α14OSD1, α13OSD1, and α12OSD1. 15. Apply 5-V external voltage to pin 80, and repeat the steps 12 to 14 above: α14OSD2, α13OSD2, and α12OSD2. 16. Apply 5-V external voltage to pins 1 and 80, and repeat the steps 12 to 14 above: α14OSD3, α13OSD3, and α12OSD3. 92 2003-01-21 TA1360AFG Note Characteristics No. T35 Blue stretch point/gain SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input RAMP signal 0.7 Vp-p from pin 68. 2. Set subcontrast data to maximum. 3. Set subaddress (15) data to (0C). 4. Set subaddress (1A) data to (C0), monitor pin 14, and measure blue stretch start point using the figure below (BLPmin). 5. Set subaddress (1A) data to (CC), and repeat the step 4 above. (BLPmax) 6. Set subaddress (1A) data to (C4). 7. Monitor pin 14 and measure gradient at blue stretch ON in decibel in relation to the one at blue stretch OFF according to the figure below. (BLGmax) 8. Set subaddress (15) data to (04), and repeat the step 7 above. (BLGmin) Note: Calculate blue stretch start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. Output amplitude Blue stretch ON Blue stretch OFF Input amplitude 93 2003-01-21 TA1360AFG Note Characteristics No. T36 Blue stretch gamma correction SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Input RAMP signal 0.7 Vp-p from pin 68. 2. Set subcontrast data to maximum. 3. Set subaddress (15) data to (08). 4. Set subaddress (09) data to (81). 5. Monitor pin 14 and measure amplitude of the intersection point of blue stretch γ OFF and blue stretch γ ON according to the figure below. Calculate pin 14 output amplitude in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. 6. Set subaddress (1A) data to (C4), (C8), and (CC). Repeat the step 5 above. (BLγ2, BLγ3, and BLγ4) Output amplitude Blue stretch γ OFF Blue stretch γ ON BLγ Intersection poiint Input amplitude 94 2003-01-21 TA1360AFG Note Characteristics No. T37 White letters improvement SW68 SW67 SW66 A B B Test Conditions SW Mode SW26 SW25 SW24 A A A Test Method SW21 SW19 SW18 A A A 1. Apply a pulse to pin 68 as shown in Figure A. 2. Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal amplitude from 0 to 120 IRE (0.857 Vp-p) (See Figure B below). 3. Set subaddress (19) data to (80). 4. Monitor # 12 output waveform. Plot # 12 output amplitude when changing # 68 input signal amplitude from 0 to 120 IRE (0.857 Vp-p). Then, compare to the plot in the step 2, calculate a point where a gradient changes (WPL1). 5. Repeat the step 4 above by changing subaddress (19) data to (83) and (86). Calculate points where gradients change (WPL2, WPL3). 80 ns Figure A # 12 output amplitude Data 87 Data 86 WPL3 Data 83 WPL2 Data 80 WPL1 # 68 input amplitude Figure B 95 2003-01-21 TA1360AFG Test Condition for Synchronization Block Common Test Conditions for Synchronization Block: unless otherwise specified, VCC = 9 V, Ta = 25°C, bus data; preset value, SW68 = A, SW53 = A, SW INPUT = B, SW44 = ON, SW41 = OPEN, SW40 = B, SW39a = B, SW39b = OPEN, SW37 = B Note Characteristics Test Conditions HA01 Sync input horizontal 1. sync phase 2. Input signal A (as shown in the figure below) to TPA. Set subaddress (00) data to 82H. Monitor # 53 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (SPH). 29.36 µs Signal A 0.285 V 0.593 µs SPH #44 waveform HA02 HD input horizontal sync phase 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50. 3. Monitor #50 (Sync input) and #44 (AFC filter) waveforms. Measure phase difference (HDPH). 31.75 µs Signal B 1.5 V 2.35 µs HDPH #44 waveform 96 2003-01-21 TA1360AFG Note Characteristics HA03 Polarity detection range Test Conditions 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50 pin. 3. Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B duty (HDDUTY1) when #50 input signal phase no longer locks with that of #37 (H-OUT). 4. Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty (HDDUTY2) when #39 (FBP input) phase changes in relation to signal B. 5. Further increase signal B duty (to longer negative polarity period) and measure signal B duty (HDDUTY3) when #50 input signal phase no longer locks with that of #37 (H-OUT). 6. Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B duty (HDDUTY4) when #39 (FBP input) phase changes in relation to signal B. 31.75 µs Signal B 1.5 V A B Duty = A/B × 100% (0 to 100%) HA04 Sync input threshold amplitude 1. Set subaddress (00) data to 82H, and TEST mode to 01. 2. Connect variable power supply to #53 via 20-kΩ resistor. 3. Set variable power supply voltage to 0 V, and measure #53 voltage. (SYNC_TIP_00) Also check that #34 voltage is set to Low (GND level). 4. Increase variable power supply voltage so that #34 voltage becomes High (VCC level). Measure #53 voltage. (SYNC_OFF_00) 5. Calculate the following equation to determine SYNC input separation level at SYNC separation level is 00. VthS00 = (SYNC_OFF_00 − SYNC_TIP_00)/0.286 × 100 6. Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine VthS01, VthS10, and VthS11. VthS01 = (SYNC_OFF_01 − SYNC_TIP_01)/0.286 × 100 VthS10 = (SYNC_OFF_10 − SYNC_TIP_10)/0.286 × 100 VthS11 = (SYNC_OFF_11 − SYNC_TIP_11)/0.286 × 100 ＃53 1H 40IRE (= 286 mVp-p) 0.08H Sync separation level Sync tip level ＃34 (SYNC output mode） 97 2003-01-21 TA1360AFG Note Characteristics HA05 HD input threshold amplitude Test Conditions 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50. 3. Increase signal B amplitude from 0 Vp-p. When #37 (H-OUT) phase locks with that of signal B, measure signal B amplitude VthHD. 31.75 µs Signal B VthDH 2.35 µs HA06 Horizontal picture phase adjustment variable range 1. Set subaddress (00) data to 40H. 2. Input signal B (the figure is shown below) to TP50. 3. Change subaddress (01) data from 80H to 00H, and measure phase change amount ∆HSFT− of #39 (H-OUT) waveform. 4. Change slave address (01) data from 80H to FEH, and measure phase change amount ∆HSFT+ of #39 (H-OUT) waveform. 31.75 µs Signal B 1.5 V 2.35 µs #39 waveform Data: 00H ∆HSFT− #39 waveform Data: 80H ∆HSFT+ #39 waveform Data: FEH 98 2003-01-21 TA1360AFG Note Characteristics HA07 Curve correction amount Test Conditions 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50. 3. Connect external voltage to #40 (curve correction), and measure phase change amount (∆H#40) of #37 (H-OUT) output waveform at 1.5 V and 3.5 V. 31.75 µs Signal B 1.5 V 2.35 µs #37 waveform (#40 voltage; 1.5 V) ∆H#40 #37 waveform (#40 voltage; 3.5 V) HA08 Clamp pulse phase, width and level 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50. 3. Measure #47 (SCP output) clamp pulse phase (CPS0), width (CPPW0), and output level (CPV0) in relation to signal B. 4. Set subaddress (01) data to 81H, and repeat the step 3 above to measure (CPS1), (CPW1), and (CPV1). 5. Apply no signal input to TP50. 6. Measure #47 clamp pulse phase (CPS2), width (CPW2), and output level (CPV2) in relation to #39. 31.75 µs Signal B 1.5 V 2.35 µs CPS0/1 #47 waveform CPV0/1 CPW0/1 #39 waveform CPS2 #47 waveform CPV2 CPW2 99 2003-01-21 TA1360AFG Note Characteristics HA09 Black peak detection pulse phase and level Test Conditions 1. Set subaddress (00) data to 40H. 2. Set SW70 to C, SW68 to C, and SW39A to OPEN 3. Input signal C (as the figure shown below) to #39 (FBP input). 4. Measure #70 (BPH filter) black peak detection pulse phase (HBPS00a and HBPS00b) in relation to signal C. 5. Set HBP-PHS 1/2 to (01), (10), and (11). Measure black peak detection pulse phase. 31.5 µs 4.13 µs 2V Signal C 0V HBPS**a HBPS**b #70 waveform HA10 FBP input threshold 1. Set subaddress (00) data to 40H. 2. Input signal B (as shown in the figure below) to TP50. 3. Increase amplitude of FBP signal to be input to #39 (FBP input) from 0 Vp-p. When #37 (H-OUT) phase locks with that of signal B, measure #39 input amplitude VthFBP. 31.75 µs 1.5 V 2.35 µs 100 2003-01-21 TA1360AFG Note Characteristics HB01 H-OUT pulse duty Test Conditions 1. No signal input. 2. Measure T1 and T2 (as shown in the figure below) from #37 (H-OUT) output waveform when subaddress (00) data is 80H and A0H. Calculate duties (THA and THB) using the following equation: TH = T1/(T1 + T2) × 100 % T1 T2 #37 waveform HB02 Horizontal free-run frequency HB03 Horizontal oscillation frequency variable range HB04 Horizontal oscillation control sensitivity HB05 H-OUT output voltage 1. Set SW44 to open. 2. Set subaddress (00) data to 01H and measure horizontal free-run frequency (F15K) according to #37 (H-OUT) output waveform. 3. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Measure horizontal free-run frequency F28K, F31K, F33K, F37K, and F45K as in the step 2 above. 1. Set subaddress (00) data to 01H. 2. Connect 10-kΩ resistor between #44 and VCC. Measure horizontal frequency (F15KMIN) according to #37 (H-OUT) output waveform. 3. Connect 68-kΩ resistor between #44 and GND. Measure horizontal frequency (F15KMAX) according to #37 (H-OUT) output waveform. 4. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the steps 2 and 3 above and measure horizontal frequencies F28KMIN, F28KMAX, F31KMIN, F31KMAX, F33KMIN, F33KMAX, F37KMIN, F37KMAX, F45KMIN, and F45KMAX. 1. Set SW44 to open. 2. Connect external power supply to TP44, and set subaddress (00) data to 01H. 3. Apply V44 + 0.05 V, and V44 − 0.05 V to TP44. Measure frequencies FA and FB according to #37 (H-OUT) output waveform. Calculate frequency change rate (BH15K) using the following equation. BH15K = (FB − FA)/0.1 4. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the step 2 above, and measure frequency change rate BH28K, BH31K, BH33K, BH37K, and BH45K 1. Set SW37 to open. 2. Measure voltage at High (V37H) and Low (V37L) of #37 (H-OUT) output waveform. 101 2003-01-21 TA1360AFG Note V01 Characteristics VP output pulse width, Vertical free-run (maximum pull-in range) Test Conditions 1. Input signal D (shown in the figure below) to TP50, and signal E (shown in the figure below) to #39 (FBP input). 2. Measure VP output pulse width (VPw) according to TP35 output waveform. 3. Measure VP pull-in range (VPt0) according to TP35 output waveform. 4. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure pull-in range VPt1, VPt2, VPt3, VPt4, VPt5, and VPt6 as in the step 3 above. 2.35 µs 29.63 µs Signal D (TP50 input signal) 4V 5.6 µs 9V Signal E (#39 input waveform) GND #39 input waveform TP35 waveform VPw VPt V02 Vertical minimum pull-in range 1. Repeat the step 1 of Note #V01. 2. Input signal F (shown in the figure below) to TP52. 3. Increase signal-F cycle from 30 H. Measure the cycle (TVPULL) when phase locks with that of TP35. Signal F (TP 52 waveform input) 3H TVPULL #39 input waveform TP 35 waveform 102 2003-01-21 TA1360AFG Note V03 Characteristics Vertical black peak detection pulse Test Conditions 1. Repeat the step 1 of Note #V01. Set SW70 to C, and SW68 to C. 2. Input signal F (shown in the figure below) to TP52. 3. Measure phase differences VBPP0E and VBPP0S according to #47 output waveform. 4. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure phase differences VBPP1E, VBPP1S, VBPP2E, VBPP2S, VBPP3E, VBPP3S, VBPP4E, VBPP4S, VBPP5E, VBPP5S, VBPP6E, and VBPP6S as in the step 3 above. Signal F (TP 52 waveform input) 3H 262.5H to 1125H #39 input waveform VBPPS VBPPE #70 waveform V04 Vertical blanking stop 1. phase 2. 3. Repeat the step 1 of Note #V01. Input signal F (shown in the figure below) to TP52. Set subaddress (03) data to 00H and F0H. Measure blanking stop phase VBLKMIN and VBLKMAX according to #12 output waveform. Signal F (TP 52 waveform input) 3H 1125H #39 input waveform VBLK #12 input waveform 103 2003-01-21 TA1360AFG (1) Video signal 63.5 µs Sine wave of frequency f0 (2) Input signal 1 (3) Input signal 2 Amplitude A Sine wave of frequency f0 (4) Input signal 3 Figure T-1 Signals for Text/Color Difference Signal 2 104 2003-01-21 TA1360AFG 63.5 µs 20 µs 20 µs 20 µs 20 ns 20 ns (1) Input signal 4 50% tPF tPR (2) 0% 10% 50% 90% 100% τF τR tPR (3) tPF 0% 10% 50% 90% 100% τR Figure T-2 τF Test Pulses for Text/Color Difference Signal 2 105 2003-01-21 TA1360AFG Test Circuit VCC (9 V) TP35 #35 I2L VDD 31 74 APL FILTER #31 SCL 30 #75 TP78 14 3 15 2 16 1 9 8 50 kΩ 1000 pF 5.1 kΩ 31.5/33.75 kHz 10 µF 51 kΩ TP30 470 Ω TP28 #28 I L GND 27 7 11 6 #24 0.1 µF 10 kΩ 0.1 µF #23 A B SW21 TP21 A 0.1 µF #21 24 TP25 4 14 3 15 2 16 1 51 kΩ 10 µF 51 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ #19 23 13 5 10 kΩ #2 #18 TP19 #16 22 12 TP26 A 21 ANALOG R IN 20 B SW24 ANALOG OSD B IN 19 SW26 A 0.1 µF B SW25 #26 A ANALOG G IN 25 0.1 µF B #25 ANALOG B IN 26 TP24 NC 18 NC ANALOG OSD G IN 17 DAC2 (ACP PULSE) ANALOG OSD R IN 16 0.1 µF A B SW19 100 Ω 300 pF 6.8 V #1 15 B SW18 #8 #7 0.01 µF #6 0.01 µF #4 12 13 14 #12 #13 #14 TP18 11 NC 10 0.01 µF 9 RGB VCC NC 8 NC RGB GND 7 100 µF NC 6 B OUT IK IN 5 G OUT B S/H 4 100 Ω G S/H 3 100 Ω NC 2 R OUT R S/H 1 0.01 µF 80 Ys1 (ANALOG OSD) NC #80 YS3 (ANALOG RGB) 79 YM/P-MUTE/BLK YS2 (ANALOG OSD) #78 10 2 78 ABCL IN 100 kΩ #79 15.75 kHz NC 29 SDA 28 77 VSM OUT 50 kΩ SW77 0.01 µF #77 4 51 kΩ 2.0 V 0.1 µF 470 Ω 5 #30 76 NC 1 kΩ 6 1000 pF TP77 7 11 13 NC 32 75 Y/C VCC 100 µF 8 5.1 kΩ SW74 0.01 µF #74 9 10 30 kΩ NC 33 73 NC 10 µF 1 #34 TA1360AFG 72 NC 2 16 TC4538BP 20 kΩ DAC1 (SYNC OUT) 34 B SW71 #71 15 12 50 kΩ 7.5 kΩ 1200 pF TP71 A 1 kΩ VP OUT 35 3 50 kΩ 70 BPH FILTER 71 DARK AREA DET FILTER 30 pF SW37 NC 36 0.47 µF #70 A 1 µF 14 10 µF 51 kΩ B 3.9 kΩ #37 69 NC 1 µF 100 kΩ B A SW70 C H-OUT 37 50 kΩ 7.5 kΩ 1200 pF 2 kΩ 4 51 kΩ 1000 pF H-FREQ SW2 100 Ω A TP40b 1 µF B C SW40 #40 10 kΩ B FBP IN 39 10 kΩ SW39a A #39 SW39B DEF/DAC GND 38 5.1 kΩ H CURVE 40 CORRECTION 5 5.1 kΩ 41 NC #41 42 HVCO #42 43 50 kΩ 7.5 kΩ 1200 pF 13 67 Cb1/Pb1 IN B SW67 0.1 µF #67 A B 68 Y1 IN SW68 0.1 µF C 20 kΩ 6 TC4538BP 15 kΩ 15 kΩ 15 kΩ CSBLA503KECZF30 470 Ω 3 kΩ 1 µF 0.01 µF 1 k Ω TP44 100 µF SW44 #44 44 AFC FILTER 0.01 µF 45 DEF/DAC VCC CP OUT 46 NC 100 Ω #47 47 NC 48 SCP IN HD IN NC SYNC IN TP47 470 Ω TP49 TP50 100 Ω 100 Ω TP52 A 30 kΩ TP53 TP55 #55 #54 #53 #52 #51 #50 #49 55 54 53 52 51 50 49 NC NC 56 H-FREQ SW1 #57 57 7 11 TC4538BP 66 Cr1/Pr1 IN 100 Ω 0.01 µF 2.2 µF 58 VSM FILTER Cr2/Pr2 IN #58 59 COLOR LIMITER Cb2/Pb2 IN SW61 B #60 60 NC Y2 IN #61 61 8 10 12 1/2W 220 Ω B SW66 #66 TP67 A 0.1 µF 62 NC TP66 A 0.1 µF LIGHT AREA DET FILTER 65 Y/C GND #63 63 0.1 µF A TP61 SW60 B 0.1 µF A TP60 SW64 TP64 A B 0.47 µF 0.1 µF A B SW63 0.1 µF TPB #64 64 VD IN TPD 5.1 kΩ 3.9 kΩ 2 kΩ 5.1 kΩ 3.9 kΩ 75 Ω TPA 10 µF A 2 kΩ 75 Ω TPC 10 µF B 0.1 µF SW53b 100 Ω TP53b 9 SW INPUT B 45 kHz VCC (9 V) 106 2003-01-21 TA1360AFG 75 Ω M 0.1 µF ○ 46 45 44 43 HD IN SCP IN NC CP OUT NC DEF/DAC VCC AFC FILTER NC NC COLOR LIMITER VSM FILTER M 0.01 µF ○ 0.01 µF 0.1 µF 560 Ω 47 NC Cr2/Pr2 IN 0.1 µF 48 42 41 HVCO 49 B VCC 470 Ω H-FREQ SW2 50 CSBLA503KECZF30 51 VD IN 57 100 µF 3 kΩ 1 µF SCP-IN 52 SYNC IN 58 CP-OUT HD-IN 53 NC 59 VD-IN 54 NC 60 A 1.5 kΩ 1 kΩ 5.1 kΩ 3.9 kΩ 75 Ω 55 H-FREQ SW1 2.2 µF 56 0.01 µF 0.1 µF 61 66 Cr1/Pr1 IN 1 kΩ 5.1 kΩ 3.9 kΩ 1 kΩ 62 Cb2/Pb2 IN M 0.1 µF ○ 75 Ω 63 NC M 0.1 µF ○ 64 Y2 IN M ○ 5.1 kΩ 3.9 kΩ SYNC IN VCC 47µ H H CURVE 40 CORRECTION FBP IN 39 67 Cb1/Pb1 IN CURVE CORR 10 kΩ FBP-IN DEF/DAC GND 38 68 Y1 IN H-OUT 37 H-OUT 69 NC 1 kΩ 75 Ω 5.1 kΩ 3.9 kΩ Y1 IN 10 µF 1 kΩ M 0.1 µF ○ 10 µF 1 kΩ 75 Ω 0.47 µF M 0.1 µF ○ 1 kΩ 10 µF 5.1 kΩ 3.9 kΩ 65 Y/C GND Cb1 /Pb1 IN Cr2/Pr2 IN 10 µF LIGHT AREA DET FILTER 75 Ω 1 kΩ 10 µF Cr1/Pr1 IN 5.1 kΩ 3.9 kΩ 75 Ω Y2-IN Cb2/Pb2 IN 10 µF 1 kΩ 10 µF 5.1 kΩ 3.9 kΩ Application Circuit 1 µF 0.47 µF NC 36 70 BPH FILTER VP OUT 35 71 DARK AREA DET FILTER DAC1 (SYNC OUT) 34 DAC1-OUT TA1360AFG 72 NC NC 33 73 NC NC 32 2.2 µF I2L VDD 31 74 APL FILTER 47 µH VP-OUT 30 kΩ 0.01 µF 2.0 V 0.01 µF 75 Y/C VCC SCL 30 100 µF 76 NC 470 Ω SCL NC 29 VSM OUT 100 kΩ 77 VSM OUT SDA 28 470 Ω SDA 0.01 µF ABCL 2 78 ABCL IN I L GND 27 NC ANALOG OSD B IN NC DAC2 (ACP PULSE) ANALOG R IN 15 16 17 18 19 20 21 22 23 24 OSD B-IN OSD R-IN ANALOG B IN 26 0.1 µF ANALOG B IN ANALOG G IN ANALOG R-IN 30 kΩ 0.1 µF ANALOG G IN 25 0.1 µF M : Mylar capacitor ○ DAC2-OUT 100 µF 100 Ω 100 Ω B OUT 100 Ω G OUT R OUT IK-IN 30 kΩ 6.8 V 300 pF 107 0.1 µF ANALOG OSD G IN 14 0.1 µF ANALOG OSD R IN 13 0.1 µF 12 OSD G-IN 11 NC 10 0.01 µF NC 9 47 µH RGB GND 8 RGB VCC NC 7 NC IK IN 6 B OUT B S/H 5 R OUT G S/H 4 G OUT NC 3 2.2 µF R S/H 2 2.2 µF NC 1 2.2 µF YS3 (ANALOG RGB) 80 Ys1 (ANALOG OSD) Ys3 Ys1 Ys2 79 YM/P-MUTE/BLK YS2 (ANALOG OSD) 100 kΩ YM Application of H-FREQ switching (31.5 k/33.75 k/45 kHz) Tr. Pin 55 voltage Pin 41 voltage A B 31.5 kHz L L 9V 6V 33.75 kHz L H 9V 3V 45 kHz H * 9V 0V H-FREQ *: Don’t care 2003-01-21 TA1360AFG ACB Application Circuit +B CRT R G CRT CRT B 1 Vp-p R G B 0~3.0 V (DC) 108 20~51 kΩ 8 51~330 pF CLAMP 6.8 V Z IK IN 2003-01-21 TA1360AFG Package Dimensions Weight: 1.6 g (typ.) 109 2003-01-21 TA1360AFG RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 110 2003-01-21