TOSHIBA TMP95C061

TOSHIBA
TLCS-900 Series
CMOS 16-bit Microcontrollers
TMP95C061F
1.
Outline and Device Characteristics
TMP95C061F is a high-speed advanced 16-bit microcontroller developed for controlling medium to large-scale equipment.
The TMP95C061F is housed in an 100-pin flat package.
Device characteristics are as follows:
(1) Original 16-bit CPU
• TLCS-90/900 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed DMA
- 4 channels (640ns/2 bytes at 25MHz)
(2) Minimum instruction execution time
- 160ns at 25MHz
(3) Internal RAM: None
Internal ROM: None
TMP95C061
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data)
• AM8/16 pin (select external data bus width)
• Can mix 8- and 16-bit external data bus width.
…Dynamic data bus sizing
(5) DRAM Controller
(6) 8-bit timer: 2 channels
(7) 16-bit timer: 2 channels
(8) Pattern generators: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 4 blocks
(13) Interrupt functions
• 2 CPU interrupts… …SWI instruction and Illegal instruction
• 18 internal interrupts
7-level priority can be set.
• 6 external interrupts
(14) I/O ports: 56 pins
(15) Standby function : 3 HALT modes (RUN, IDLE, STOP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP95C061
Figure 1. TMP95C061 Block Diagram
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TMP95C061
2.
Pin Assignment and Functions
The assignment of input/output pins for TMP95C061, their
name and outline functions are described below.
2.1 Pin Assignment
Figure 2.1 shows pin assignment of TMP95C061.
Figure 2.1. Pin Assignment (100-pin QFP)
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2.2 Pin Names and Functions
The names of input/output pins and their functions are
described below.
Table 2.2. Pin Names and Functions
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TMP95C061
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TMP95C061
3.
Operation
This section describes in blocks the functions and basic operations of TMP95C061 device.
Check the [7. Care Points and Restriction] because of the
Care Points, etc., are described.
3.1 CPU
TMP95C061 device has a built-in high-performance 16-bit
CPU (900/H CPU). (For CPU operation, see TLCS-900 CPU in
the previous section.)
This section describes CPU functions unique to
TMP95C061 that are not described in the previous section.
3.1.1 Reset
To reset the TMP95C061, the RESET input must be kept at 0
for at least 10 system clocks (10 states: 800ns with a 25MHz
system clock) within an operating voltage range and with a
stable oscillation.
When reset is accepted, the CPU sets as follows:
• Program Counter (PC) to 8000H.
PC (7 : 0)
← stored data to 0FFFF00H
PC (15 : 8)
← stored data to 0FFFF01H
PC (23 : 16) ← stored data to 0FFFF02H
• Stack pointer (XSP) for system mode to 100H.
• IFF2 to 0 bits of status register to 111. (Sets mask register to
interrupt level 7.)
• MAX bit of status register to 1. (Sets to minimum mode.)
• Bits RFP2 to 0 of status register to 000. (Sets register banks
to 0.)
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When reset is released, instruction execution starts from
PC reset vector. CPU internal registers other than the above
are not changed.
When reset is accepted, processing for built-in I/Os,
ports, and other pins is as follows:
• Initializes built-in I/O registers as per specifications.
• Sets port pins (including pins also used as built-in I/Os) to
general-purpose input/output port mode.
• Sets the WDTOUT pin to 0. (Watchdog timer is set to enable
after reset.)
• Pulls up the CLK pin to 1.
3.1.2 External Data Width Selection Pin (AM18/16)
After reset operation, TMP95C061, the operates 8 bits or 16
bits external data width according to input to AM8/16 pin.
• Fixed 16 bit bus or 16 bit bus interlarded with 8 bit
bus
“0” should be input. Port 1 (P10 to P17) operate as
data bus D8 to 15. The data bus width for external
access is set by Chip Select/Wait Control resistor.
• Fixed 8 bit bus
“1” should be input. Port 1 (P10 to P17) operate as 8
bit data I/O ports. The value set in Chip Select/Wait
Control resistor <B0BUS>, <B1BUS>, <B2BUS>,
<B3BUS> and <BEXBUS> are neglected.
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3.2 Memory Map
Figure 3.2 shows a memory map of the TMP95C061.
Figure 3.2. Memory Map
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TMP95C061
3.3 Interrupts
TLCS-900 interrupts are controlled by the CPU interrupt mask
flip-flop (IFF2 to 0) and the built-in interrupt controller.
TMP95C061F has the following 26 interrupt sources:
• Interrupts from the CPU…2
(Software interrupts, privileged violations, and Illegal (undefined) instruction execution)
• Interrupts from external pins (NMI, INT0, and INT4 to 7)…6
• Interrupts from built-in I/Os…14
• Interrupts from high-speed DMA (HDMA)…4
A fixed individual interrupt vector number is assigned to
each interrupt source; six levels of priority (variable) can also be
assigned to each maskable interrupt. Non-maskable interrupts
have a fixed priority of 7.
When an interrupt is generated, the interrupt controller
sends the value of the priority of the interrupt source to the
CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest
priority (7 for non-maskable interrupts is the highest) to the
CPU.
The CPU compares the value of the priority sent with the
value in the CPU interrupt mask register (IFF2 to 0). If the value
is greater than that of the CPU interrupt mask register, the
interrupt is accepted. The value in the CPU interrupt mask register (IFF2 to 0) can be changed using the EI instruction (contents of the EI num/IFF<2:0> = num). For example,
programming EI 3 enables acceptance of maskable interrupts
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with a priority of 3 or greater, and non-maskable interrupts
which are set in the interrupt controller. The DI instruction
(IFF<2:0> = 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable interrupts are 0 to 6,
the DI instruction is used to disable maskable interrupts to be
accepted. The EI instruction becomes effective immediately
after execution. (With the TLCS-90, the EI instruction becomes
effective after execution of the subsequent instruction.)
In addition to the general-purpose interrupt processing
mode described above, there is also a high-speed DMA
(HDMA) processing mode. HDMA is a mode used by the CPU
to automatically transfer byte, word and 4-byte data. It enables
the CPU to process interrupts such as data saves to built-in I/Os
at high speed.
Figure 3.3 (1) is a flowchart showing overall interrupt
processing.
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TMP95C061
Figure 3.3 (1). Interrupt Processing Flowchart
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TMP95C061
3.3.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows:
(1)
The CPU reads the interrupt vector from the interrupt
controller. When more than one interrupt with the
same level is generated simultaneously, the interrupt
controller generates interrupt vectors in accordance
with the default priority (which is fixed as follows: the
smaller the vector value, the higher the priority), then
clears the interrupt request.
(2)
The CPU pushes the program counter and the status
register to the system stack area (area indicated by the
system mode stack pointer(XSP)).
(3)
The CPU sets a value in the CPU interrupt mask register <IFF2 to 0> that is higher by 1 than the value of the
accepted interrupt level. However, if the value is 7, 7 is
set without an increment.
(4)
The CPU increments the INTNEST (Interrupt Nesting
Counter).
(5)
The CPU jumps to address FFFF00H + interrupt vector, then starts the interrupt processing routine.
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Bus Width of
Stack Area
8 bit
16 bit
Bus Width
Interrupt
Vector Area
Interrupt Processing State Number
MAX mode
Min mode
8 bit
23
24
16 bit
24
20
8 bit
22
20
16 bit
18
16
To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing
this instruction restores the contents of the program counter
and the status registers and decements the INTNEST (Interrupt Nesting Counter).
Though acceptance of non-maskable interrupts cannot
be disabled by program, acceptance of maskable interrupts
can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority
higher than the value in the CPU mask register <IFF2 to 0>.
The CPU mask register <IFF2 to 0> is set to a value higher by
1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is
generated, the CPU accepts the interrupt with the higher level,
causing interrupt processing to nest.
If an interrupt generated while the CPU is performing processes (1) to (5) for an earlier interrupt, the new interrupt is
sampled immediately after the start instruction of the interrupt
processing is executed. Setting DI as the start instruction disables maskable interrupt nesting. (Note: With the 900 and
900/L, an interrupt is sampled before the start instruction is
executed.)
Resetting initializes the CPU mask registers <IFF2 to 0>
to 7; therefore, maskable interrupts are disabled.
The addresses 0FFFF00H to 0FFFFFFH (256 bytes) of
the TMP95C061 are assigned for interrupt processing entry
area.
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Table 3.3 (1) TMP95C061 Interrupt Table
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Setting to Reset/Interrupt Vector
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TMP95C061
3.3.2 High-Speed DMA (HDMA)
In addition to the conventional interrupt processing,
TMP95C061 also has a high-speed DMA (HDMA) function.
Each interrupt request starts HDMA operation in level “6” irrelevant to the set interrupt level. Level “6” is the interrupt level
which has the highest priority among maskable interrupts.
(1)
HDMA Operation
When the interrupt is generated in the interrupt request
source set by HDMA start vector resistors, the interrupt controller sends the HDMA request to the CPU in
level “6” irrelevant to the set interrupt level.
The HDMA has four channels so that it can be set up
for up to four types of interrupt source.
When an HDMA interrupt is accepted, data is automatically transferred from the transfer source address
to the transfer destination address set in the control
register, and the transfer counter is decremented. If the
value in the counter after decrementing is not 0,
HDMA processing is completed; if the value in the
counter after decrementing is 0, the CPU notifies the
interrupt controller of the HDMA transfer end interrupt
(INTTCn), zero-clears the HDMA start vector register,
disables re-start of the HDMA, and ends the HDMA
processing.
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The priority of the HDMA transfer end interrupt generated at this time is determined by its interrupt level and
default priority, same as with other maskable interrupts.
The priorities of HDMA requests generated simultaneously in multiple channels are irrelevant to their input
levels. The HDMA request which is generated in the
channel with the small number has a higher priority.
(CH0: highest priority; CH3: lowest priority).
The 32-bit control registers are used for setting transfer
source/destination addresses. However, the TLCS900 has only 24 address pins for output. A 16M-byte
space is available for the high-speed HDMA. There are
two data transfer modes: one-byte mode and oneword mode. Incrementing, decrementing, and fixing
the transfer source/destination address after transfer
can be done in both modes. Therefore data can easily
be transferred between I/O and memory and between
I/Os. For details of transfer modes, see the description
of transfer mode registers.
The transfer counter has 16 bits, so up to 65536 transfers (the maximum when the initial value of the transfer
counter is 0000H) can be performed for one interrupt
source by high-speed DMA processing.
Interrupt sources processed by HDMA processing are
those with the high-speed HDMA start vectors listed in
Table 3.3 (1).
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TMP95C061
(2)
Register Configuration (CPU Control Register)
These Control Registers cannot be set only “LCD cr, r” instruction.
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(3)
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Transfer Mode Register Details
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TMP95C061
3.3.3. Interrupt Controller
Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 24 channels) in the interrupt controller has an interrupt request flip-flop, interrupt priority setting register, and a register for storing the high-speed
micro DMA start vector. The interrupt request flip-flop is used
to latch interrupt requests from peripheral devices. The flip-flop
is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the
CPU executes an instruction that clears the interrupt of that
channel (writes 0 in the clear bit of the interrupt priority setting
register).
For example, to clear the INT0 interrupt request, set the
register after the DI instruction as follows.
INTE0AD←---- 0 ---
Zero-clears the INT0 Flip-Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-
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ables the corresponding interrupt request. The priority of the
non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR <IFF2 to 0>. Interrupt requests where the priority value equals or is higher than
the set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR <IFF2 to 0>.
The interrupt controller also has four registers used to
store the HDMA start vector. These are I/O registers; unlike
other HDMA registers (DMAS, DMAD, DMAM, and DMAC),
they can be accessed in either normal or system mode. Writing
the start vector of the interrupt source for the HDMA processing
(see Table 3.3 (1)), enables the corresponding interrupt to be
processed by micro HDMA processing. The values must be set
in the HDMA parameter registers (e.g., DMAS and DMAD) prior
to the micro HDMA processing.
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Figure 3.3.3 (1). Block Diagram of Interrupt Controller
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(1)
Interrupt Priority Setting Register
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(2)
External Interrupt Control
Setting of External Interrupt Pin Functions
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(3)
HDMA Start Vector
Register used to assign HDMA processing to an interrupt source. The interrupt source whose HDMA start
vector matches the vector value set in this register is
assigned as the HDMA start source.
When the HMDA transfer counter value reaches 0, the
controller is notified of the HDMA transfer end interrupt
corresponding to the channel, the HDMA start vector is
cleared, and the HDMA start source of the channel is
also cleared. To continue the HDMA processing, the
HDMA start vector register must be set again within
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the HDMA transfer end interrupt processing.
If the same vector is set in the HDMA start vector registers of the multiple channels, the interrupt generated in
the channel with the smaller number has a higher priority.
Thus, if the same vector is set in the HDMA start vector
registers of two channels, the interrupt generated in
the channel with the smaller number is processed until
the HDMA transfer end. If a HDMA start vector is not
set, then the HDMA processing is started for the channel with the larger number is processed.
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(4)
Notes
The instruction execution unit and the bus interface
unit of this CPU operate independently of each other.
Therefore, if the instruction used to clear an interrupt
request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might
execute the fetched instruction to clear the interrupt
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request flag while reading the interrupt vector after
accepting the interrupt. If so, the CPU would read the
default vector “0028H” and start the interrupt processing from the address “FFFF28H”.
To avoid this, make sure that the instruction used to
clear the interrupt request flag comes after the DI
instruction.
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TMP95C061
3.4 Standby Controller
When the “HALT” instruction is executed, the operating mode
changes RUN, IDLE, or STOP mode depending on the contents of the HALT mode setting register WDMOD <HALTM 1 :
0>.
(1)
RUN : Only the CPU halts; power consumption
remains unchanged.
(2)
IDLE : Only the built-in oscillator operates, while all
other built-in circuits stop. The power consumption is reduced to 1/10 or less than that
during NORMAL operation.
When the halt state is released by a reset, the status in
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(3)
STOP : All internal circuits including the built-in oscillator stop. This greatly reduces power consumption.
The HALT release depends on these three modes. For
details, see “Table 3.4 (2)”. (Note: The HALT state cannot be
released by HDMA start.)
(Example releasing “RUN” mode)
INT0 interrupt releases HALT state when the RUN mode
is on.
effect before entering the halt status is hold.
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TMP95C061
(1)
RUN Mode
Figure 3.4.1 shows the timing fro releasing the HALT
state by interrupts in the RUN mode.
In the RUN mode, the system clock in the MCU continues to operate even after a HALT instruction is exe-
cuted. Only the CPU stops executing the instruction.
Until the HALT state is released, the CPU repeats
dummy cycles. In the HALT state, an interrupt request
is sampled with the rising edge of the “CLK” signal.
The external interrupts (INT4, 5, 6, 7) releases only
RUN mode.
Figure 3.4.1. Timing Chart for Releasing the HALT State by Interrupt in RUN Modes
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TMP95C061
(2)
IDLE Mode
Figure 3.4.2 illustrates the timing for releasing the HALT
state by interrupts in the IDLE mode.
In the IDLE mode, only their internal oscillator operates. The system clock in the MCU stops, and the
CLK pin is fixed at the “1” level.
In the HALT state, an interrupt request is sampled
asynchronously with the system clock, however, the
HALT release (restart of operation) is performed synchronously with it.
The interrupts except NMI and INT0 is disable during
this mode.
Figure 3.4.2. Timing Chart for Releasing the HALT State by Interrupts in RUN Mode
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TMP95C061
(3)
STOP Mode
Figure 3.4.3 is a timing chart fro releasing the HALT
state by interrupts in the STOP mode.
The STOP mode is selected to stop all internal circuits
including the internal oscillator. In this mode, all pins
except special ones are put in the high-impedance
state, independent of the internal operation of the
MCU. Note, however, that the pre-halt state (the status
prior to execution of HALT instruction) of all output pins
can be retained by setting the internal I/O register
WDMOD <DRVE> to “1”. The content of this register is
initialized to “0” by resetting.
When the CPU accepts an interrupt request, the internal oscillator is restarted immediately. However, to get
the stabilized oscillation, the system clock starts its
output after the time set by the warming up counter
WDMOD <WARM>. A warming up time of either the
clock oscillation time x 214 or 216 can be set by setting
this bit to either “0” or “1”. This bit is initialized to “0” by
resetting.
Figure 3.4.3. Timing Chart for Released by Interrupt in STOP Mode
Only either the NMI, INT0, or RESET can release the
STOP mode.
When the STOP is released by the except RESET, the
system clock is started outputting after warming up
time to get the stabilized oscillation.
When the STOP mode is released by RESET, it is necessary to keep the RESET signal at “0” long enough to
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release to get the stabilized oscillation because the
warming up counter is ignored.
The warming up counter operates when the STOP
mode is released even the system which is used as an
external oscillator. As a result, it takes warming up time
from inputting the releasing request to outputting the
system clock.
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Table 3.4 (1) Pin States in STOP Mode
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Table 3.4 (2) I/O Operation and Cancel During Halt Mode
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3.5 Functions of Ports
The TMP95C061 has a total of 56 bits when the AM8/16 pin is
set to 1; a total of 48 bits when the AM8/16 pin is set to 0.
These ports are also used for internal CPU and I/O. Table
3.5 lists port pin functions.
(R:
↑ = With programmable pull-up resistor
↓ = WIth programmable pull-down)
Table 3.5 Functions of Ports
Port Name
Pin Name
Number of
Pins
Direction
R
Direction Setting Unit
Port1
P10 to P17
8
I/O
–
Bit
Port2
P20 to P27
8
Output
–
(Fixed)
Port5
P50
P53
P54
P55
1
1
1
1
I/O
I/O
I/O
I/O
↑
↑
↑
↑
Bit
Bit
Bit
Bit
Port6
P60
P61
P62
P63
P64
P65
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
–
–
–
–
–
–
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
Port7
P70 to P77
8
I/O
↑
Bit
PG00 to PG03,
PG10 to PG13
Port8
P80
P81
P82
P83
P84
P85
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
↑
↑
↑
↑
↑
↑
Bit
Bit
Bit
Bit
Bit
Bit
TXD0
RXD0
CTS0/SCLK0
TCD1
RXD1
SCLK1
Port9
P90 to P93
4
Input
–
(Fixed)
AN0 to AN3
PortA
PA0
PA1
PA2
PA3
1
1
1
1
I/O
I/O
I/O
I/O
↑
↑
↑
↑
Bit
Bit
Bit
Bit
WAIT
TI0
TO1
TO3
PortB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
↑
↑
↑
↑
↑
↑
↑
↑
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
TI4/INT4
TI5/INT5
TO4
TO5
TI6/INT6
TI7/INT7
TO6
INT0
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Pin Name for Built-in Function
D8 to D15
A16 to A23
HWR
BUSRQ
BUSAK
R/W
CS0
CS1
CS2
CS3/CAS
RAS
REFOUT
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TMP95C061
3.5.1 Port 1 (P10 - P17)
Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis using control register P1CR. Resetting resets all bits
of output latch P1 and control register P1CR to 0 and sets Port
1 to input mode.
In addition to functioning as a general purpose I/O port,
Port 1 also functions as an address data bus (D8 to 15).
Port 1 always functions as a data bus (D8 to 15) (AM8/16
= “0”).
Figure 3.5 (1). Port 1
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Figure 3.5 (2). Registers for Port 1
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3.5.2 Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. I/O can be set on
bit basis using the control register P2FC. Resetting resets all
bits of output latch P2 and function register P2FC. Resetting
also sets P2 to input mode.
With the TMP95C061, which has no internal ROM, all
bits of P2FC are set to “1” and operate A23 to A16 after reset
input.
Figure 3.5 (3). Port 2
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Figure 3.5 (4). Registers for Port 2
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3.5.3 Port 5 (P52 to P55)
Port 5 is a 4-bit general-purpose I/O port. I/O can be set on bit
basis using control register P5CR and the function register
P5FC. Resetting does the following:
Resets all the bits of the output latch, the control register
P5CR and the function register P5FC to “0” and sets each port
input mode with pull-up resistors.
Figure 3.5 (5). Port5 (P50, P51, P52, P54, P55)
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Figure 3.5 (6). Port5 (P53)
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Figure 3.5 (7). Registers for Port5
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3.5.4 Port6 (P60 to P65)
Port 6 is a 6-bit general-purpose output port. Resetting sets
each output latch P62 = “0”, P60, P61, P63 to P65 = “1”.
Functions can be selected using P6FC and provided chip
select and DRAM control functions (CS0 to 3, CAS, RAS and
REFOUT). After resetting, each port operates as output port.
Figure 3.5 (8). Port6
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Figure 3.5 (9). Register for Port 6
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TMP95C061
3.5.5 Port7 (P70 to P77)
Port 7 is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis. Resetting sets Port 7 as an input port and connects
a pull-up resistor. It also sets all bits of the output latch to 1. In
addition to functioning as a general-purpose I/O port, Port 7
also functions as a pattern-generator PG0/PG1 output. PG0 is
assigned to P70 to P73; PG1, to P74 to P77. Writing in the
corresponding bit of port 7 control register (P7CR) and function register (P7FC) enables PG output. Resetting resets the
function register P7FC value to 0, and sets all bits to ports.
Figure 3.5 (10). Port 7
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TMP95C061
Figure 3.5 (11). Register for Port 7
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TMP95C061
3.5.6 Port 8 (P80 - P85)
Port 8 is a 6-bit general-purpose I/O port, also used as an analog input pin. I/O can be set on a bit basis. Resetting sets Port
8 as an input port and connects a pull-up resistor. It also sets
all bits of the output latch register P8 to 1. In addition to functioning as a general-purpose I/O port, Port 8 also functions as
an I/O for serial channel 1, 0. Writing “1” in the corresponding
bit of Port 8 function register enables those functions. Resetting resets the function register value to “0”, and sets all bits to
ports.
(1)
Port 80, 83 (TXD0/TXD1)
P80 and P83 also function as serial channel TXD output pins in addition to I/O ports. They have programmable open drain function.
Figure 3.5 (12). Port 80, 83
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TMP95C061
(2)
Port 81, 84 (RXD0, 1)
input pins for serial channels.
P81 and P84 are I/O ports, and also used as RXD
Figure 3.5 (13). Port 81, 84
(3)
as a SCLK0 I/O pin for serial channels.
Port 82 (CTS0/SCLK0)
P92 is an I/O port, and also used as a CTS input pin or
Figure 3.5 (14). Port 82
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(4)
Port 85 (SCLK1)
SCLK1 I/O pin for serial channel 1.
P85 is a general-purpose I/O port. It is also used as a
Figure 3.5 (15). Port 85
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TMP95C061
Figure 3.5 (16). Register for Port 8
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3.5.7 Port 9 (P90 to P93)
Port 9 is a 4-bit input I/O port, also used as analog input pins
for the internal A/D Converter.
Figure 3.5 (17). Port 9
Figure 3.5 (18). Register for Port 9
3.5.8 Port A (PA0 to PA3)
Port A is a 4-bit general-purpose I/O port. I/O can be set on a
bit basis. Resetting sets Port 7 as an input port and connects
a pull-up resistor. In addition to functioning as a general-purpose I/O port, Port A0 also functions as wait input pin WAIT;
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Port A1 as an 8-bit timer input (TI0), Port A2 as a PWM0 output (TO1), and Port A3 as a PWM1 output (TO3) pin. Writing 1
in the corresponding bit of the Port A function register (PAFC)
enables output of the timer. Resetting resets the function register PAFC value to 0, and sets all bits to ports.
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TMP95C061
Figure 3.5 (19). Port A
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TMP95C061
Figure 3.5 (20). Register for Port A
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TMP95C061
3.5.9 Port B (PB0 to PB7)
Port B is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis. Resetting sets Port B as an input port and connects
a pull-up resistor. It also sets all bits of the output latch register
PB to 1. In addition to functioning as a general-purpose I/O
port, Port B also functions as an input for 16-bit timer 4 and 5
clocks, an output for 16-bit timer F/F 4, 5, and 6 output, and
an input for INT0. Writing “1” in the corresponding bit of the
Port B function register (PB FC) enables those functions.
Resetting resets the function register PBFC value to “0”, and
sets all bits to ports.
(1)
PB0 ~ PB6
Figure 3.5 (21). Port B (PB0 - PB6)
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TMP95C061
(2)
PB7 (INT0)
as an INT0 pin for external interrupt request input.
Port B7 is a general-purpose I/O port, and also used
Figure 3.5 (22). Port B7
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TMP95C061
Figure 3.5 (23). Register for Port B
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3.6 Chip Select/Wait Control, AM8/16 pin
TMP96C061 has a built-in chip select/wait controller used to
control chip select (CS0 to CS3 pins), wait (WAIT pin), and
data bus size (8 or 16 bits) for any of the three block address
areas.
Additionally, there is an AM8/16 pin which selects external data bus width for TMP95C061.
3.6.1 Control Register
Table 3.6 (1) shows control registers
Each block address area is controlled by 1-byte CS/
WAIT control registers. Start address register (MSAR0 to
MSAR3) and address mask register (MAM0 to 3).
Table 3.6 (1) Chip Select/Wait Control Register
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TMP95C061
(1)
Enable
(3)
Wait control
Bit 4 (B0E, B1E, B2E, and B3E) of control register
BXCS is a master bit used to specify enable (1)/disable
(0) of the setting.
Resetting sets B0E, B1E, and B3E to disable (0) and
B2E to enable (1).
(2)
Control register bits 1 and 0 (B0W1, 0; B1W1, 0; B2W1,
0; B3W1, 0; BEXW1, 0) are used to specify the number
of waits. Setting these bits to 00 inserts a 2-state wait
regardless of the WAIT pin status. Setting them to 01
inserts a 1-state wait regardless of the WAIT status.
Setting them to 10 inserts a 1-state wait and samples
the WAIT pin status. If the pin is low, inserting the wait
maintains the bus cycle until the pin goes high. Setting
them to 11 completes the bus cycle without a wait
regardless of the WAIT pin status.
Resetting sets these bits to 00 (2-state wait mode).
Data bus size select
Bit 2 (B0BUS, B1BUS, B2BUS, B3BUS, BEXBUS) of
the control register is used to specify data bus size.
Setting this bit to 0 accesses the memory in 16-bit
data bus mode; setting it to 1 accesses the memory in
8-bit data bus mode.
This bit is effective only in 16 bit bus mode (AM8/16 =
0). In 8-bit bus mode (AM8/16 = 1), this bit is negligible
and all external memory areas are accessed in fixed 8
bit bus (See 3.1.2 External Data width selection pin
(AM8/16)).
Changing data bus size depending on the access
address is called dynamic bus sizing. Table 3.6 (2)
shows the details of the bus operation.
Note:
In case of competition of accessing and refreshing to DRAM,
TMP95C061 automatically inserts refresh cycle in addition to settled wait cycle.
(4)
CS/CAS Waveform Select
Bit 3 of control register B3 is used to specify waveform
mode output from the chip select pin (CS3/CAS). Setting this bit to 0 specifies CS3 waveforms; setting it to
1 specifies CAS waveforms.
Resetting clears bit 5 to 0.
Table 3.6 (2) Dynamic Bus Sizing
Operand
Start Address
Memory
Data Size
CPU Address
2n + 0
(even number)
8 bits
8 bits
16 bits
8 bits
2n + 1
(odd number)
2n + 0
(even number)
16 bits
2n + 1
(odd number)
2n + 0
(even number)
D15 to D8
D7 to D0
2n + 0
xxxxx
b7 to b0
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
8 bits
2n + 0
2n + 1
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
2n + 2
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 1
2n + 2
b7 to b0
xxxxx
xxxxx
b15 to b8
2n + 0
2n + 1
2n + 2
2n + 3
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
2n + 0
2n + 2
b15 to b8
b31 to b24
b7 to b0
b23 to b16
2n + 1
2n + 2
2n + 3
2n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
2n + 1
2n + 2
2n + 4
b7 to b0
b23 to b16
xxxxx
xxxxx
b15 to b8
b31 to b24
8 bits
16 bits
32 bits
2n + 1
(odd number)
8 bits
16 bits
xxxxx:
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CPU Data
Operand
Data Size
During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.
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TMP95C061
(5)
Extra CS Area Bus/Wait Control
BEXCS register is used to specify the data bus size and
the number of wait in case of accessing address area
which is not specified using CS0 to 3 register.s This register has no master enable bit, so always enable to
unspecified area. Each bit has same meaning as BxCS.
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(6)
Setting B2CS <B2M> = 0 selects CS2 in the 16Mbyte area (000080H to FFFFFFHF). Setting B2CS
<B2M> = 1 selects CS2 according to the setting area
for start address register MSAR2 and address mark
register MAMR2, the same as for CS0 and SC1. A
reset zero-clears this bit.
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TMP95C061
3.6.2 Address Area Specification
The address space is specified with the start address register
(MSAR0 to 3). For each bus cycle, the chip select controller
compares the address on the bus and value of this start
address register. The value of the address mask register is
used to ignore result of this address comparison. When there
is a match, the specified space is assumed to be accessed
and a low strobe signal is output from the corresponding chip
select pin (CS0 to CS3) if it is enabled (B0E to B3E = “1”).
If the set address areas overlap or CS2 is enable for the
16M-byte area, the one with a smaller CS number is selected.
Figure 3.6 (1). Chip Select (CS0 to CS3) Operation Timing
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TMP95C061
Figure 3.6 (2). CS0 Address Decode Block Diagram
Figure 3.6 (3). CS1 Address Decode Block Diagram
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TMP95C061
Figure 3.6 (4). CS1 Address Decode Block Diagram
(1)
Memory start address register
Memory address mask register
Table 3.6 (3) Memory Start Address Register
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TMP95C061
Table 3.6 (4) Memory Address Mask Register
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CS1, CS2, and CS3 can be used in the same manner.
Resetting sets the registers MSAR0, MSA1, MSAR2,
MSAR3, MAMR0, MAMR1, MAMR2 and MAMR3 to
“0FFH”, and sets the control register bits B0E, B1E, to
“0”. So, chip select CS0, CS1, and CS3 are disable
after resetting, while Bit B2E = 1, B2M = 0 and CS2 is
enable for memory area 000080H to 0FFFFFFH (16M
byte).
MSAR0 3 < S23> to <S16> correspond to addresses
A23 to A16 and S15, S14 to 9, and S8 corresponding
to addresses A15, A14, to 9, and A8 are “0” by
default. MAMR0 <V20> to <V8> enable/disable comparison of value set with MSAR0 and address and
<V20> to <V8> correspond to <S20> to <S16>, S15,
S14 to 9, and S8. In addition, V21, V22, and V23 corresponding to <S21>, <S22>, and <S23> are “0” by
default and comparison is always enabled.
(2)
Example of enabling/disabling comparison
(CS0 registers MSAR0 and MSAMR0)
When comparison is disabled by setting <V16> = 1,
the comparison of the value of <S16> and address
A16 is disabled and the value of <S16> becomes
invalid.
When comparison is enabled by setting <V16> = 0,
the comparison of the value of <S16> and address
A16 is enabled and CS0 is enabled only when they
match.
How to the Start Address
The address decoder is output by specifying the start
address for CS output and the space size.
The start address is set every 64K-byte because it is
decoded by A16 to A23 as shown in the block diagram.
In other words, the DRAM start address is set to one
of the 64K-byte intervals after “000000H”.
However, note that the start address may be changed
due to the value of the MAMR.
Figure 3.6 (5). Where to Set Start Address
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(3)
How to Set the Address Space
The address space is specified by setting the memory
start address mask register (MAMR0 to 3).
As shown in the address decoder block diagram (Fig-
ures 3.6 (2) to (4)), CS0, CS1, or CS2/CS3 can specify
the address area for which the chip select signal can
be output depending on whether to compare the
address A8 to A20, A8 to A21, or A15 to A22, respectively.
Figure 3.6 (6). Chip Select and Space Size
(4)
Start Address/Address Space Setting Procedure
(Setting Example)
➀ Set memory start address register (MSARx)
(Set address)
When the setting the CS0 area to 64Kbyte (010000
to 01FFFFH), 16 bit data width and non-wait,
➁ Set memory start address mask register (MAMRx)
(Set area start area)
MSAR0 = 01H
MAMR0 = 07H
B0CS = 13H
start address 010000H
address area 64Kbyte
16 bit data width, 0-wait
➂ Set control register (BxCS)
data bus width, number of waits, enable/disable of
the area
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TMP95C061
3.7 Dynamic RAM (DRAM) Controller
TMP95C061 consists of a control circuit to refresh DRAM, an
access circuit to perform read/write.
1)
refresh mode
CAS before RAS refresh mode
2)
refresh interval
31-195 states (programmable)
3)
refresh cycle width
2-9 states (programmable)
60
4)
address mapping size
CS3 area: 64K-8M byte
5)
memory access address length
8-11 bits
6)
wait controller
depends on the setting CS/WAIT controller
7)
arbitration between refresh and memory access
refreshing is prior to memory access, automatically
inserted wait cycle during memory access cycle.
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TMP95C061
Control Register
Figure 3.7 (1). Refresh Control Register
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TMP95C061
Figure 3.7 (2). DRAM Memory Access Control Register
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TMP95C061
Operation Description
(1)
Memory Access Control
Access control is enable when DMEMCR <MAC> = 1.
And then DRAM control signals (RAS, CAS, and
REFOUT) are output during the time CPU access CS3
area. The cycle (bus width and number of wait) depend
on the value of CS/WAIT controller
To facilitate connection with low-speed DRAM, the
DRAM controller can accelerate RAS rise at wait inser-
tion and delay RAS precharge time (RAS high width).
This is called slow access mode. Set mode to slow
access using DMEMCR <MACM>.
In the access cycle, Address multiplexer outputs row/
column address through A0 to A11 pin. The enable/
disable setting of address multiplexing and multiplexed
address width are controlled by DMEMCR <MUXE>
and <MUXW0, 1>. The relation between address width
and bus width is below.
Figures 3.7 (3), (4) show the access timing.
Table 3.7 Address Multiplex
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TMP95C061
Figure 3.7 (3). DRAM Access Timing (Normal Access Mode)
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TMP95C061
Figure 3.7 (4). DRAM Access Timing (Slow Access Mode)
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TMP95C061
(2)
Refresh Controller
i) CAS before RAS interval refresh mode
The TMP95C061 can output RAS/CAS used to
refresh the DRAM. At the same time the state signal
REFOUT which indicates a refresh cycle is output.
(Only for interval refresh mode.)
DRAM can be refreshed easily because RAS/CAS/
REFOUT output frequency and pulse width are programmable.
The refresh controller has the following features.
The refresh interval and refresh width for CAS before
RAS interval refresh mode depends on the DRAM
being used.
Therefore, TMP95C061 enables the refresh interval
and refresh cycle width to be set with the refresh controller register value according to the system clock
and DRAM that are being used.
Figure 3.7 (5) shows a timing example for CAS before
RAS refresh cycle.
CAS before RAS interval refresh
mode
CAS before RAS self refresh mode
• Refresh interval:
31 to 195 states (programmable)
• Refresh cycle width:
2 to 9 states (programmable)
• Dummy cycle can be generated
• Refresh cycle is asynchronous with CPU operation
cycle
• Refresh mode:
Figure 3.7 (5). Refresh Cycle Timing Example
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TMP95C061
How to set the register is described next.
Figure 3.7 (1) shows the bit structure of the refresh
control register DREFCR.
The insertion interval is set with the three bits DREFCR
<RS22 to 0> according to the system clock being
used.
Example:
➀ Refresh cycle insertion interval
When the system clock is 25MHz and the
DRAM refresh cycle is to be 15.6µs, set
these bits to “111”.
Table 3.13 (2) Refresh Cycle Insertion Interval
➁ The three bits DREFCR <RW2 to 0> can be used to
change the refresh cycle width (RAS, CAS Low output width). (2 to 9 states)
➂ Refresh cycle control
The refresh cycle can be disabled/enabled with the bit
DREFCR <RC>.
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ii) CAS before RAS self refresh mode
This mode is used when DRAM controller or is halted
with HALT (IDLE, STOP) instruction while refreshing
with CAS before RAS interval refresh mode (hereafter
referred to as interval mode).
However, REFOUT is not output. (“1” is output.)
Figure 3.7 (6) shows the self refresh mode timing diagram.
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TMP95C061
Figure 3.7 (6). Self Refresh Cycle Timing
This mode is executed as follows. First, the settings are
made fro normal interval mode. Then B3CS <SRFC> is
set to “0” before a HALT instruction to perform one
normal refresh. Then the CAS pin and RAS pin are kept
at low level and the self refresh mode is entered. Cancelling HALT and supplying a clock to the DRAM controller automatically sets DMEMCR <SRFC> to 1 and
cancels self refresh mode. After cancellation, refresh is
performed once normally and processing returns to
interval mode. (Note that when HALT is cancelled by a
reset, the I/O registers are initialized, therefore, refresh
is not normally performed.)
After DMEMCR <SRFC> to “0”, make sure that the
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TMP95C061
(4)
Priority
The DRAM refresh cycle may overlap with the DRAM
read/write cycle because it is not synchronized with
the CPU operating cycle. In this case, the DRAM controller gives priority to the cycle that starts operation
first. If the priority is given to the refresh cycle, a wait is
automatically inserted in the memory access cycle.
(5)
Bus Release Mode
The TMP95C061 has a bus release function. Setting
dedicated DRAM control pins (RAS, CAS, REFOUT)
enables selection of release mode (by setting the pins
to high impedance like other pins) or non-release
(remain driving) mode in which refresh cycle output is
supported. For the states of other pins at bus release,
see 3.14 (2), Pin states at bus release.
(i) Mode used by DRAM control dedicated pin to
release bus (DMEMCR <BRM> = 0)
When the bus release request (BUSRQ) pin is set to
active (low level), the TMP95C061 acknowledges
the bus release request. After the current bus cycle
(including DRAM access cycle) ends, the
TMP95C061 sets the DRAM control dedicated pin
(RAS, CAS, REFOUT) to high, sets the output buffer
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to off, and sets the pin to high impedance.
The refresh cycle is asynchronous with the access
cycle. When a refresh request is generated and the
refresh cycle is at wait because of a conflict with the
access cycle until the bus release, the bus release
timing is delayed until the refresh cycle is completed.
The refresh counter keeps counting during bus
release. The refresh request generated during bus
release is held for one cycle. The refresh cycle is
performed immediately after the TMP95C061
regains bus mastership.
The bus release request or refresh counter is asynchronous with the bus cycle. To use this mode, the
external bus master must generate a refresh cycle
during bus release.
(ii) Mode not used by DRAM control dedicated pin to
release bus (DMEMCR <BRM> = 1)
Valid even if the DRAM is not accessed by the external bus master during bus release. If this mode is
set, the DRAM dedicated pin does not release the
bus even if a bus release request is generated but
keeps supporting a refresh cycle only. Note that all
the other pins release the bus. Unlike (i), bus release
timing is not influenced by a refresh request.
A reset DMECR <BRM> to 0 and the DRAM control
dedicated pin to bus release mode.
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TMP95C061
(6)
Connection Example
(1) 8 bit bus configuration
(2) 16 bit bus configuration
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3.8 8-bit Timers
TMP95C061 contains four 8-bit timers (timers 0, 1, 2 and 3),
each of which can be operated independently. The cascade
connection allows these timers to be used as 16-bit timers.
The following four operating modes are provided for the 8-bit timers:
• 8-bit interval timer mode (4 timers)
• 16-bit interval timer mode (2 timers)
• 8-bit programmable square wave pulse generation (PPG:
variable duty with variable cycle) output mode (2 timers)
• 8-bit pulse width modulation (PWM: variable duty constant
with cycle) output mode (2 timers)
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Figure 3.8 (1) shows the block diagram of the 8-bit timer
(timer 0 and timer 1).
Timers 2/3 have the same circuit configuration as timer 0
and timer 1. The difference between Timer 0 and Timer 2 is
that Timer 0 has an external clock input pin (TI0), while Timer 2
has none.
Each interval timer consists of an 8-bit comparator, and 8bit timer register. Besides, timer flip-flops (TFF1, TFF3) are provided for each pair of timer 0/1 and timer 2/3.
Among the input clock sources for the interval timers, the
internal clocks of øT1, øT4, øT16, and øT256 are obtained
from the 9-bit prescaler shown in Figure 3.8 (2).
The operation modes and timer flip-flops of the 8-bit timer
are controlled by five control registers T01MOD, T23MOD,
TFFCR, TRUN, and TRDC.
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TMP95C061
Figure 3.8 (1). Block Diagram of 8-bit Timers (Timers 0 and 1)
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➀ Prescaler
These are 9 bit prescaler and prescaler clock selection
register to generates input clock for 8-bit Timer 0/1,
Timer 4/5 and Serial Interface 0/1.
The 8-bit Timer 0, uses 4 types of clock: øT1, øT4,
øT16 and øT256 among the prescaler output.
This prescaler can be run or stopped by the timer operation control register TRUN <PRRUN>. Counting starts
when <PRRUN> is set to “1”, while the prescaler is
cleared to zero and stops operation when <PRRUN>
is set to “0”.
Figure 3.8 (2). Prescaler
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TMP95C061
➁ Up-counter
There is an 8 bit binary counter which counts up by the
input clock pulse specified by the Timer 0/1 mode register T01MOD and Timer 2/3 mode register T23MOD.
The input clocks of timer 0/2 are selected from the
three internal clocks øT1, øT4, and øT16 and the
external clock input (TI0: timer 0 only) using the mode
register T01MOD and T23MOD.
The input clocks of timer 1/3 differ depending on the
operation mode. When the timers are set to 16 bit
timer mode, the overflows output of timer 1/3 are used
as the input clock. When the timers are not set to the
16 bit mode, the input clock is selected from the internal clocks øT1, øT16, and øT256, and the output
comparator (match detection).
Example:
When T01MOD <T10M1,0> = 01
the overflow output of timer 0
becomes the input clock of timer 1
(16-bit timer).
When T01MOD7, 6 = 00 and
T01MOD3, 2 = 01, øT1 becomes
the input of timer 1 (8 bit timer
mode).
Operation mode is also set by T01MOD register and
T23 MOD register. When reset, it is initialized to
T01MOD <T01M1, 0> = 00, T23MOD <T23M1, 0> =
00, whereby the up-counter is placed in the 8-bit timer
mode.
The counting and stop and clear of up-counter can
74
be controlled for each interval timer by the timer operation
control register TRUN. When reset, all up-counters will
be cleared to stop the timers.
➂ Timer register
This is an 8-bit register for setting an interval time.
When the set value of timer registers TREG0, TREG1,
TREG2, TREG3, matches the value of up-counter, the
comparator match detect signal becomes active. If the
set value is 00H, this signal becomes active when the
up-counter overflows.
Timer register TREG0/TREG2 is of double buffer structure, each of which makes a pair with register buffer.
The timer register double buffer register TRDC
<TR0DE, TR2DE> bit controls whether the double
buffer structure in the TREG0/TREG2 should be
enabled or disabled. It is disabled when <TR0DE>/
<TR2DE> = 0, and enabled when they are set to 1.
In the condition of double buffer state, the data is
transformed from the register buffer to the timer register when the 2n - 1 overflow occurs in PWM mode, or
at the PPG cycle in PPG mode.
When reset, it will be initialized to <TR0DE>/<TR2DE>
= 0 to disable the double buffer. To use the double
buffer, write data in the timer register, set <TR0DE>/
<TR2DE> to 1, and write the following data in the register buffer.
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TMP95C061
Figure 3.8 (3). Configuration of Timer Register 0/2
Note:
Timer register and the register buffer are allocated o the same memory address. When <TR0DE>/<TR2DE> = 0, the same value is written in the register buffer as well as the timer register, while when <TR0DE>/<TR2DE> = 1 only the register buffer is written.
The memory address of each timer register is as follows.
TREG0: 000022H
TREG1: 000023H
TREG2: 000026H
TREG3: 000027H
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All the registers are write-only and cannot be read.
The initial value is indeterminate; when using the 8-bit
timer, always write data to the timer register.
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Figure 3.8 (4). Timer 0/1 Mode Control Register (T01MOD)
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Figure 3.8 (5). Timer 2/3 Mode Register (T23MOD)
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Figure 3.8 (6). 8-Bit Timer Flip-flop Control Register (TFFCR)
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Figure 3.8 (7). Timer Operation Control Register (TRUN)
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Figure 3.8 (8). Timer Register Double Buffer Control Register (TRDC)
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➃
➄
Comparator
The operation of 8-bit timers will be described below:
A comparator compares the value in the up-counter
with the values to which the timer register is set. When
they match, the up-counter is cleared to zero and an
interrupt signal (INTT0 to 3) is generated. If the timer
flip-flop inversion is enabled, the timer flip-flop is
inverted at the same time.
(1)
8-bit Timer Mode
Four interval timers, 0, 1, 2, and 3, can be used independently as an 8-bit interval timer. All interval timers operate in the same manner, and thus, only the operation
of timer 1 will be explained below.
Timer flip-flop (timer F/F)
➀ Generating interrupts in a fixed cycle
The status of the timer flip-flop is inverted by the match
detect signal (comparator output) of each interval timer
and the value can be output to the timer output pins
TO1 (also used as PA2) and TO3 (also used as PA3).
The timer F/F are provided for a pair of timer 0/1 and
timer 2/3. The outputs of timer F/F are TFF1 and TFF3,
and output signals through the TO1 and TO3.
To generate timer 1 interrupt at constant intervals
using timer 1 (INTT1), first stop timer 1, then set the
operation mode, input clock, and synchronization to
T01MOD and TREG1, respectively. Then, enable interrupt
INTT1 and start the counting of timer 1.
Example: To generate timer 1 interrupt every 32µs at
fc = 25MHz, set each register in the following manner.
Use Table 3.8 (1) for selecting the input clock.
Table 3.8 (1) Setting the Interrupt Period and Input Clock for 8 Bit Timer
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Input clock
Interrupt period (at fc = 25MHz)
Resolution
øT1 (8/fc)
øT4 (32/fc)
øT16 (128/fc)
øT256 (2048/fc)
32µs to 81.92µs
12.8µs to 327.7µs
5.12µs to 1.311ms
81.92µs to 20.97ms
32µs
1.28µs
5.12µs
81.92µs
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➁ Generating a 50% duty square wave pulse
The timer flip-flop is inverted at constant intervals, and
its status is output to a timer output pin (TO1).
Example: To output a 1.92µs square wave pulse from
TO1 pin at fc = 25MHz, set each register in the
following procedures. Either timer 0 or timer 1
may be used, but this example uses timer 1.
Figure 3.8 (9). Square Wave (50% Duty) Output Timing Chart
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➂ Making timer 1 count up by match signal from timer
0 comparator
Set the 8-bit timer mode, and set the comparator output
of timer 0 as the input clock to timer 1.
Figure 3.8 (10). Timer 1 Count Up by Timer 0
➃ Output inversion with software
➄ Initial setting of timer flip-flop (TFF)
The value of timer flip-flop (timer F/F) can be inverted,
independent of timer operation.
Writing 00 into TFFCR <FF1C1, 0> inverts the value of
TFF1. Writing 00 into TFFCR <FF3C1, 0> inverts the
value of TFF3.
The value of TFF can be initialized to “0” or “1”, independent of timer operation.
For example, write “10” in TFFCR <FF1C1, 0> to
clear TFF1 to “0”, while write “01” in TFFCR
<TFF1C1, 0> to set TFF1 to “1”.
Note: The value of timer F/F and timer register cannot
be read.
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(2)
16-bit timer mode
A 16-bit interval timer is configurated by using the pair
of timer 0/1 and timer 2/3.
Timer 2/3 operate as Timer 0/1, so described have
about Timer 0/1.
To make a 16-bit interval timer by cascade connection
timer 0 and timer 1, set timer 0/timer 1 mode register
T01MOD <T01M1, 0> to “0, 1”.
When set in 16-bit timer mode, the overflow output of
timer 0 will become the input clock of timer 1, regardless of
the set value of clock control register TCLK.
The lower 8 bits of the timer (interrupt) cycle are set by
the timer register TREG0, and the upper 8 bits are set
by TREG1. Note that TREG0 always must be set first
(Writing data into TREG0 disables the comparator
temporarily, which is restarted by writing data into
TREG1).
Table 3.8 (2) Interrupt Period and Input Clock in 16 Bit Timer Mode
Input clock
Interrupt period (at fc = 25MHz)
Resolution
øT1 (8/fc)
øT4 (32/fc)
øT16 (128/fc)
32µs to 20.971ms
12.8µs to 83.885ms
5.12µs to 335.539ms
32µs
1.28µs
5.12µs
Setting example: To generate an interrupt INTT1 every 0.32
seconds at fc = 25MHz, set the following
values for timer registers TREG0 and
TREG1.
When counting with input clock of øT16
(5.12µs @ 25MHz)
0.32s ÷5.12µs = 62500 = F424H
Therefore, set TREG1 = F4H and TREG0 =
24H,respectively.
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The comparator match signal is output from timer 0
each time the up-counter UC0 matches TREG0,
where the up-counter UC0 is not be cleared, and then
the INTT0 is not decremented.
With the timer 1 comparator, the match detect signal is
output at each comparator timing when up-counter
UC1 and TREG1 values match. When the match
detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up-counters UC0
and UC1 are cleared to “0”, and the interrupt INTT1 is
generated. If inversion is enabled, the value of the
timer flip-flop TFF1 is inverted.
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Example: When TREG1 = 04H and TREG0 = 80H
Figure 3.8 (11). Timer Output by 16-Bit Timer Mode
(3)
8-bit PPG (Programmable Pulse Generation) Mode
Square wave pulse can be generated at any frequency
and duty by timer 0 and timer 2. The output pulse may
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be either low-active or high-active. In this mode, timer
1 and timer 3 cannot be used.
Timer 0 outputs pulse through TO1 pin (also used as
PA2). Timer 2 outputs pulse to TO3 pin (also used as
PA3).
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As an example, Timer 0 will be explained below. Timer 2
provides the same functions.
Figure 3.8 (12). Block Diagram of 8-bit PPG Output Mode
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When the double buffer of TREG0 is enabled in this mode,
the value of register buffer will be shifted in TREG0 each
TREG1 matches UC0.
Example: Generating 1/4 duty 78.125kHz pulse (at fc =
25MHz)
• Calculate the value to be set for timer register
To obtain the frequency 78.125kHz, the pulse
cyc;e t should be: t = 1/78.125kHz = 12.8µs
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Use of the double buffer makes easy the handling of low
duty waves (when duty is varied).
Given øT1 = 0.32µs (at 25MHz),
12.8µs ÷ 0.32µs = 40
Consequently, to set the timer register 1 (TREG1) to
TREG1= 40 = 28H and then duty to 1/4, t x 1/4 = 12.8µs
x 1/4 = 3.2µs
3.2µs ÷ 0.32µs = 10
Therefore, set timer register 0 (TREG0) to TREG0 = 10
= 0AH.
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(4)
8-bit PWM (Pulse Width Modulation) Mode
This mode is valid only for timer 0/2. In this mode, 2-8
bit resolution of PWM pulse can be output. PWM pulse
is output through TO1 pin) when using timer 0. When
using timer 2, the pulse is through TO3 pin. Timer 1
and timer 3 are valid for 8-bit timers.
As an example, the PWM mode operation of Ti mer 0
will be explained below. Timer 2 provides the same
operation as Timer 0.
Timer output is inverted when up-counter (UC0)
matches the set value of timer register TREG0 or when
2n - 1 (n = 6, 7 or 8; specified by T01MOD <PWM01,
0>) counter overflow occurs. Up-counter UC1 is cleared
when 2n - 1 counter overflow occurs.
To use this PWM mode, the following conditions must
be satisfied.
(Set value of timer register) < (set overflow value of 2n 1 counter)
(Set value of timer register) ≠ 0
Figure 3.8 (13) shows the block diagram of this mode.
Figure 3.8 (13). Block Diagram of 8-Bit PWM Mode
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In this mode, the value of register buffer will be shifted in
TREG0 if 2n - 1 overflow is detected when the double buffer of
TREG0 is enabled.
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Use the double buffer makes easy the handling of small
duty waves.
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Example:
To realize 40.64µs of PWM cycle by øT1 = 0.32µs
(at fc = 25MHz),
40.64µs ÷ 0.32µs = 127 = 2n - 1
Consequently, n should be set to 7.
As the period of low level is 28.8µs, for T1 = 0.32µs,
set the following value for TREG0.
28.8µs ÷ 0.32µs = 90 = 5AH
To output the following PWM waves to TO1
pin at fc = 25MHz.
.
Table 3.8 (3) PWM Cycle and Selection of 2n - 1 Counter
PWM cycle (@fc = 25MHz)
øT16
øT256
20.2µs
80.6µs (12.4kHz)
322.6µs (3.1kHz)
27 - 1
40.6µs
162.6µs (6.2kHz)
650.2µs (1.5kHz)
28 - 1
81.6µs
326.4µs (3.1kHz)
1.31ms (0.8kHz)
26 - 1
90
øT1
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(5)
Table 3.8 (4) shows the list of 8-bit timer modes.
Table 3.8 (4) Selection of 8 Bit Timer Mode and Control Register
Timer mode
(8-bit timer x 2
channels)
TO1M
(T23M)
PWM0
(PWM2)
Upper input
T1CLK
(T3CLK)
Lower input
T0CLK
(T2CLK)
Invert select
FF1IS
(FF31S)
16-bit timer
(16-bit) x 1 ch
01
–
–
(External clock
øT1, 4, 16)
–
8-bit timer
(Input of upper timer is
output of power one)
00
–
00
(External clock
øT1, 4, 16)
0: Lower timer
1: Upper timer
8-bit timer x 2 ch
00
–
(øT1, 16, 256)
(External clock
øT1, 4, 16)
0: Lower timer
1: Upper time
8-bit PPG x 1 ch
10
–
–
(External clock
øT1, 4, 16)
–
8-bit PWM x 1 ch (Lower)
8-bit timer x 1 ch (Upper)
11
PWM cycle
(øT1, 16, 256)
(External clock
øT1, 4, 16)
–
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3.9 16-bit Timer
The TMP95C061 contains two (timer 4 and timer 5) multifunctional 16-bit timer/event counter with the following operating
modes:
•
•
•
•
•
•
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16-bit interval timer mode
16-bit event counter mode
16-bit programmable pulse generation (PPG) mode
Frequency measurement mode
Pulse width measurement mode
Time differential measurement mode
Timer/event counter consists of 16-bit up-counter, two
16-bit timer registers, two 16-bit capture registers (one of them
applies double-buffer), two comparators, capture input controller,
and timer flip-flop and the control circuit.
Timer/event counter is controlled by 4 control registers:
T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN, and T45CR.
Figure 3.9 (1), (2) shows the block diagram of the 16-bit
timer/event counter (timer 4 and timer 5).
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Figure 3.9 (1). Block Diagram of 16-Bit Timer (Timer 4)
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Figure 3.9 (2). Block Diagram of 16-bit Timer (Timer 5)
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Figure 3.9 (3). 16-Bit Timer Mode Controller Register (T4MOD) (1/2)
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Figure 3.9 (4). 16-Bit Timer Mode Controller Register (T4MOD) (2/2)
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Figure 3.9 (5). 16-Bit Timer 4 F/F Control (T4FFCR)
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Figure 3.9 (6). 16-Bit Timer Mode Control Register (T5MOD) (1/2)
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Figure 3.9 (7). 16-Bit Timer Mode Control Register (T5MOD) (2/2)
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Figure 3.9 (8). 16-Bit Timer 5 F/F Control (T5FFCR)
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Figure 3.9 (9). 16-Bit Timer (Timer 4, 5) Control Register (T45CR)
Figure 3.9 (10). Timer Operation Control Register (TRUN)
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➀ Up-counter (UC16)
UC16 is a 16-bit binary counter which counts up
according to the input clock specified by T4MOD
<T4CLK1, 0> register or T5MOD <T5CLK1, 0> register.
As the input clock, one of the internal clocks øT1, øT4,
and øTI6 from 9-bit prescaler (also used for 8-bit
timer), and external clock from TI4 pin (also used as
PB0/INT4 pin) and TI67 pin (also used as PB4/INT6
pin) can be selected. When reset, it will be initialized to
<T4CLK1, 0>/<T5CLK1, 0> = 00 to select TI4, TI6
input mode. Counting or stop and clear of the counter
is controlled by timer operation control register TRUN
<T4RUN>, <T5RUN>.
When clearing is enabled, up-counter UC4/UC5 will be
cleared to zero each time it coincides or matches the
The timer register TREG4/TREG6 make double buffer
structure, which are paired with register buffer. The
timer control register T45CR <DB4EN, DB6EN> controls whether the double buffer structure should be
enabled or disabled. : disabled when <DB4EN, DB6EN>
= 0, while enabled when <DB4EN, DB6EN> = 1.
When the double buffer is enabled, the timing to transfer
data from the register buffer to the timer register is at
the match between the up-counter (UC4 and UC5)
and timer register TREG5 and TREG7.
When reset, it will be initialized to <DB4EN, DB6EN> =
0, whereby the double buffer is disabled. To use the double
buffer, write data in the timer register, set <DB4EN,
DB6EN> = 1, and then write the following data in the register buffer.
102
timer register TREG5, TREG7. The “clear enable/disable” is set by T4MOD <CLE> and T5MOD <CLE>.
If clearing is disabled, the counter operates as a freerunning counter.
➁ Timer Registers
These two 16-bit registers are used to set the value of
counter. When the value of up-counter UC4/UC5
matches the set value of this timer register, the comparator match detect signal will be active.
Setting data for timer register (TREG4, TREG5/TREG6
and TREG7) is executed using 2 byte data load
instruction or by using 1 byte data load instruction
twice for lower 8 bits and upper 1 bits in order.
TREG4, TREG6 and register buffer are allocated to the
same memory addresses 000030H/000031H and
000040H/000041H. When <DB4EN, DB6EN> = 0, the
same value will be written in both the timer register and
the register buffer. When <DB4EN, DB6EN> = 1, the
value is written into only the register buffer.
Since the timer register is indeterminate after a reset,
always write data to higher and lower bits.
➂ Capture Register (CAP1 and CAP2)
These 16-bit registers are used to hold the values of
the up-counter.
Data in the capture registers should be read by a 2byte load instruction or two 1- byte data load instruction,
from the lower 8 bits followed by the upper 8 bits.
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➃ Capture Input Control Circuit
counter UC4/UC5 value with the set value of (TREG4,
TREG5, TREG5/TREG6, TREG7) to detect the match.
When a match is detected, the comparators generate
an interrupt (INTTR4, INTTR5/INTTR6, INTTR7), respectively. The up-counter UC4/UC5 is cleared only when
UC4/UC5 matches TREG5/TREG7. (The clearing of upcounter UC4/UC5 can be disabled by setting T4MOD
<CLE>/T5MOD <CLE> = 0).
This circuit controls the timing to latch the value of
up-counter UC4/UC5 into (CAP1, CAP2/CAP3,
CAP4). The latch timing of capture register is controlled by
register T4MOD <CAP12M1, 0>/T5MOD <CAP34M1,
0>.
• When T4MOD <CAP12M1, 0>/T5MOD <CAP34M1,
0> = 00
Capture function is disabled. Disable is the default on
reset.
➅ Timer Flip-flop (TFF4/TFF6)
This flip-flop is inverted by the match detect signal
from the comparators and the latch signals to the capture registers. Disable/enable of the inversion can be
set for each element by T4FFCR <CAP2T4, CAP1T4,
EQ5T4, EQ4T4> /T5FFCR <CAP 4T6, CAP3T6,
EQ7T6, EQ6T6>. TFF5/TFF6 will be inverted when
“00” is written in T4FFCR < TFF4C1, 0>/T5FFCR <
TFF6C1, 0>. Also, it is set to “1” when “10” is written,
and cleared to “0” when “10” is written. The value of
TFF4 can be output to the timer output pin TO4 (commonly
used as PB2)/TO6 (also used used as PB6).
• When T4MOD <CAP12M1, 0>/T5MOD <CAP34M1,
0> = 01
Data is loaded to CAP1/CAP3 at the rise edge of TI4
pin (also used as PB0/INT7) input, while data is loaded
to CAP2/CAP4 at the TI5 pin (also used as P81/INT5)
and TI7 pin (also used as PB5/INT7) input. (Time difference measurement)
• When T4MOD <CAP12M1, 0>/T5MOD <CAP34M1,
0> = 10
Data is loaded to CAP1/CAP3 at the rise edge of the
TI4 pin/TI6 pin input, while data is loaded to CAP2/CAP4
at the fall edge. Only in this setting, interrupt INT4/INT6
occurs at fall edge. (Pulse width measurement)
➆ Timer Flip-flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator and the latch signal to the capture register CAP2. TFF5 will be inverted when “00” is
written in T4FFCR < TFF5C1, 0>. Also, it is set to “1”
when “10” is written, and cleared to “0” when “10” is
written. The value of TFF5 can be output to the timer output pin TO5 (commonly used as P82).
• When T4MOD <CAP12M1, 0>/T5MOD <CAP34M1,
0> = 11
Data is loaded to CAP1/CAP3 at the rise edge of timer flipflop TFF1, while to CAP2/CAP4 at the fall edge.
Note: This flip-flop (TFF5) is contained only in the 16-bit timer 4.
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAPIN>, T5MOD <CAP3IN>, the current
value of up-counter will be loaded to capture register
CAP1/CAP3. It is necessary to keep the prescaler in
RUN mode (TRUN <PRUN> to be “1”).
➄ Comparator
(1)
16-bit Timer Mode
Timer 4 and Timer 5 can be operated independently. Both
can be operated all the same, so, Timer 4 is shown here
for the purposes of illustration only.
Generating interrupts at fixed intervals, the interval time
is set in the timer register TREG5 to generate the interrupt INTTR5.
These are 16-bit comparators which compare the up-
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(2)
16-bit Event Counter Mode
In timer mode as described in above, the timer can be
used as an event counter by selecting the external
clock (TI4 pin/TI6 pin input) as the input clock. To read
the value of the counter, first perform “software capture” once and read the captured value.
(3)
16-bit Programmable Pulse Generation (PPG) Output
Mode
Timer 4 and Timer 5 can be operated all the same,
Timer 4 is used for the purposes of explanation.
The PPG mode is obtained by inversion of the timer
The counter counts at the rise edge of TI4 pin/TI6 pin
input.
TI4 pin/TI6 pin can also be used as PB0/INT4 and
PB4/INT6.
Since both timers operate in exactly the same way,
timer 4 is used for the purposes of explanation.
flip-flop TFF4 that is to be enabled by match of the upcounter UC4 with the timer register TREG 4 or 5 and to
be output to TO4 (also used as P82). In this mode, the
following conditions must be satisfied.
(Set value of TREG4) < (Set value of TREG5)
Figure 3.9 (11). Programmable Pulse Generation (PPG) Output Waveforms
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When the double buffer of TREG4 is enabled in this
mode, the value of register buffer 4 will be shifted in
TREG4 at match with TREG5. This feature makes easy
the handling of low duty waves.
Figure 3.9 (12). Operation of Register Buffer
Figure 3.9 (13). Block Diagram of 16-Bit PPG Mode
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(4)
Application examples of capture function
➀ One-shot pulse output from external trigger pulse
Timer 4 and Timer 5 can be operated all the same,
Timer 4 is used for the purposes of explanation
The loading of up-counter (UC4) values into the capture registers CAP1 and CAP2, the timer flip-flop TFF4 inversion
due to the match detection by comparators CP4 and
CP5, and the output of the TFF4 status to TO4 pin can
be enabled or disabled. Combined with interrupt function, they can be applied in many ways, for example:
Set the up-counter UC4 in free-running mode with the
internal input clock, input the external trigger pulse
from TI4 pin, and load the value of up-counter into the
capture register CAP1 at the rising edge of TI4 pin.
Then set to T4MOD <CAP12M1, 0> = 01.
When the interrupt INT4 is generated at the rising edge
of TI4 input, set the CAP1 value (c) plus a delay time (d)
to TREG4 (= c + d), and set the above set value (c + d)
pulse a one shot pulse width (p) the TREG5 (= c + d +
p). When the interrupt INT4 occurs the T4FFCR
<EQ5T4, EQ4T4> register should be set that the TFF4
inversion is enabled only when the up-counter value
matches TREG4 or 5. When interrupt INTTR5 occurs,
this inversion will be disabled.
➀ One-shot pulse output from external trigger pulse
➁ Frequency measurement
➂ Pulse width measurement
➃ Time difference measurement
Figure 3.9 (14). One-Shot Output (with Delay)
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Setting example: To output 2ms one-shot pulse with a
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3ms delay to the external trigger pulse to TI4 pin.
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When delay time is unnecessary, invert timer flip-flop
TFF4 when the up-counter value is loaded into capture
register 1 (CAP1), and set the CAP1 value (c) plus the
one-shot pulse width (p) to TREG5 when the interrupt
INT4 occurs. The TFF4 inversion should be enabled
before the up-counter (UC4) value matches TREG5,
and disabled when generating the interrupt INTTR5.
Figure 3.9 (15). One-Shot Pulse Output (without Delay)
➁ Frequency measurement
The frequency of the external clock can be measured
in this mode. The clock is input through the TI4 pin,
and its frequency is measured by using the 8-bit timers
(Timer 0 and Timer 1) and the 16-bit timer/event
counter (Timer 4).
The TI4 pin input should be selected for the input clock
of Timer 4. The value of the up-counter is loaded into
the capture register CAP1 at the rise edge of the timer
flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and
into CAP2 at its fall edge.
The frequency is calculated by the difference between
the loaded values CAP1 and CAP2 when the interrupt
(INTT0 or INTT1) is generated by either 8-bit timer.
Figure 3.9 (16). Frequency Measurement
For example, if the value for the level “1” width of TFF1
of the 8-bit timer is set to 0.5 sec. and the difference
108
between CAP1 and CAP2 is 100, the frequency will be
100/0.5 [s] - 200 [Hz].
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➂ Pulse width measurement
This mode allows to measure the “H” level width of an
external pulse. While keeping the 16-bit timer/event
counter counting (free-running) with the internal clock
input, the external pulse is input through the TI4 pin.
Then the capture function is used to load the UC4 values into CAP1 and CAP2 at the rising edge and falling
edge of the external trigger pulse respectively. The
interrupt INT4 occurs at the falling edge of TI4.
The pulse width is obtained from the difference
between the values of CAP1 and CAP2 and the internal
clock cycle.
For example, if the internal clock is 8.0 microseconds
and the difference between CAP1 and CAP2 is 100,
the pulse width will be 100 x 0.8µs = 80µs.
Figure 3.9 (17) Pulse Width Measurement
Note: Only in this pulse width measuring mode (T4MOD <CAP12M1, 0> = 10), external interrupt INT1 occurs at the falling edge of TI4 pin input. In other
modes, it occurs at the rising edge.
The width of “L” level can be measured from the difference
between the first C2 and the second C1 at the second
INT1 interrupt.
➃ Time difference measurement
This mode is used to measure the difference in time
between the rising edges of external pulses input
through TI4 and TI5.
Keep the 16-bit timer/event counter (Timer 4) counting
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(free-running) with the internal clock, and load the UC4
value into CAP1 at the rising edge of the input pulse to
TI4. Then the interrupt INT1 is generated.
Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input pulse to TI5, generating the interrupt INT2.
The time difference between these pulses can be
obtained from the difference between the time counts
at which loading the up-counter value into CAP1 and
CAP2 has been done.
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Figure 3.9 (18). Time Difference Measurement
(5)
Different Phased Pulses Output Mode
In this mode signals with any different phase can be
output by free-running up-counter UC4.
When the value in up-counter UC4 and the value in
TREG4 (TREG5) match, the value in TFF4 (TFF5) is
inverted and output to TO4 (TO5).
This mode can be used only in Timer 4.
Figure 3.9 (19). Phase Output
Cycles (counter overflow time) of the above output
waves are listed on Table 3.9 (2). The following table
shows cycles (counter overflow) of the above output
wave.
110
20MHz
25MHz
øT1
26.214ms
20.97ms
øT4
104.856ms
83.88ms
øT16
419.424ms
335.54ms
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3.10 Stepping Motor Control/Pattern Generation Port
TMP95C061 contains two channels (PG0 and PG1) of 4-bit
hardware stepping motor control/pattern generation (herein
after called PG) which actuate in synchronization with the (8bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit I/
O ports P7.
Channel 0 (PG0) is synchronous with 8-bit timer 2 or
timer 3, 16-bit timer 5, to update the output.
The PG ports are controlled by control registers
(PG01CR) and can select either stepping motor control mode
or pattern generation mode. Each bit of the P7 can be used as
the PG port.
PG0 and PG1 can be used independently.
All PG operate in the same manner except the following
points, and thus only the operation of PG0 will be explained
below.
Different Points between PG0 and PG1
Trigger Signal
PG0
PG1
from 8-bit timer 0, 1 or
16-bit timer 4
from 8-bit timer 2, 3 or
16-bit timer 5
Figure 3.10 (1). PG Block Diagram
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Figure 3.10 (2a). Pattern Generation Control Register (PG01CR)
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Figure 3.10 (2b). Pattern Generation Control Register (PG01CR)
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Figure 3.10 (3). Pattern Generation 0 Register (PG0REG)
Figure 3.10 (4). Pattern Generation 1 Register (PG1REG)
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Figure 3.10 (5). 16-bit Timer Trigger Control Register (T45CR)
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Figure 3.10 (6). Connection of Timer and Pattern Generator
(1)
Pattern Generation Mode
PG functions as a pattern generation according to the
setting of PG01CR <PAT1>. In this mode, writing from
CPU is executed only on the shifter alternate register.
Writing a new data should be done during the interrupt
operation of the timer for shift trigger, and a pattern can
be output synchronous with the timer.
In this mode, set PG01CR <PG0M> and <PG1M> to
1, and PG01CR <CCW0> and <CCW1> to 0.
The output of this pattern generator is output to port 7;
since port and functions can be switched on a bit basis
using port 7 function control register P7FC, any port
pin can be assigned to pattern generator output.
Figure 3.10 (7) shows the block diagram of this mode.
Example of pattern generation mode
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Figure 3.10 (7). Pattern Generation Mode Block Diagram (PG0)
In this pattern generation mode, only writing the output
latch is disabled by hardware, but other functions do the same
operation as 1-2 excitation in stepping motor control port
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mode. Accordingly, the data shifted by trigger signal from a
timer must be written before the next trigger signal is output.
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(2)
Stepping Motor Control Mode
➀ 4-phase 1-Step/2-Step Excitation
Figure 3.10 (8) and Figure 3.10 (9) show the output
waveforms of 4-phase 1 excitation and 4-phase 2
excitation, respectively, when channel 0 (PG0) is
selected.
Figure 3.10 (8). Output Waveforms of 4-Phase 1-Step Excitation (Normal Rotation and Reverse Rotation)
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Figure 3.10 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation)
The operation when channel 0 is selected is explained
below.
The output latch of PG0 (also used as P6) is shifted at
the rising edge of the trigger signal from the timer to be
output to the port.
The direction of shift is specified by PG01CR
<CCW0>: Normal rotation (PG00 → PG01 → PG02 →
PG03) when <CCW0> is set to “0”; reverse rotation
(PG00 ← PG01 ← PG02 ← PG03) when “1”. 4-phase
1-step excitation will be selected when only one bit is
set to “1” during the initialization of PG, while 4-phase
2-step excitation will be selected when two consecutive bits are set to “1”.
The value in the shift alternate registers are ignored
when the 4-phase 1-step/2-step excitation mode is
selected.
Figure 3.10 (10) shows the block diagram.
Figure 3.10 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation (Normal Rotation)
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➁ 4-Phase 1-2 Step Excitation
Figure 3.10 (11) shows the output waveforms of 4phase 1 -2 step excitation when channel 0 is selected.
Figure 3.10 (11). Output Waveforms of 4-Phase 1-2 Step Excitation (Normal Rotation and Reverse Rotation)
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The initialization for 4-phase 1-2 step excitation is as
follows:
By rearranging the initial value “b7 b6 b5 b4 b3 b2 b1
b0” to “b7 b3 b6 b2 b5 b1 b4 b0”, the consecutive 3
bits are set to “1” and other bits are set to “0” (positive
logic).
For example, if b7, b3, and b6 are set to “1", the initial
value becomes “11001000”, obtaining the output
waveforms as shown in Figure 3.10 (11).
To get an output waveform of negative logic, set values
1’s and 0’s of the initial value should be inverted. For
example, to change the output waveform shown in
Figure 3.10 (11) into negative logic, change the initial
value to “00110111”.
The operation will be explained below for channel 0.
The output latch of PG0 (shared by P7) and the shifter
alternate register (SA0) for Pattern Generation are
shifted at the rising edge of trigger signal from the timer
to be output to the port. The direction of shift is set by
PG01CR <CCW0>.
Figure 3.10 (12) shows the block diagram.
Figure 3.10 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)
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Setting example: To drive channel 0 (PG0) by 4-phase 1-2
step excitation (normal rotation) when
(3)
Trigger Signal From Timer
The trigger signal from the timer which is used by PG is
timer 0 is selected, set each register as follows:
not equal to the trigger signal of timer flip-flop (TFF1,
TFF4, TFF5, and TFF6) and differs as shown in Table
3.10 (1) depending on the operation mode of the timer.
Table 3.10 (1) Select of Trigger Signal
TFF1 Inversion
Note:
8-bit timer mode
Selected by TFFCR <TFF1IS> when the up-counter value matches
TREG0 or TREG1 value.
16-bit timer mode
When the up-counter value matches with both TREG0 and TREG1
values. (The value of up-counter = TREG1*28 + TREG0)
PPG output mode
When the up-counter value matches with both TREG0 and TREG1.
When the up-counter value matches TREG1 value (PPG cycle).
PWM output mode
When the up-counter value matches TREG0 value and PWM cycle.
Trigger signal for PG is not generated.
To shift PG, TFFCR <FF1IE> must be set to “1” to enable TFF1 inversion.
Channel 1 of PG can be synchronized with the 16-bit
timer Timer 4/Timer 5. In this case, the PG shift trigger
signal from the 16-bit timer is output only when the upcounter UC4/UC5 value matches TREG5/TREG7.
When using a trigger signal from Timer 4, set either
T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1” and a
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PG Shift
trigger is generated when the value in UC4 and the
value in TREG5 match. When using a trigger signal
from Timer 5, set T5FFCR <EQ7T6> to 1. Generates a
trigger when the value in UC5 and the value in TREG7
match.
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(4)
Application of PG and Timer Output
As explained in “Trigger signal from timer”, the timing
to shift PG and invert TFF differs depending on the
mode of timer. An application to operate PG while
operating an 8-bit timer in PPG mode will be explained
below.
To drive a stepping motor, in addition to the value of
each phase (PG output), synchronizing signal is often
required at the timing when excitation is changed over.
In this application, port 7is used as a stepping motor
control port to output a synchronizing signal to the
TO1 pin (shared by PA2).
Figure 3.10 (13). Output Waveforms of 4-Phase 1-Step Excitation
Setting example:
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3.11 Serial Channel
TMP96C061 contains two serial Input/Output channels.
●
I/O interface mode
●
Asynchronous transmission
(UART) mode
The serial channel has the following operation modes:
Mode 0: To transmit and receive I/O data as well as
the synchronizing signal SCLK for extending I/O.
Mode 1: 7-bit data
Mode 2: 8-bit data
Mode 3: 9-bit data
In mode 1 and mode 2, a parity bit can be added. Mode
3 has wake-up function for making the master controller start
slave controllers in serial link (multi-controller system).
Figure 3.11 (1) shows the data format (for one frame) in
each mode.
Figure 3.11 (1). Data Formats
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The serial channel has a buffer register for transmitting
and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving
operations can be done independently (full duplex).
However, in I/O interface mode, SCLK (serial clock) pin is
used for both transmission and receiving, the channel
becomes half-duplex.
The receiving data register is of a double buffer structure
to prevent the occurrence of overrun error and provides one
frame of margin before CPU reads the received data. The
receiving data register stores the already received data while
the buffer register receives the next frame data.
By using CTS and RTS (there is no RTS pin, so any one
port must be controlled by software), it is possible to halt data
send until CPU finishes reading receive data every time a frame
is received (Handshake function).
In the UART mode, a check function is added not to start
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is
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detected to be normal at least twice in three samplings.
When the transmission buffer becomes empty and
requests the CPU to send the next transmission data, or when
data is stored in the receiving data register and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs.
Besides, if an overrun error, parity error, or framing error occurs
during receiving operation, flag SC0CR/SC1CR <OERR,
PERR, FERR> will be set.
The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by dividing the frequency
of four clocks (φT0, φT2, φT8, and φT32) from the internal prescaler (shared by 8-bit/16-bit timer) by the value 2 to 16.
In I/O interface mode, it is possible to input synchronous
signals as well as to transmit or receive data by external clock.
3.11.1 Control Registers
The serial channel is controlled by three control registers
SC0CR, SC0MOD, and BR0CR. Transmitted and received
data is stored in register SC0BUF.
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Figure 3.11 (2). Serial Mode Control Register (Channel 0, SC0MOD)
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Figure 3.11 (3). Serial Control Register (Channel, SC0CR)
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Figure 3.11 (4). Serial Channel Control (Channel 0, BR0CR)
Figure 3.11 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)
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Figure 3.11 (6). Serial Mode Control Register (Channel 1, SC1MOD)
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Figure 3.11 (7). Serial Control Register (Channel 1, SC1CR)
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Figure 3.11 (8). Baud Rate Generator Control Register (Channel 0, BR0CR)
Figure 3.11 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
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Figure 3.11 (10). Port 9 Function Register (P9FC)
Port 3.11 (11). Port 9 Open Drain Enable Register (ODE)
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3.11.2 Configuration
Figure 3.11 (12) shows the block diagram of the serial channel 0.
Figure 3.11 (12). Block Diagram of the Serial Channel 0
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Figure 3.11 (13) shows the block diagram of the serial channel 1.
Figure 3.11 (13). Block Diagram of the Serial Channel 1
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➀ Baud Rate Generator
Baud rate generator comprises a circuit that generates transmission and receiving clocks to determine the
transfer rate of the serial channel.
The input clock to the baud rate generator, φT0 (fc/
4), φT2 (fc/16), φT8 (fc/64), or φT32 (fc/256) is generated
by the 9-bit prescaler which is shared by the timers. One
●
UART mode
Transfer rate =
●
of these input clocks is selected by the baud rate generator control register bit <BR0CK1/0>/<BR1CK1.0> of
BR0CR/BR1CR.
The baud rate generator includes a 4-bit frequency
divider, which divides frequency by 2 to 16 values to
determine the transfer rate.
How to calculate a transfer rate when the baud rate
generator is used is explained below.
Input clock of baud rate generator
÷ 16
Frequency divisor of baud rate generator
I/O interface mode
Transfer rate =
Input clock of baud rate generator
÷2
Frequency divisor of baud rate generator
The relation between the input clock and the source clock (fc) is as follows:
φT0 = fc/4
φT2 = fc/16
φT8 = fc/64
φT32 = fc/256
Accordingly, when source clock fc is 12.288 MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate
in UART mode becomes as follows:
Transfer rate =
fc/16 ÷ 16
5
= 12.288 x 106/16/5/16 = 9600 (bps)
Table 3.11 (1) shows an example of the transfer rate in UART mode.
Also with 8-bit timer 2, the serial channel can get a transfer rate. Table 3.11 (2) shows an example of baud rate using
timer 2.
Table 3.11 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used)
Unit (kbps)
Input Clock
fc [Mhz]
Note:
Frequency
Divisor
φT0
(fc/4)
φT2
(fc/16)
φT8
(fc/64)
φT32
(fc/256)
9.830400
2
76.800
19.200
4.800
1.200
↑
4
38.400
9.600
2.400
0.600
↑
8
19.200
4.800
1.200
0.300
↑
16
9.600
2.400
0.600
0.150
12.288000
5
38.400
9.600
2.400
0.600
↑
A
19.200
4.800
1.200
0.300
14.745600
3
76.800
19.200
4.800
1.200
↑
6
38.400
9.600
2.400
0.600
↑
C
19.200
4.800
1.200
0.300
Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table.
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Table 3.11 (2) Selection of Transfer Rate (1) (When Timer 2 (Input Clock φT1) is Used)
Unit (Kbps)
fc
TREG0
12.288MHz
1H
96
2H
48
3H
32
4H
24
5H
19.2
8H
12
AH
9.6
10H
6
14H
4.8
12MHz
9.8304MHz
8MHz
6.144MHz
76.8
62.5
48
38.4
31.25
31.25
24
16
19.2
12
9.6
9.6
6
4.8
4.8
3
2.4
How to calculate the transfer rate (when timer 2 is used):
Transfer rate =
fc
TREG2 x 8 x 16
↑
(When Timer 2 (input clock φT1) is used)
Input clock of Timer 2
φT1 = 8/fc
φT4 = 32/fc
φT16 = 128/fc
Note 1: Timer 2 match detect signal cannot be used as the transfer clock in I/O interface mode.
➁ Serial Clock Generation Circuit
➂ Receiving Counter
This circuit generates the basic clock for transmitting
and receiving data.
The receiving counter is a 4-bit binary counter used in
asynchronous communication (UART) mode and
counts up by SIOCLK clock. Sixteen pulses of SIOCLK
are used for receiving one bit of data, and the data bit
is sampled three times at 7th, 8th and 9th clock.
With the three samples, the received data is evaluated
by the rule of majority.
For example, if the sampled data bit is “1", “0” and “1”
at 7th, 8th and 9th clock respectively, the received data
is evaluated as “1”. The sampled data “0", “0” and “1”
is evaluated that the received data is “0”.
1) I/O interface mode (channel 1 only)
When in SCLK output mode with the setting of SC1CR
<IOC> = “0", the basic clock will be generated by
dividing by 2 the output of the baud rate generator as
described before. When in SCLK input mode with the
setting of SC0CR <IOC> = “1", the rising edge or falling edge will be detected according to the setting of
SC0CR <SCLKS> register to generate the basic clock.
➃ Receiving Control
2) Asynchronous Communication (UART) mode
1) I/O interface mode (channel 1 only)
According to the setting of SC0MOD/SC1MOD <SC1,
0>, the above baud rate generator clock, internal clock
φ1 (max. 500 Kbps @ fc = 16MHz), or the match
detect signal from timer 0 will be selected to generate
the basic clock SIOCLK.
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When in SCLK1 output mode with the setting of
SC1CR <IOC> = “0", RxD1 signal will be sampled at
the rising edge of shift clock which is output to SCLK
pin.
When in SCLK input mode with the setting SC1CR
<IOC> = “1", RxD1 signal will be sampled at the rising
edge or falling edge of SCLK input according to the
setting of SC1CR <SCLKS> register.
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2) Asynchronous Communication (UART) mode
The receiving control has a circuit for detecting the
start bit by the rule of majority. When two or more “0”
are detected during 3 samples, it is recognized as start
bit and the receiving operation is started.
Data being received is also evaluated by the rule of
majority.
➄ Receiving Buffer
To prevent overrun error, the receiving buffer has a
double buffer structure.
Received data is stored one bit by one bit in the receiving buffer 1 (shift register type). When 7 bits or 8 bits of
data are stored in the receiving buffer 1, the stored
data is transferred to another receiving buffer 2
(SC0BUF/SC1BUF), generating an interrupt INTRX0/
INTRX1. The CPU reads only receiving buffer 2
(SC0BUF/SC1BUF). Even before the CPU reads the
receiving buffer 2 (SC0BUF/SC1BUF), the received
data can be stored in the receiving buffer 1. However,
unless the receiving buffer 2 (SC0BUF/SC1BUF) is
read before all bits of the next data are received by the
receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of the receiving buffer 1
will be lost, although the contents of the receiving
buffer 2 and SC0CR <RB8> SC1CR <RB8> are still
preserved. Reading data from receive data buffer 2
(SC0BUF/SC1BUF) clears interrupt request flags
INTR0 <IRX0C> and INTRX1 <IRX1C7>.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SC0CR <RB8>/SC1CR <RB8>.
When in 9-bit UART mode, the wake-up function of
the slave controllers is enabled by setting SC0MOD
<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/
INTRX1 occurs only when SC0CR <RB8>/SC1CR
<RB8> is set to “1”.
➅ Transmission Counter
Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK clock,
generating TxDCLK every 16 clock pulses.
Figure 3.11 (14). Generation of Transmission Clock
➆ Transmission Controller
1) I/O interface mode
In SCLK0 output mode with the setting of SC1CR
<IOC> = “0", the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge of shift
clock which is output from SCLK1 pin.
In SCLK1 input mode with the setting SC1CR <IOC> =
“1", the data in the transmission buffer are output bit
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by bit to TxD1 pin at the rising edge or falling edge of
SCLK input according to the setting of SC1CR
<SCLKS> register.
2) Asynchronous Communication (UART) mode
When transmission data is written in the transmission
buffer sent from the CPU, transmission starts at the rising edge of the next TxDCLK, generating a transmission shift clock TxDSFT.
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Handshake function
Serial channel 0 has a CTS0 pin. Using this pin, data
can be sent in units of one frame; thus, overrun errors
can be avoided. The handshake function is enabled/
disabled by SC0MOD <CTSE>.
When the CTS0 pin goes high, after completion of the
current data send, data send is halted until the CTS0
pin goes low again. The INTTX0 Interrupts are gener-
ated, requests the next send data to the CPU.
Though there is no RTS pin, a handshake function can
be easily configured by setting any port assigned to the
RTS function. The RTS should be output “High” to
request data send halt after data receive is completed
by a software in the RXD interrupt routine.
Figure 3.11 (15). Handshake Function
Figure 3.11 (16). Timing of CTS (Clear to Send)
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➇ Transmission Buffer
UART mode and with SC0MOD <RB8>/SC1MOD
when in 8-bit UART mode. If they are not equal, a parity error occurs, and SC0CR <PERR>/SC1CR
<PERR> flag is set.
Transmission buffer (SC0BUF/SC1BUF) shifts to and
sends the transmission data written from the CPU from
the least significant bit (LSB) in order, using transmission shift clock TxDSFT which is generated by the
transmission control. When all bits are shifted out, the
transmission buffer becomes empty and generates
INTTX0/INTTX1 interrupt.
➉ Error Flag
Three error flags are provided to increase the reliability
of receiving data.
➈ Parity Control Circuit
1. Overrun error <OERR>
When serial channel control register SC0CR <PE>/
SC1CR <PE> is set to “1", it is possible to transmit
and receive data with parity. However, parity can be
added only in 7-bit UART or 8-bit UART mode. With
SC0CR <EVEN>/SC1CR <EVEN> register, even (odd)
parity can be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
(SC0BUF/SC2BUF), and data are transmitted after
being stored in SC0BUF <TB7>/SC1BUF <TB7>
when in 7-bit UART mode while in SC0MOD <TB8>/
SC1MOD <TB8> when in 8-bit UART mode. <PE>
and <EVEN> must be set before transmission data are
written in the transmission buffer.
For receiving, data is shifted in the receiving buffer 1,
and parity is added after the data is transferred in the
receiving buffer 2 (SC0BUF/SC1BUF), and then compared with SC0BUF <RB7>/SC1BUF when in 7-bit
11
If all bits of the next data are received in receiving buffer
1 while valid data is stored in receiving buffer 2
(SCBUF0/1), an overrun error will occur.
2. Parity error <PERR>
The parity generated for the data shifted in receiving
buffer 2 (SCBUF0/1) is compared with the parity bit
received from RxD pin. If they are not equal, a parity
error occurs.
3. Framing error <FERR>
The stop bit of received data is sampled three times
around the center. If the majority is “0", a framing error
occurs.
Generating Timing
1) UART mode
Receiving
Mode
Interrupt timing
Note:
9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity, 7 Bit
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Framing error timing
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Overrun error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Framing error occurs after an interrupt has occurred. Therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit
period of transfer rate.
Transmitting
Mode
Interrupt timing
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9 Bit
8 Bit + Parity
8-Bit, 7 Bit + Parity, 7 Bit
Just before last bit is transmitted.
←
←
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2) I/O Interface mode
Transmission interrupt timing
SCLK output mode
Immediately after rise of last SCLK signal. (See Figure 3.11 (19).)
SCLK input mode
Immediately after rise of last SCLK signal (rising mode), or immediately after fall in falling mode.
(See Figure 3.11 (20).)
SCLK output mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after
last SCLK. (See Figure 3.11 (21).)
SCLK input mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after
SCLK. (See Figure 3.11 (22).)
Receiving interrupt timing
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3.11.3 Operational Description
(1)
Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins
for transmitting or receiving data to or from the external
shifter register.
This mode includes SCLK output mode to output synchronous clock SCLK and SCLK input mode to input
external synchronous clock SCLK.
Figure 3.11 (17). Example of SCLK Output Mode Connection
FIgure 3.11 (18). Example of SCLK Input Mode Connection
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➀ Transmission
In SCLK output mode, 8-bit data and synchronous clock
are output from TxD pin and SCLK0 pin, respectively, each
time the CPU writes data in the transmission buffer. When
all data is output, INTES0 <ITX0C> will be set to generate
INTTX0 interrupt.
Figure 3.11 (19) Transmitting Operation in I/O Interface Mode (SCLK Output Mode) (Channel 1)
In SCLK output mode, 8-bit data are output from TxD0
pin when SCLK0 input becomes active while data are
written in the transmission buffer by CPU.
When all data are output, INTES0 <ITX0C> will be set
to generate INTTX0 interrupt.
Figure 3.11 (20). Transmitting Operation in I/O Interface Mode (SCLK Input Mode)
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➁ Receiving
In SCLK output mode, synchronous clock is output
from SCLK pin and the data is shifted in the receiving
buffer 1 whenever the receive interrupt flag INTES0
<IRX0C> is cleared by reading the received data.
When 8-bit data are received, the data will be transferred in the receiving buffer 2 (SC1BUF) at the timing
shown below, and INTES1 <IRX1C> will be set again
to generate INTRX1 interrupt.
Figure 3.11 (21). Receiving Operation in I/O Interface Mode (SCLK Output Mode)
In SCLK input mode, the data is shifted in the receiving
buffer 1 when SCLK input becomes active, while the
receive interrupt flag INTES1 <IRX1C> is cleared by reading the received data. When 8-bit data is received, the
data will be shifted in the receiving buffer 2 (SC1BUF) at
the timing shown below, and INTES1 <IRX1C> will be set
again to generate INTRX interrupt.
Figure 3.11 (22). Receiving Operation in I/O Interface Mode (SCLK Input Mode)
Note:
For data receiving, the system must be placed in the receive enable state (SC1MOD <RXE> = “1”)
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TMP95C061
(2)
Mode 1 (7-bit UART Mode)
The 7-bit mode can be set by setting serial channel
mode register SC0MOD <SM1,0> /SC1MOD
<SM1,0> to “01”.
In this mode, a parity bit can be added, and the addition of a parity bit can be enabled or disabled by serial
channel control register SC0CR <PE> /SC1CR <PE>,
(3)
Mode 2 (8-bit UART Mode)
The 8-bit UART mode can be specified by setting
SC0MOD <SM1,0> / SC1MOD <SM1,0> to “10”. In
this mode, parity bit can be added, the addition of a
parity bit is enabled or disabled by SC0CR <PE>, and
144
and even parity or odd parity is selected by SC0CR
<EVEN> /SC1CR <EVEN> when <PE> is set to “1”
(enable).
Setting example:
When transmitting data with the following format, the control registers
should be set as described below.
Channel 0 is explained here.
even parity or odd parity is selected by SC0CR
<EVEN>/SC1CR <EVEN> when <PE> is set to “1”
(enable).
Setting example:
When receiving data with the following format, the control register
should be set as described below.
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TMP95C061
(4)
Mode 3 (9-bit UART Mode)
Wake-up function
The 9-bit UART mode can be specified by setting
SC0MOD <SM1,0> /SC1MOD <SM1,0> to “11”. In
this mode, parity bit cannot be added
For transmission, the MSB (9th bit) is written in
SC0M0D <TB8>, while in receiving it is stored in
SCCR <RB8>. For writing and reading the buffer, the
MSB is read or written first, then SC0BUF/SC1BUF.
In 9-bit UART mode, the wake-up function of slave
controllers is enabled by setting SC0MOD <WU> /
SC1MOD <WU> to “1”. The interrupt INTRX1/INTRX0
occurs only when <RB8> = 1.
Figure 3.11 (23). Serial Link Using Wake-Up Function
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TMP95C061
Protocol
➀ Select the 9-bit UART mode for master and slave controllers.
➂ The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The
MSB (bit 8) <TB8> is set to “1”.
➁ Set SC0MOD <WU>/SC1MOD <WU> bit of each
slave controller to “1” to enable data receiving.
146
➃ Each slave controller receives the above frame, and
clears WU bit to “0” if the above select code matches
its own select code.
➄ The master controller transmits data to the specified
slave controller whose SC0MOD <WU>/SC1MOD
<WU> bit
is cleared to “0.” The MSB (bit 8) <TB8> is cleared to
“0”.
➅ The other slave controllers (with the <WU> bit remaining at “1”) ignore the receiving data because their
MSBs (bit 8 or <RB8>) are set to “0” to disable the
interrupt INTRX0/INTRX1.
The slave controllers (WU = 0) can transmit data to the
master controller, and it is possible to indicate the end
of data receiving to the master controller by this transmission.
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Setting Example:
To link two slave controllers serially
with the master controller, and use
Since serial channels 0 and 1 operate in exactly the
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the internal clock φ1 (fc/2) as the
transfer clock.
same way, channel 0 is used for the purposes of explanation.
147
TMP95C061
3.12 Analog/Digital Converter
TMP95C061 contains a high-speed analog/digital converter
(A/D converter) with 4-channel analog input that features 10-bit
successive approximation.
Figure 3.12 (1) shows the block diagram of the A/D converter. The 4-channel analog input pins (AN3 to AN0) are
shared by input-only P9 and so can be used as input port.
Figure 3.12 (1). Block Diagram of A/D Converter
Note 1: This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and
hold circuit externally.
Note 2: To lower the power supply current in IDLE or STOP mode, depending on the timing, standby mode can be entered with the internal comparator in
enable state. Thus, stop A/D conversion before executing the HALT instruction.
The ladder resistor between VREF (VREFH) - AGND (VREFL) cannot be disconnected internallly.
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Figure 3.12 (2). A/D Control Register
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Figure 3.12 (3-1). A/D Conversion Result Register (ADREG0, 1)
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Figure 3.12 (3-2). A/D Conversion Result Register (ADREG2, 3)
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3.12.1 Operation
(1)
Analog Reference Voltage
High analog reference voltage is applied to the VREF
(VREFH) pin, and low analog reference voltage is
applied to AGND (VREFL) pin.
The reference voltage between VREG (VREFH) and
AGND (VREFL) is divided by 1024 using ladder resistance, and compared with the analog input voltage for
A/D conversion.
(2)
(4)
A/D Conversion Mode
Both fixed A/D conversion channel mode and A/D conversion channel scan mode have two conversion
modes, i.e., single and repeat conversion modes.
In fixed channel repeat mode, conversion of specified
one channel is executed repeatedly.
In scan repeat mode, scanning from AN0, … → AN3 is
executed repeatedly.
A/D conversion mode is selected by ADMOD <REPET,
SCAN>.
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(6)
A/D Conversion End and Interrupt
• A/D conversion single mode
ADMOD <EOCF> for A/D conversion end will be set to
“1,” ADMOD <ADBF> flag will be reset to “0,” and
INTAD interrupt will be enabled when A/D conversion
of specified channel ends in fixed conversion channel
mode or when A/D conversion of the last channel ends
in channel scan mode.
• A/D conversion repeat mode
For both fixed conversion channel mode and conversion channel scan mode, INTAD should be disabled
when in repeat mode. Always set the INTE0AD at
“000,” that disables the interrupt request.
Write “0” to ADMOD <REPET> to end the repeat
mode. Then, the repeat mode will be exited as soon as
the conversion in progress is completed.
(7)
Storing the A/D Conversion Result
The results of A/D conversion are stored in ADREG0 to
ADREG3 registers for each channel. In repeat mode,
the registers are updated whenever conversion ends.
ADREG0 to ADREG3 are read-only registers.
Starting A/D Conversion
A/D conversion starts when A/D conversion register
ADMOD <ADS> is written “1". When A/D conversion
starts, A/D conversion busy flag ADMOD <ADBF>
which indicates “conversion is in progress” will be set
to “1".
A/D Conversion Speed Selection
There are four A/D conversion speed modes. The
selection is executed by ADMOD <ADMCDSPEED>
register.
When reset, ADMOD <ADCS> will be initialized to “0,”
so that high speed conversion mode will be selected.
Analog Input Channels
Analog input channel is selected by ADMOD <ADCH1,
0>. However, which channel to select depends on the
operation mode of the A/D converter.
In fixed analog input mode, one channel is selected by
ADMOD <ADCH1, 0> among four pins: AN0 to AN3.
In analog input channel scan mode, the number of
channels to be scanned from AN0 is specified by
ADMOD <ADCH1, 0>, such as AN0 → AN1, AN0 →
AN1 → AN2, and AN0 → AN1 → AN2 → AN3.
When reset, A/D conversion channel register will be initialized to ADMOD <ADCH1, 0> = 00, so that AN0 pin
will be selected.
The pins which are not used as analog input channel
can be used as ordinary input port P9.
(3)
(5)
(8)
Reading the A/D Conversion Result
The results of A/D conversion are stored in ADREG0 to
ADREG3 registers. When the contents of one of
ADREG0 to ADREG3 registers are read, ADMOD
<EOCF> will be cleared to “0".
Reading data from the upper 8 bits of the register
(ADREG0H, ADREG1H, ADREG2H, ADREG3H) for
one of the channels in use clears interrupt request flag
INTE0AD <IADC>.
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TMP95C061
3.13 Watchdog Timer (Runaway Detecting Timer)
TMP95C061 is containing watchdog timer of Runaway detecting.
The watchdog timer (WDT) is used to return the CPU to
the normal state when it detects that the CPU has started to
malfunction (runaway) due to causes such as noise. When the
154
watchdog timer detects a malfunction, it generates a nonmaskable interrupt to notify the CPU of the malfunction, and
outputs 0 externally from watchdog timer out pin WDTOUT to
notify the peripheral devices of the malfunction.
Connecting the watchdog timer output to the reset pin
internally forces a reset.
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3.13.1 Configuration
Figure 3.13 (1) shows the block diagram of the watchdog timer
(WDT).
Figure 3.13 (1). Block Diagram of Watchdog Timer
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TMP95C061
The watchdog timer is a 22-stage binary counter which
uses φ (fc/2) as the input clock. There are four outputs from the
binary counter: 216/fc, 218/fc, 220/fc, and 222/fc. Selecting one
of the outputs with the WDMOD register generates a watchdog interrupt, and outputs watchdog timer out when an overflow occurs.
Since the watchdog timer out pin (WDTOUT) outputs “0”
due to a watchdog timer overflow, the peripheral devices can
be reset. The watchdog timer out pin is set to “1” after disabling WDT and clearing the watchdog timer (by writing a clear
code 4EH in the WDCR register).
LDW
(WDMOD), B100H ;
disable
LD
(WDCR), 4EH
;
write clear
SET
7, (WDMOD)
;
enable again
In other words, the WDTOUT continues to output “0” until
the clear code is written.
The watchdog timer out pin (WDTOUT) outputs 0 to 8 to
20 states (640ns to 1.6µs @ 25MHz) and resets itself.
(Example)
Figure 3.13 (2). Normal Mode
Figure 3.13 (3). Reset Mode
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TMP95C061
To disable, it is necessary to clear this bit to “0” and
write the disable code (B1H) in the watchdog timer
control register WDCR. This makes it difficult for the
watchdog timer to be disabled by runaway.
However, it is possible to return from the disable state
to enable state by merely setting <WDTE> to “1".
3.13.2 Control Registers
Watchdog timer WDT is controlled by two control registers
WDMOD and WDCR.
(1)
Watchdog Timer Mode Register (WDMOD)
➀ Setting the detecting time of watchdog timer
<WDTP>
➂ Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the
watchdog timer with RESET terminal, internally. Since
WDMOD <RESCR> is initialized to 0 at reset, a reset
by the watchdog timer will not be performed.
This 2-bit register is used to set the watchdog timer
interrupt time for detecting the runaway. This register is
initialized to WDMOD <WDTP1, 0> = 00 when reset,
and therefore 216/fSYS is set. (The number of states is
approximately 32,768).
(2)
➁ Watchdog timer enable/disable control register
<WDTE>
Watchdog Timer Control Register (WDCR)
This register is used to disable and clear the binary
counter of the watchdog timer function.
When reset, WDMOD <WDTE> is initialized to “1”
enable the watchdog timer.
• Disable control
WDMOD
←
0
–
–
–
–
–
x
x
Clear WDMOD <WDTE> to “0".
WDCR
←
1
0
1
1
0
0
0
1
Write the disable code (B1H).
• Enable control
The binary counter can be cleared and resume
counting by writing clear code (4EH) into the WDCR register.
Set WDMOD <WDTE> to “1".
• Watchdog timer clear control
WDCR
←
0
1
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0
0
1
1
1
0
Write the clear code (4EH).
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Figure 3.13 (4). Watchdog Timer Mode Register
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Figure 3.13 (5). Watchdog Timer Control Register
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3.13.3 Operation
The watchdog timer generates interrupt INTWD after the
detecting time set in the WDMOD <WDTP1, 0> register and
outputs a low level signal. The watchdog timer must be zerocleared by software before an INTWD interrupt is generated. If
the CPU malfunctions (runaway) due to causes such as noise,
but does not execute the instruction used to clear the binary
counter, the binary counter overflows and an INTWD interrupt
is generated. The CPU detects malfunction (runaway) due to
the INTWD Interrupt and it is possible to return to normal oper-
160
ation by an anti-malfunction program. By connecting the
watchdog timer out pin to peripheral devices’ resets, a CPU
malfunction can also be acknowledged to other devices.
The watchdog timer restarts operation immediately after
resetting is released.
The watchdog timer stops its operation in the IDLE and
STOP modes. In the RUN mode, the watchdog timer is
enabled.
However, the function can be disabled when entering the
RUN mode.
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3.14 Bus Release Function
The TMP95C061 supports a bus request pin (BUSRQ: also
used as P53) and a bus acknowledge pin (BUSAK: also used
as P54). Set these pins using P5CR and P5FC.
3.14 (1) Operation Description
When 0 is input to the BUSRQ pin, the TMP95C061 acknowledges a bus request. When the current bus cycle ends, the
TMP95C061 sets the address bus (A23 to A0) and bus control
signals (RD, WR, R/W, CS0 to 3) to high, then sets these signals and the data bus (D15 to D0) output buffer to off, sets the
BUSAK pin to low to indicate the bus is released. For bus
release timing and DRAM dedicated pin state when the DRAM
controller is in use, see 3.7 (5) Bus release mode.
During bus release, the TMP95C061 cannot access
internal I/Os and internal I/Os keep functioning. Therefore, the
watchdog timer continues counting. To use the bus release
function, set runaway detect time with bus release time in consideration.
3.14 (2) Pin States as Bus Release
Table 3.14 shows pin states at bus release.
Table 3.14 Pin States as Bus Release
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4.
Electrical Characteristics
4.1 Absolute Maximum
Symbol
Parameter
Rating
Unit
Vcc
Power Supply Voltage
-0.5 ~ 6.5
V
V IN
Input Voltage
-0.5 ~ Vcc + 0.5
V
Σ IOL
Output Current (total)
102
mA
Σ IOH
Output Current (total)
-120
mA
PD
Power Dissipation (Ta = 70°C)
600
mW
260
°C
T STG
Storage Temperature
-65 ~ 150
°C
T OPR
Operating Temperature
-20 ~ 70
°
T SOLDER
Soldering Temperature (10s)
C
4.2 DC Characteristics
Vcc = 5V ± 10%, Ta = -20 to 70°C (8 to 25MHz) (Typical values are for Ta = 25°C and Vcc = 5V unless otherwise noted)
Symbol
Parameter
Min
Max
Unit
V IL
Input Low Voltage (AD0-15)
-0.3
0.8
V
V IL1
P5, P7, P8, P9, PA, PB
-0.3
0.3Vcc
V
V IL2
RESET, NMI, INTO (PB7)
-0.3
0.25Vcc
V
V IL3
EA, AM8/16
-0.3
0.3
V
V IL4
X1
-0.3
0.2Vcc
V
V IH
Input High Voltage (D0 to 15)
2.2
Vcc + 0.3
V
V IH1
P5, P7, P8, P9, PA, PB
0.7Vcc
Vcc + 0.3
V
V IH2
RESET, NMI, INTO (PB7)
0.75Vcc
Vcc + 0.3
V
Vcc - 0.3
Vcc + 0.3
V
0.8Vcc
Vcc + 0.3
V
0.45
V
V IH3
EA, AM8/16
V IH4
X1
V OL
Output Low Voltage
V OH
Output High Voltage
Test Condition
I OL = 1.6mA
2.4
V
I OH = -400µA
V OH1
0.75Vcc
V
I OH = -100µA
V OH2
0.9Vcc
V
I OH = - 20µA
-3.5
mA
V EXT - 1.5V
R EXT = 1.1KΩ
µA
0.0 ≤ Vin ≤ Vcc
I DAR
Darlington Drive Current
(8 Output Pins max.)
-1.0
Input Leakage Current
0.02 (Typ)
±5
I LO
Output Leakage Current
0.05 (Typ)
±10
µA
0.2 ≤ Vin ≤ Vcc - 0.2
26 (Typ)
1.7 (Typ)
0.2 (Typ)
50
10
50
10
mA
mA
µA
µA
fc = 25MHz
I cc
Operating Current (RUN)
IDLE
STOP (Ta = -20 ~ 70°C)
STOP (Ta = 0 ~ 50°C)
V STOP
Power Down Voltage
(@STOP, RAM Back up)
2.0
6.0
V
R RST
RESET Pull Up Register
50
150
KΩ
10
pF
I LI
C IO
Pin Capacitance
V TH
Schmitt Width
RESET, NMI, INTO (PB7)
0.4
1.0 (Typ)
V
RK
Pull Down/Up Register
50
150
KΩ
Note:
162
0.2 ≤ Vin ≤ Vcc - 0.2
0.2 ≤ Vin ≤ Vcc - 0.2
V IL2 = 0.2Vcc,
V IH2 = 0.8Vcc
fc = 1MHz
I-DAR is guaranteed for a total of up to 8 ports.
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TMP95C061
4.3 AC Electrical Characteristics
Vcc = 5V±10%, Ta = -20 ~ 70°C (8MHz to 25MHz)
Variable
No.
Symbol
20MHz
25MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
40
125
50
40
ns
85
40
ns
1
tOSC
Osc. Period (= x)
2
tCLK
CLK width
3
tAK
A0 to 23 Valid→CLK Hold
0.5x - 20
11.0
0
ns
4
tKA
CLK Valid→A0 to 23 Hold
1.5x - 60
240
0
ns
2x - 40
5
tAC
A0 to 23 Valid→RD/WR fall
0.5x - 20
160
20
ns
6
tCA
RD/WR rise→A0 to 23 Hold
0.5x - 20
11.0
0
ns
7
tAD
A0 to 23 Valid→D0 - 15 input
3.0x - 35
140
105
ns
60
ns
8
tRD
RD fall →D0 - 15 input
9
tRR
RD Low width
10
tHR
RD rise→D0 to 15 Hold
11
tWW
WR Low width
2.5x - 40
85
60
ns
12
tDW
D0 to 15 Valid→WR rise
2.0x - 40
60
40
ns
13
tWD
WR rise→D0 to 15 Hold
0.5x - 10
15
10
ns
14
tAW
A0 to 23 Valid→ WAIT input (1WAIT + n mode)
15
tCW
WR Low width
16
tAPH
A0 to 23 Valid → PORT input
17
tAPH2
A0 to 23 Valid → PORT Hold
18
tCP
WR rise → PORT Valid
3.5x - 40
2.0x - 40
0
85
85
60
ns
0.0
0
ns
3.5x - 90
2.5x - 0
85
125
2.5x - 90
2.5x - 50
35
175
200
50
100
10
150
200
ns
ns
ns
ns
200
ns
AC Measuring Conditions
• Output Level:
High 2.2V
/Low 0.8V, CL50pF
(However, D0 to D15, A0 to A23, ALE, RD, WR, HWR, R/W, CLK, CS0 to CS3, CL = 100pF)
• Input Level:
High 2.4V
/Low 0.45V (D0 to D15)
High 0.8Vcc /Low 0.2Vcc (except for D0 to D15)
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(1) Read Cycle
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(2) Write Cycle
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4.4 DRAM Control AC Characteristics
Vcc = 5V±10% TA = -20 ~ 70°C (8MHz to 25MHz)
Variable
No.
Symbol
20MHz
25MHz
Parameter
Unit
Min
Max
Max
200
Min
Max
tRC
RAS cycle time
2
tRAC
RAS access time
3x -40
110
80
ns
3
tCAC
CAS access time
1.5x - 25
40
25
ns
4
tAA
Column address access time
2.5x - 35
70
45
ns
5
tOFF
Input data hold time
0
0
ns
6
tRP
RAS precharge time
1.5x - 10
65
50
ns
7
tRAS
RAS low pulse width
2.5x - 30
65
70
ns
8
tRSH
RAS hold time
1x - 15
65
25
ns
9
tCSH
CAS hold time
3x - 35
65
85
ns
10
tCAS
CAS low pulse width
1.5x - 15
65
45
ns
1.5x - 40
1
4x
Min
0
160
ns
11
tRCD
RAS - CAS delay time
12
tRAD
CAS column address delay time
0.5x - 5
1.5x
35
75
20
60
ns
0.5x - 20
20
45
15
40
ns
13
tCRP
RAS - CAS precharge time
1x - 35
15
5
ns
14
tCP
CAS precharge time
2.5x - 35
90
65
ns
15
tASR
Low address setup time
0.5x - 15
10
5
ns
16
tRAH
Low address hold time
0.5x - 5
20
15
ns
17
tASC
Column address setup time
1x - 25
25
15
ns
18
tCAH
Column address hold time
2x - 35
65
45
ns
19
tRAL
Column address RAS read time
2x - 30
70
50
ns
20
tCWL
Write command CAS read time
2.5x - 35
90
65
ns
21
tDS
Data output setup time
0.5x - 5
10
5
ns
22
tDH
Data output hold time
2x - 35
65
45
ns
23
tWCS
Write command setup time
1x - 30
20
10
ns
24
tCHR*1
CAS hold time
2x - 50
50
30
ns
25
tRPC*
RAS precharge CAS active time
1.5x - 30
45
30
ns
26
tCSR*
CAS setup time
0.5x - 10
15
10
ns
27
tRPS*2
RAS precharge time
6x - 50
250
190
ns
28
tCHS*2
CAS hold time
0
0
0
ns
29
tCFL
Refresh setup time
1x - 5
45
35
ns
30
tCFH
Refresh hold time
1x - 10
40
30
ns
*1 CAS before RAS interval refresh mode
*2 CAS before RAS self-refresh mode
* Both refresh modes
AC Measuring Conditions
• Output Level:
High 2.2V
/Low 0.8V, CL50pF
(However CL = 100pF for D0 to D15, A0 to A23, RD, WR, HWR, R/W RAS)
• Input Level:
High 2.4V
/Low 0.45V (AD0 ~ AD15)
High 0.8Vcc/Low 0.2Vcc (except for D0 to D15)
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(1) Read/Write Access Cycle
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(2) CAS Before RAS Interval Refresh Cycle
(3) CAS Before RAS Self-Refresh Cycle
168
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TMP95C061
4.5 A/D Conversion Characteristics
Vcc = 5V±10% TA = -20 ~ 70°C (8 to 25MHz)
Symbol
Parameter
Min
Typ
Max
VREF
Analog reference voltage
Vcc - 1.5
Vcc
Vcc
AGND
Analog reference voltage
Vss
Vss
Vss
VAIN
Analog input voltage range
Vss
IREF
Analog current for analog reference voltage
Error
4 ≤ fc ≤ 16MHz
(Quantize error of
±0.5 LSB not included)
16 ≤ fc ≤ 25MHz
Unit
V
Vcc
0.5
1.5
Slow mode
±1.5
±4.0
Fast mode
±3.0
±6.0
Slow mode
±1.5
±4.0
Fast mode
±4.0
±8.0
mA
LSB
4.6 Serial Channel Timing - I/O Interface Mode
Vcc = 5V±10% TA = -20 to 70°C (8 to 25MHz)
(1) SCLK Input Mode
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
16x
0.8
0.64
µs
tSCY/2 - 5x - 50
100
70
ns
SCLK rising edge→output data hold
5x - 100
150
100
ns
tHSR
SCLK rising edge→input data hold
0
tSRD
SCLK rising edge→effective data input
tSCY
SCLK cycle
tOSS
Output Data→rising edge of SCLK
tOHS
0
ns
450
340
ns
Vcc = 5V±10% TA = -20 to 70°C (8 to 25MHz)
(2) SCLK Output Mode
Variable
Symbol
0
tSCY - 5x - 100
16MHz
20MHz
Parameter
tSCY
SCLK cycle (programmable)
Unit
Min
Max
Min
Max
Min
Max
16x
8192x
0.8
512
0.64
409.6
µs
tOSS
Output Data→rising edge of SCLK
tSCY - 2x - 150
550
410
ns
tOHS
SCLK rising edge→output data hold
2x - 80
20
0
ns
tHSR
SCLK rising edge→input data hold
0
tSRD
SCLK rising edge→effective data input
0
0
tSCY - 2x - 150
ns
550
410
ns
4.7 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Vcc = 5V±10% TA = -20 to 70°C (8 to 25MHz)
Variable
Symbol
20MHz
25MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
500
420
ns
tVCKL
Low level clock pulse width
4x + 40
240
200
ns
tVCKH
High level clock pulse width
4x + 40
240
200
ns
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4.8 Interrupt Operation
Vcc = 5V±10% Ta = -20 to 70°C (8 to 25MHz)
Variable
Symbol
25MHz
Unit
Min
170
20MHz
Parameter
Max
Min
Max
Min
Max
tINTAL
NMI, INT0 Low level pulse width
4x
200
160
ns
tINTAH
NMI, INT0 High level pulse width
4x
200
160
ns
tINTBL
INT4 ~ INT7 Low level pulse width
8x + 100
500
420
ns
tINTBH
INT4 ~ INT7 High level pulse width
8x + 100
500
420
ns
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4.9 Timing Chart for I/O Interface Mode
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4.10 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK)
Variable
Symbol
25MHz
Unit
Min
Max
120
Min
Max
120
Min
Max
tBRC
BUSRQ setup time for CLK
tCBAL
CLK→BUSAK falling edge
1.5x + 120
220
200
ns
tCBAH
CLK→BUSAK rising edge
0.5x + 40
65
60
ns
tABA
Floating time to BUSAK fall
0
80
0
80
0
80
ns
tBAA
Floating time to BUSAK rise
0
80
0
80
0
80
ns
Note:
172
20MHz
Parameter
120
ns
The bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “wait” cycle.
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5.
Table of Special Function Registers
(SFRs)
(SFR; Special Function Register)
The special function registers (SFRs) include the I/O ports
and peripheral control registers allocated to the 128-byte
addresses from 000000H to 00007FH.
(1) I/O port
(2) I/O port control
(3) Timer control
(4) Pattern Generator control
(5) Watch Dog Timer control
(6) Serial Channel control
(7) A/D converter control
(8) Interrupt control
(9) Chip Select/Wait Control
(10) DRAM Control
Configuration of the table
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Table 5 I/O Register Address Map
174
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(1) I/O Port
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(2) I/O Port Control (1/2)
176
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(2) I/O Port Control (2/2)
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(3) Timer Control (1/3)
178
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(3) Timer Control (2/3)
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(3) Timer Control (3/3)
180
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(4) Pattern Generator
(5) Watch Dog Timer
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(6) Serial Channel
182
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(7) A/D Converter Control
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(8) Interrupt Control (1/2)
184
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(8) Interrupt Control (2/2)
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(9) Chip Select/Wait Control (1/2)
186
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(9) Chip Select/Wait Control (2/2)
(10) DRAM Control
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6. Port Section Equivalent Circuit Diagram
• Reading The Circuit Diagram
Basically, the gate symbols written are the same as
those used for the standard CMOS logic IC [74HCXX]
series.
The dedicated signal is described below.
STOP: This signal becomes active “1” when the hold
mode setting register is set to the STOP mode
(WDMOD <HALTM1,0> = 0,1) and the CPU
executes the HALT instruction. When the drive
enable bit [DRVE] is set to “1”, however, STP
remains at “0”.
• The input protection resistor ranges from several tens of
ohms to several hundreds of ohms.
• D0 to D7, P1 (D8 to 15)
• P2 (A16 to A23), A0 to A15, RD, WR, P6
• P52 52, P7, P81, P82. P84, P85, PA, PB6 ~ B0
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• P9 (AN0 to 3)
• P87 (INT0)
• P80 (TXD0), P83 (TXD1)
• NMI
• WDTOUT
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• CLK
• EA, AM8/16
• RESET
• X1, X2
• VREF (VREFH), AGND (VREFL)
190
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7. Care Points and Restriction
(2)
(1)
Care Points
Special Expression
➀ EA, pin, AM/16 pin
➀ Explanation of a built-in I/O register: Register
Fix these pins VCC or GND unless changing voltage.
Symbol
<Bit Symbol>
ex) TRUN <TRUN> . . . Bit T0RUN of Register TRUN
➁ Read, Modify and Write Instruction
An instruction which CPU executes following by one
instruction.
➁ Warming-up Counter
The warming-up counter operates when the STOP
mode. is released even the system which is used an
external oscillator. As a result, it takes warming up time
from inputting the releasing request to outputting the
system clock.
1. CPU reads data of the memory.
➂ Programmable Pull Up/Down Resistance
2. CPU modifies the data.
3. CPU writes the data to the same memory.
ex1) SET 3, (TRUN) . . . set bit3 of TRUN
ex2) INC1, (100H) . . . increment the data of 100H
• The representative Read, Modify and Write
Instruction in the TLCS-900
SET
imm, mem,
RES
imm, mem
CHG
imm, mem,
TSET
imm, mem
INC
imm, mem,
DEC
imm, mem
RLD
A, mem,
ADD
imm, reg
The programmable pull up/down resistors can be
selected ON/OFF by program when they are used as
the input ports. The case of they are used as the output ports, they cannot be selected ON/OFF by program.
➃ Bus Releasing Function
Refer to the “Note about the Bus Release” in 3.5 Functions of Ports because the pin state when the bus is
released is written.
➂ 1 state
➄ Watch Dog Timer
One cyclecycle clock divided by 2 oscillation frequency
is called 1 state.
The watch dog timer starts operation immediately after
the reset is released. When the watch dog timer is not
used, set watch dog timer to disable.
ex) Oscillation frequency is 25MHz.
2/25MHz = 80ns = 1 state
➅ CPU (HDMA)
Only the “LDC cr, r”, “LDC r, cr” instruction can be
used to access the control register like transfer source
address register (DMASn) in the CPU.
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Notes
192
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