ETC TMP90CM38F

TOSHIBA
TLCS-90 Series
TMP90CM38
CMOS 8–Bit Microcontroller
TMP90CM38F/TMP90CM38T
1. Outline and Characteristics
The TMP90CM38 is a high-speed, high performance 8-bit
microcontroller developed for application in the control of
various devices.
The TMP90CM38, CMOS 8-bit microcontroller, integrates an
8-bit CPU, ROM, RAM, A/D converter, D/A converter, multi-function timer/event counter, general-purpose serial interface, signal
measure circuit, timing pulse generation circuit and PWM output
in a single chip, and with which external program memory and
data memory can be extended up to 31KB.
The TMP90CM38F uses an 80-pin flat package.
The TMP90CM38T uses an 84-pin QF (PLCC) package.
(6)
(7)
(8)
(9)
(10)
The following are the features of TMP90CM38:
(1)
(2)
(3)
(4)
(5)
Highly efficient instruction set: 167 basic instructions
instructions, including
Division and multiplication instructions, 16-bit operation instructions and bit operation instructions
Minimum instruction executing time: 250ns (at 16MHz)
Built-in ROM:
32K bytes
Built-in RAM:
1K bytes
Memory extension capability
External program memory: 31K bytes
External data memory:
31K bytes
(11)
(12)
(13)
Interrupt functions:
13 internal, 5 external
8-bit A/D converter (8 channels)
8-bit D/A converter (2 channels)
General-purpose serial interface mode (2 channels)
• With asynchronous mode and I/O interface mode (1
channel)
• With synchronous mode (1 channel)
• I/O interface mode (1 channels)
Timer function
(1) 16-bit timer/event counter (1 channel)
----- Built-in 2 capture register and 2 comparator
(2) 8-bit timer (4 channels)
----- Built-in 1 comparator in each channel
(3) Watchdog timer function (WDTOUT pin having)
I/O ports:
Max. 66 pins
HDMA function (2 channels) ----- 1 byte transmission:
1.75µs (@16.0MHz)
Software standby function ----- RUN, STOP, IDLE
modes
Hardware standby function ----- STOP mode
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP90CM38
Figure 1. TMP90CM38 Block Diagram
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TMP90CM38
2. Pin Assignment and Functions
The assignment of input/output pins for TMP90CM38, their
name and outline functions are described below.
2.1 Pin Layout Diagram
Figure 2.1 (1) shows the pin assignment of TMP90CM38F.
Figure 2.1 (1). Pin Assignments (Flat Package)
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TMP90CM38
Figure 2.1 (2) shows the pin assignment of TMP90CM38T.
Figure 2.1 (2). Pin Assignments (QFJ (PLCC) Package)
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TMP90CM38
2.2 Pin Names and Functions
The names of input/output pins and their functions are described
below. Table 2.2 Shows the input/output pin names and functions.
Table 2.2. Pin Names and Functions (1/3)
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Table 2.2. Pin Names and Functions (2/3)
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TMP90CM38
Table 2.2. Pin Names and Functions (3/3)
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TMP90CM38
3. Operation
This section explains the functions and basic operations of the
TMP90CM38 in blocks.
3.1 CPU
The TMP90CM38F has a built-in, high performance 8 bit
CPU.
For the operation of the CPU, see the book TLCS 90
Series CPU Core Architecture.
This section explains the CPU functions unique to the
TMP90CM38 that are not explained in “that book.
3.1.1 Reset
Figure 3.1 (1) shows the basic timing of reset.
To reset TMP90CM38, it is required that the power supply
voltage is within operating range, the internal oscillator is stably functioning, and RESET input be kept at “0” for at least 10
system clocks (10 states: 2 microseconds with a 10MHz system clock)
When a reset is accepted, among I/O common ports, port 0
(address data bus A0 - A7), port 1 (address bus A8 - A15) and
port 2 are set to input status (with high impedance). Output
ports P30 (RD), P31 (WR), CLK, and WDTOUT (P80) are set to
“1” and ALE (P83) is cleared to “0”.
CPU registers and external memory are not changed.
However, program counter PC and interrupt enable/disable
flag IFF are cleared to “0”. The A register becomes undefined.
When the reset is released, instruction execution starts
from address 0000H.
Figure 3.1 (1). Reset Timing of TMP90CM38
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3.1.2 EXF (Exchange Flag)
The exchange flag EXF is inverted when the EXX instruction is
executed to exchange data between the TMP90CM38 main
registers and auxiliary registers. This flag is allocated to bit 7 at
memory address FFE1H.
3.1.3 Wait Control
For the TMP90CM38, a wait control register (WAITC) is assigned
to bits 4 and 5 at memory address FFB0H.
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TMP90CM38
3.2 Memory Map
The TMP90CM38 can provide a maximum 64K byte program
memory and data memory.
The program and data memories may be allocated to the
addresses 0000H ~ FFFFH.
(1)
(2)
The TMP90CM38 contains a 1K byte built-in RAM
which is allocated to the addresses FBA0H ~ FF9FH.
The CPU can also access some portions of the RAM (160
byte area FF00H ~ FF9FH) using short instruction codes in
the direct addressing mode.
Built-in ROM
The TMP90CM38 has an internal 32K byte ROM. This
ROM is located at addresses 0000H ~ 7FFFH. Program execution starts from address 000H after a reset
operation.
Addresses 0010H ~ 00C7H in the internal ROM area are
used as the interrupt processing entry area.
Built-in RAM
(3)
Built-in I/O
The TMP90CM38 uses 96 bytes of the address space
as a built-in I/O area. The area is allocated to the
addresses FFA0H ~ FFFFH. The CPU can access the
built-in I/O using short instruction codes in the direct
addressing mode.
Figure 3.2 shows the memory map and the access
ranges of the CPU for each addressing mode.
Figure 3.2. Memory Map
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3.3 Interrupt Functions
The TMP90CM38 has a general-purpose interrupt processing routine for responding to both internal and external interrupt request, and a high-speed micro DMA (HDMA)
processing mode in which the CPU automatically transfers
data.
Immediately after a reset is released, all responses to
interrupt requests are set to the general-purpose interrupt
processing mode.
The high-speed DMA processing mode can be set by
loading a vector value to the DMAV 0/1 register.
Figure 3.3 (1) shows the interrupt response flow.
Figure 3.3 (1). Interrupt Response Flow
When an interrupt request is generated, this is reported to
the CPU via the built-in interrupt controller. If the request is for
a non-maskable interrupt or an enabled maskable interrupt,
the CPU starts interrupt processing. If for a disabled maskable
interrupt, the request is ignored and not received.
If the interrupt is received, the CPU first reads the interrupt
vector from the built-in interrupt controller to determine the
source of the interrupt request.
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Next, a check is made as to whether this request is for
general-purpose interrupt processing, micro DMA processing or
high-speed DMA (HDMA) processing, and then the corresponding
processing is performed.
The interrupt vector is read in an internal operation cycle
so the bus cycle becomes a dummy cycle.
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3.3.1 General-Purpose Interrupt Processing
Figure 3.3 (2) shows the general-purpose interrupt processing
flow.
The CPU first saves the contents of the program counter
PC and register AF (including the interrupt enable/disable flag
IFF immediately before an interrupt) to the stack and then
resets the interrupt enable/disable flag IFF to “0” (interrupt
disable). Finally, the interrupt vector contents [V] are transferred to
the program counter and a jump is made to the interrupt
processing program.
There is a 20-state overhead from the time when the interrupt is
received until the jump is made to the interrupt processing program.
Figure 3.3 (2). General-Purpose Interrupt Processing Flow
Interrupt processing program is ended with the RETI
instruction for both maskable and non-maskable interrupts.
Executing this instruction restores the program counter
PC and register AF contents from the stack. (Resets the interrupt
enable/disable flag immediately before an interrupt.)
When the CPU reads the interrupt vector, the interrupt
request source confirms that the interrupt has been received
and then clears the interrupt request. Non-maskable interrupts
cannot be disabled by program. Maskable interrupts, however, can be enabled and disabled by program. Bit 5 of CPU reg-
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ister F is an interrupt enable/disable flipflop (IFF). Interrupts are
enabled by setting this bit to “1” with the EI (interrupt enable)
instruction and disabled by resetting this bit to “0” with the DI
(interrupt disable) instruction. IFF is reset to “0” by resetting
and when an interrupt is received (including non-maskable
interrupts).
The EI instruction is actually executed after the next
instruction is executed.
Table 3.3 (1) shows the interrupt sources.
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TMP90CM38
Table 3.3 (1) Interrupt Sources
The “priority sequence” shown in Table 3.3 (1) indicates the
sequence in which interrupt sources are received by the CPU
when multiple interrupt requests are generated simultaneously.
For example, if interrupt requests with the priority
sequences 4 and 5 are generated simultaneously, the CPU will
receive the interrupt request with priority sequence 4 first.
When processing of the interrupt with priority sequence 4 is
ended with the RETI instruction, the CPU will then receive the
interrupt with priority sequence 5.
If the interrupt processing program for the priority
sequence 4 interrupt is interrupted by executing the EI instruction,
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the CPU will receive the priority sequence 5 interrupt request.
When multiple interrupt requests are generated simultaneously, the
built-in interrupt controller only determines the priority
sequence of the interrupt sources received by the CPU. There
is no function to compare the priority sequence of the interrupt
currently being processed and the interrupt currently being
requested.
Another interrupt can be enabled while another interrupt is
being processed by resetting the interrupt enable/disable flag
IFF to enable.
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3.3.2 High-Speed Micro DMA Processing
The TMP90CM38 has two built-in DMA channels called
HDMA.
HDMA has three times the processing capacity of µDMA
and is used for high-speed data transfers. HDMA execution
time (decrease the value of transfer number and the value is
not “0” data) is 14 states, regardless of whether the 1-byte
transfer mode or 2-byte transfer mode is used. HDMA and
micro DMA (the TMP90CM38 has not the micro DMA) transfer
speeds.
Table 3.3 (4) shows the HDMA functions.
Table 3.3 (3) Transfer Speeds
Table 3.3 (4) Shows the DHMA Functions
(1)
HDMA Setting Registers
HDMA operation.
The following describes the registers required for
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Note:
(2)
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It is ineffective to set decrement for a destination address when a source
address being increment; and to set increment for a destination address when
a source address being decrement.
Register Loading
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TMP90CM38
(3)
HDMA Start
(4)
HDMA Channel 0 and Channel 1 Priority Sequence
HDMA can be started by any of the following
TMP90CM38 maskable interrupt sources
The channel where an interrupt is generated first has
priority
(a)
Note: HDMA, regardless of an interrupt enable flag,
compares the vector and the values of the DMA
V0/1 register. If they match in EI mode, the
HDMA starts.
Do not write the vector value of the nonmaskable interrupt to the DMA V0/1 register. If
doing so, the HDMA does not operate normally.
To stop the HDMA from being started, set DI
mode before generating the interrupt to start the
HDMA, or set the DMA V0/1 register to 00H.
Internal start factors
• Internal I/O interrupts
Assign starting of HDMA channel 0 or channel 1 to the
INT0 - INT3 external interrupts, connect any of the bits
of ports 0 - 8 (output mode) externally to INT0 - INT3
to genrate a start interrupt.
(b)
External start factors
• INT0 ~ 3 pin
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TMP90CM38
(5)
HDMA Operation Flow
Figure 3.3 (6). HDMA Operation Flow
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TMP90CM38
(6)
HDMA Operation Timing
Figure 3.3 (7a). HDMA Operation Timing
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Figure 3.3 (7b). HDMA Operation Timing
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3.3.3 Interrupt Controller
Figure 3.3 (9) shows an abbreviated interrupt circuit diagram.
The left half of this diagram shows the interrupt controller and
the right half shows the CPU interrupt request signal circuit
and hold release circuit.
The interrupt controller has an interrupt request flipflop
and interrupt enable/disable flag for each interrupt channel
(total: 18 channels), and a micro DMA enable/disable flag. The
interrupt request flip-flop latches interrupt requests that arrive
from the periphery. This flipflop is reset to “0” when there is a
reset, when the CPU receives an interrupt and reads the vector
of that interrupt channel, and when an instruction that clears
the interrupt request (writes “vector value/8” to memory
address FFE0H) for that channel is executed.
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LD (0FFE0H), 60H/8
For example, when LD (0FFE0H), 38H/8 is executed, the
interrupt request flipflop for the interrupt channel [INTT1] with
the vector value 38H is reset to “0” (to clear the flipflop, also
write to address FFC9H when the interrupt request flag is
assigned to FFE1H and FFE2H).
Table 3.3 (5) shows the “interrupt vector value/8” values.
The status of the interrupt request flipflop can be determined
by reading memory address FFC9H, FFCAH or FFCBH. “0”
means no interrupt request and “1” means an interrupt
request. Figure 3.3 (8) shows the bit layout when the interrupt
request flipflop is read.
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Table 3.3 (4) Interrupt Vector Value/8 Values
Figure 3.3 (5). Interrupt Request Flipflop Read (1/2)
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TMP90CM38
Figure 3.3 (6). Interrupt Request Flipflop Read (2/2)
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Figure 3.3 (7). Interrupt Controller Block
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TMP90CM38
The interrupt enable/disable flags for each interrupt request
channel are assigned to memory addresses FFE3H - FFE5H.
Interrupt
Common Terminal
INT0
P81
INT1
INT2
P53
Interrupts are enabled for a channel by setting the flag to “1”.
The flags are reset to “0” by reseting.
Mode
How to set
Level
INTE2 <EDGE> = 0
Rise edge
INTE2 <EDGE> = 1
Rise edge
T4MOD <CAPM1, 0> = 0, 0 or 0, 1 or 1, 1
Fall edge
T4MOD <CAPM1, 0> = 1, 0
P54
–
Rise edge
INT2
P56
–
Rise edge
For the pulse width for external interrupt, refer to “4.7
Interrupt Operation”.
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Be careful that the following five are exceptional circuits.
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INT0 Level mode
As the INT0 is not an edge type interrupt, the interrupt request flip-flop is cancelled, and thus an interrupt request from peripheral devices
passes through S input of the flip-flop to become Q output. When the mode is changed over (from edge type to level type), the previous
interrupt request flag will be cleared automatically.
When the mode is changed from level to edge, the interrupt request flag set in the level mode is not cleared. Thus, use the following
sequence to clear the interrupt request flag.
DI
SET 6, (0FFE5H): Switch the mode from level to edge
LD (0FFE0H), 05H: Clear interrupt request flag
EI
INTRX1, INTRX2
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The interrupt request flip-flop cannot be cleared only by reset operation or reading the serial channel receiving buffer, and cannot be
cleared by an instruction.
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TMP90CM38
Figure 3.3 (8). Interrupt Enable Flags
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Figure 3.3 (9). Interrupt Processing Flow Chart
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TMP90CM38
3.4 Standby Functions
When a HALT instruction is executed, TMP90CM38 enters the
RUN, IDLE1 or STOP mode according to the contents of the
halt mode setting register. The features are as follows:
(1)
Run:
Only the CPU halts, power consumption
remains unchanged.
(2)
IDLE:
Only the internal oscillators operate, while all
other internal circuits halt. Power consumption is 1/10 or less than that during normal
operation.
(3)
STOP: All internal circuits halt, including the internal
oscillator. Power consumption is extremely
reduced.
The HALT mode setting register WDMOD <HALTM1,0> is
assigned to bits 2 and 3 memory address FFECH in the built-in I/
O register area (all other bits are used to control other block functions). The RUN mode (“00”) is entered by reseting.
These HALT states can be released by requesting an
interrupt or resetting. Table 3.4 (2) shows how to release the
HALT state. If the CPU is in the EI state for non-maskable or
maskable interrupt, the interrupt will be acknowledged by the
CPU and the CPU starts interrupt processing. If the CPU is in
the DI state fro maskable interrupt, the CPU starts the execution from the instruction following HALT instruction, but the
interrupt request flag remains at “1”.
Even when HALT state is released by reset operation, the
state (including the built-in RAM) just before entering the
HALT can be retained. However, if HALT instruction has
already been executed in the built-in RAM, the RAM contents
may not be retained.
Figure 3.4 (1). HALT Mode Setting Register
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3.4.1 RUN Mode
Figure 3.4 (2) shows the timing for releasing the HALT state by
an interrupt during RUN mode. In the RUN mode, the system
clock inside MCU does not stop even after HALT instruction
has been executed; the CPU merely stops executing instructions. Accordingly, the CPU repeats dummy cycle until HALT
state, interrupt requests are sampled at the fall edge of CLK
signal.
Figure 3.4 (2). HALT Release Timing Using Interrupts in RUN Mode
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TMP90CM38
3.4.2 IDLE1 Mode
Figure 3.4 (3) shows the timing used for releasing the HALT mode
by interrupts in the IDLE1 mode.
In the IDLE1 mode, only the internal oscillator operates,
the system clock inside MCU stops and CLK signal is fixed to
“1”.
In the HALT state, interrupt requests are sampled asynchronously with the system clock but sampling is performed
synchronously with the system clock, whereas the HALT
release (restart of operation) is performed synchronously with
it.
Figure 3.4 (3). HALT Release Timing Using Interrupts in the IDLE1 Mode
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TMP90CM38
3.4.3 STOP Mode
Figure 3.4 (4) shows the timing of HALT release caused by
interrupts in STOP mode.
In the STOP mode, all interval circuits stop, including
internal oscillator. When the STOP mode is activated, all pins
except special ones are put in the high-impedance state, isolated from the internal operation of MCU. Table 3.4 (1) shows
the state of each pin in the STOP mode. However, if WDMOD
<DRVE> (drive enable: bit 0 of memory address FFECH) of th
built-in I/O register is set to “1”, the pre-halt state of the pins can
be retained. The register is cleared to “0” by reset operation.
When the CPU accepts an interrupt request, the internal
oscillator first restarts. However, to get the stabilized oscillation, the system clock starts its output after the time set by
warming up counter has passed. WDMOD <WARM> (warming up: bit 4 at memory address FFECH) is used to set up the
warming up time. Warming up is executed for 214 clock oscillation time when this bit is set to “0”, while 216 clock oscillation
time when set to “1”. This bit is cleared to “0” by reset operation.
Figure 3.4 (4). HALT Release Timing Using Interrupts in STOP Mode
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The internal oscillator can also be restarted by inputting
the RESET signal “0” to the CPU.
However, the warming up counter remains inactive in
order to make the CPU rapidly operate when the power is
turned on. Accordingly, wrong operation may occur due to
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unstable clocks immediately after the internal oscillator has
restarted. To release the HALT state by resetting in the STOP
mode, RESET signal must be kept at “0” for a sufficient period
of time.
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Table 3.4 (1) State of Pins in STOP Mode
IN/OUT
DRVE = 0
DRVE = 1
Input Mode
Output Mode
–
–
–
Output
P10 ~ P17
Input Mode
Output Mode
–
–
Input
Output
P20 ~ P23
Input Mode
Output Mode
–
–
Input
Output
P00 ~ P07
P30 ~ P31
Output Mode
–
Output
P32 ~ P33
Input Mode
Output Mode
–
–
Input
Output
P40 ~ P47
Input Mode
Output Mode
–
–
Input
Output
P56 ~ P57
Input Mode
Output Mode
–
–
Input
Output
P60 ~ P67
Input Mode
–
–
P70 ~ P77
Input Mode
Output Mode
–
–
Input
Output
NMI
CLK
X1
X2
EA
Input Mode
Output Mode
Input Mode
Output Mode
Input Mode
Input
–
–
“1”
Input
Input
–
–
“1”
Input
P80 (WDTOUT)
P81 (INT0)
P82 (STBY)
P83 (ALE)
Output Mode
Input Mode
Input Mode
Output Mode
–
Input
Input
–
Output
Input
Input
Output
P90 ~ P93
Input Mode
Output Mode
–
Output
Input
Output
P100, P101
Input Mode
Output Mode
–
–
Input
Output
–
Indicates that input mode/input pin cannot be used for input and
that the output mode/output pin have been set to high
impedance.
Input: Input is enabled.
Input: The input gate is operating. Fix the input voltage at either “0” or “1” to prevent the pin floating.
Ouput: Output status.
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Table 3.4 (2) I/O Operation Release in HALT Mode
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3.4.5 Hardware Standby Function
STBY input pin
This pin is used for setting MCU-standby mode. When
this pin is set “Low”, the oscillator stops and internal clock is
frozen. The power consumption is extremely reduced.
This function sets every pin to a condition as same as
STOP mode which a HALT instruction is executed.
Figure 3.4 (5) indicates the block diagram of standby
mode.
Figure 3.4 (5). Standby Mode Block Diagram
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3.5 Function of Ports
The TMP90CM38 contains total of 66 I/O port pins. These
port pins function not only as the general-purpose I/O ports
but also as the I/O ports for the internal CPU and built-in I/O.
Table 3.5 shows the functions of these port pins.
Table 3.5 Functions of Ports
These port pins function as the general-purpose I/O port
pins by resetting (except P30, P31, P60 ~ P67, P80 ~ P83). The
port pins, for which input or output is programmably selectable,
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function as input ports by resetting. A separate program is
required to use them for an internal function.
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3.5.1 Port 0 (P00 ~ P07)
Port 0 is the 8-bit general-purpose I/O port P0, each bit of
which can be set independently for input or output. The control register P0CR is used to set input or output. Reset operations clear all output latch and control register bits to “0” and
set port 0 to the input mode.
In addition to the general-purpose I/O port function, port 0
also functions as an address/data bus (AD0 ~ AD7). When the
external memory is accessed, port 0 automatically functions
as the address/data bus.
Figure 3.5 (1). Port 0 (P00 ~ P07)
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Figure 3.5 (2). Registers for Port 0
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3.5.2 Port 1 (P10 ~ P17)
Port 1 is the 8-bit general-purpose I/O port P1, each bit of
which can be set to input or output. The port 1 control register
P1CR is used to set input or output. Reset operations clear all
output latch and the control register bits to “0” and sets all port
1 bits to the input mode.
In addition to the general-purpose I/O port function, port 1
also functions as an address bus (A8 ~ A15). This is specified
by setting the external extended specification register
IRFL<EXT> to “1” and setting P1CR to the output mode.
When the P1CR cleared to “0”, port 1 is set to the input mode,
regardless of the external extended specification register
value. IRF2 <EXT> also controls P30 (RD) and P31 (WR), P80
(ALE).
Figure 3.5 (3). Port 1 (P10 ~ P17)
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Figure 3.5 (4). Registers for Port 1
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3.5.3 Port 2 (P20 ~ P27)
Port 2 is a 4-bit general-purpose I/O port, each bit of which can
be set to input or output. The control register P29CR <P23C ~
P20C> is used to set for input or output. By reset operation,
this control register is reset to “0”, and port 2 is placed in the
input mode.
This port can also be used as a stepping motor control/
pattern generation port 1 (M00 ~ M03). The function register
P29FR <M0S> specifies whether it is to be used as the general-purpose I/O port or stepping motor control/pattern generation port. When reset, it becomes a general-purpose I/O
port.
Figure 3.5 (5). Port 2
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3.5.4 Port 9 (P90 ~ P93)
Port 9 is a 4-bit general-purpose I/O port, each bit of which can
be set for input or output. The control register P29CR <P93C
~ P90C> is used to set for input or output. When reset, control
register will be cleared to “0”, placing the port 9 in the input
mode.
This port can also be used as a stepping motor control/
pattern generation port 1 (M10 ~ M13). The function register
P29FR <M1S> specifies whether it is to be used as the general-purpose I/O port or stepping motor control/pattern generation port. When reset, it becomes a general-purpose I/O port.
Figure 3.5 (6). Registers for Port 2
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Figure 3.5 (7). Registers for Port 2 and Port 9 (1/2)
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TMP90CM38
Figure 3.5 (8). Registers for Port 2 and Port 9 (2/2)
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3.5.5 Port 3 (P30 ~ P33)
P32, P33 are a 2-bit general-purpose I/O port. The control
register P38CR <P33C, P32C> is used for input or output.
P30, P31 are output ports. All bits of the output latch are
set to “1” by resetting, and “1” is generated to the output port.
Access of external memory makes P30, P31 function as the
memory control pins (RD and WR), when set IRF2 <EXT> to
“1”. When access of an internal memory makes them function, “1” is generated always.
Also function register P38CR <RDE> is intended fro a
pseudostatic RAM. When set IRF2 <EXT> to “1”, and set
P38CR <RDE> to “1”, it always functions as RD pin. Therefore, the RD pin outputs “0” (Enable) when it is an internal
memory read and internal I/O read cycle.
Figure 3.5 (9). Port 3 (P30, 31)
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Figure 3.5 (10). Port 3
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Figure 3.5 (11). Register for Port 3
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TMP90CM38
3.5.6 Port 4 (P40 ~ P47)
Port 4 is the 8-bit general-purpose I/O port, each bit of which
can be set for input or output. The control register P4CR is
used to set input or output.
All bits of the control register are cleared to “0” by resetting, and the port turns of input port mode (output latch is set
to “1” by resetting).
Figure 3.5 (12). Port 4
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TMP90CM38
Figure 3.5 (13). Register for Port 4
50
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TMP90CM38
3.5.7 Port 5 (P50 ~ P57)
Port 4 is the 8-bit general-purpose I/O port, each bit of which
can be set for input or output. The control register P5CR is
used to set input or output.
By reset operation, the output latch is set to “1” and the
control register is set to “0”, and port 5 is placed in the input
mode.
In addition to the general-purpose I/O port function, these
ports function as interrupt request input, clock input for timer
or event counter, or timer output, or wait input.
(1)
P55, P57, P51, P52
When specified by port 5 function register P5FR
<TO1S ~ TO5S>, these ports become the timer output.
Figure 3.5 (14). Port 5 (P55, P57, P51, P52)
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(2)
P56
as external interrupt request input (INT3).
P56 is also used as clock input (TI2) for 8-bit timer 0
Figure 3.5 (15). Port 5 (P56)
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(3)
P53, P54
timer or event counter as well as external interrupt
request input.
These ports are also used as the clock input for 16-bit
Figure 3.5 (16). Port 5 (P53, P54)
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(4)
P50
Figure 3.5 (17). Port (P50)
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Figure 3.5 (18). Registers for Port 5
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TMP90CM38
3.5.8 Port 6 (P60 - P67)
Port 6 is an 8-bit general-purpose input port with fixed input
function.
In addition to its general-purpose input port function,
these ports function as analog input pins (AN0 ~ AN7).
Figure 3.5 (19). Port 6 (P60 ~ P67)
Figure 3.5 (20). Registers for Port 6
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3.5.9 Port 7 (P70 ~ P77)
Port 7 is the 8-bit general-purpose I/O port, each bit of which
can be set for input or output. The control register P7CR is
used to set input or output. By reset operations, all bits of the
output latch are set to “0”, while all bits of control register are
to “0”, and port 7 is placed in the input mode. In addition to
the general-purpose I/O port function, port 7 have an internal
serial interface input/output function. This is specified by function register P7FR. All bits of the function register are cleared
to “0” by resetting, and the port turns to general-purpose I/O
mode.
Figure 3.5 (21). Port 7
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Figure 3.5 (22). Registers for Port 7
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Figure 3.5 (23). Registers for Port 7
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TMP90CM38
3.5.10 Port 8 (P80 - P83)
Port 8 is the 4-bit general-purpose I/O port, P81, P82 are
input-only ports. P80, P83 are output-only ports.
In addition to its general-purpose input port function, or
watch dog timer out output, these port function as external
interrupt request input, or hardware input, or ALE output.
(1)
P81/INT0
P81 is the general-purpose input port, is also used as
external interrupt request input (INT0). INT0 is to be
used as “H” level detection interrupt or rise edge
detection interrupt by control register INTE2 <EDGE>.
Figure 3.5 (24). Port 8 (P81)
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(2)
P80
P80 is used both as a general-purpose output port
and for WDTOUT output. Bit 1 of the watchdog timer
mode register (WDMOD: memory address FFECH)
and Bit 1 of the P38 control register (P38CR: memory
address FFA7H) is used to set P80 for WDTOUT output.
P80 is WDTOUT output after reset.
Figure 3.5 (25). Port 8 (P80)
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(3)
P82/STBY
P82 is a general purpose input port, and this port can
be used also as Hardware standby. By reset operations, the control register P38CR <STBYS> is “0”, and
P82 is placed in the general-purpose input port. When
the control register P38CR <STBYS> is “1”, and P82
is placed in the hardware standby input pin.
Figure 3.5 (26). Port 8 (P82)
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(4)
P83
P83 is output port, and is also used as ALE pin. When
P83 was 1 chip mode (EA = 1), by reset operations,
the control register P38CR <ALEE> is “0”, and P83 is
placed in the output port. When ALE pin uses, and
<ALEE> is set to “1”. When Multi chip mode was
<ALEE> is always “1”, and P83 becomes the ALE output.
Figure 3.5 (27). Port 8 (P83)
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TMP90CM38
Figure 3.5 (28). Registers for Port 8
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3.5.11 Port 10 (P100, 101)
All bits of the output latch are initialized to “0” by resetting,
and Port 10 turns to the input mode.
Port 10 is a 2-bit general-purpose I/O port. It is specified by
the control register P10CR in bit basis.
Figure 3.5 (29). Port 10 (P100, 101)
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Figure 3.5 (30). Register for Port 10
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TMP90CM38
3.6 Timers
The TMP90CM38 contains four 8-bit timers (timers 0, 1, 2 and
3), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timers.
The following four operating modes are provided for the 8bit timers.
• 8-bit interval timer mode (4 timers)
• 16-bit interval timer mode (2 timers)
• 8-bit programmable square wave pulse generation (PPG:
variable duty with variable cycle) output mode (2 timers)
• 8-bit pulse width modulation (PWM: variable duty with constant cycle) output mode (2 timers
one 16-bit timer).
Figure 3.6 (1) shows the block diagram of 8-bit timer
(timer 0 and timer 1).
8-bit timer (timer 2, 3) are connected to the external clock pin
TI2 in the timer 2 up counter input clock.
Other timer 2 and timer 3 have the same circuit configuration as timer 0 and timer 1. Each interval consists of an 8-bit
up-counter, 8-bit comparator, and 8-bit timer register. Besides,
one timer flip-flop (TFF1 or TFF3) is provided for each pair of
timer 0 and timer 1 as well as timer 2 and timer 3.
Among the input clock sources for the interval timers, the
internal clocks of øT1, øT4, øT16, and øT256 are obtained
from the 9-bit prescaler shown in Figure 3.6 (2).
The operation modes and timer flip-flops of the 8-bit timer
are controlled by five control registers T01MOD, T23MOD,
TFFCR, TRUN, and TRDC.
The upper two can be combined (two 8-bit timers and
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Figure 3.6 (1). Block Diagram of 8-bit Timers (Timers 0 and 1)
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➀ Prescaler
This 9-bit prescaler generates the clock input to the 8-bit
timers, 16-bit timer/event counters, and baud rate generators by further dividing the fundamental clock (fc) after it
has been divided by 4 (fc/4).
Among them, 8-bit timer uses 4 types of clock: øT1,
øT4, øT16, and øT256.
This prescaler can be run or stopped by the timer operation control register TRUN <PRRUN>. Counting starts
when <PRRUN> is set to “1”, while the prescaler is
cleared to zero and stops operation when <PRRUN>
is set to “0”. Resetting clears <PRRUN> to “0”, which
clears and stops the prescaler.
Figure 3.6 (2). Prescaler
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➁ Up-counter
This is an 8-bit binary counter that counts up the input
clock pulse specified by the timer 0/timer 1 mode register T01MOD and timer 2/timer 3 mode register
T23MOD.
The input clock pulse for timer 0 is selected from øT1
(8/fc), øT4 (32/fc) and øT16 (128/fc). Timer 2 input
clock is selected from external clock (TI2 pin = P55/
INT3) and same the timer 0 in three kinds internal
clock. According to the set value of T01MOD and
T23MOD.
The input clock of timer 1 and timer 3 differs depending on the operating mode. When set to 16-bit timer
mode, the overflow output of timer 0 and timer 2 is
used as the input clock.
When set to any other mode than 16-bit timer mode,
the input clock is selected from the internal clocks øT1
(8/fc), øT16 (128/fc), and øT256 (2048/fc) as well as
the comparator output (match detection signal) of
timer 0 and timer 2, according to the set value of
T01MOD and T23MOD.
Example:When TMOD <T01M1,0> = 01, the overflow
output of timer 0 becomes the input clock of
timer 1 (16-bit timer). When TMOD <T01M1,0> =
00 and T01MOD <T1CLK1,0> = 01, øT1 (8/fc)
becomes the input of timer 1.
Operation mode is also set by T01MOD and
T23MOD. When reset, it is initialized to
The counting, halt, and clear of up-counter can be
controlled for each interval timer by the timer operation
control register TRUN. When reset, all up-counters will
be cleared to stop the timers.
➂ Timer registers
This is an 8-bit register for setting an interval time.
When the set value of timer register TREG0, TREG1,
TREG2, and TREG3 matches the value of up-counter,
the comparator match detect signal becomes active. If
the set value is 00H, this signal becomes active when
the up-counter overflows.
Timer registers TREG0 and TREG2 are of double
buffer structure, each of which makes a pair with register buffer.
The TREG0 and TREG2 control whether the double
buffer should be enabled or disabled through the timer
register double buffer control register TRDC <TR0DE,
TR2DE>. It is disabled when <TR0DE>/<TR2DE> = 0,
and enabled when they are set to 1.
The timing to transfer data from the register buffer to
the timer register in the double buffer enable state is
the moment 2n - 1 overflow occurs in PWM mode or
the moment compare cycles will be equal in PPG
mode.
When reset, it will be initialized to <TR0DE, TR2DE> =
0 to disable the double buffer. To use the double
buffer, write data in the timer register, set <TR0DE>
and <TR2DE> to 1, and write the following data in the
register buffer.
T01MOD <T01M1, 0> = 00 and T23MOD <T23M1,
0> = 00, whereby the up-counter is placed in the 8-bit
timer mode.
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Figure 3.6 (3). Configuation of Timer Registers 0 and 2
Note: Timer register and the register buffer are allocated to the same memory address. When
<TR0DE>/<TR2DE> = 0, the same value written in the register buffer as well as the timer
register, while when <TR0DE>/<TR2DE> = 1
only the register buffer is written.
The memory address of each timer register is as follows.
TREG0: FFC6H
TREG1: FFC7H
TREG2: FFC8H
TREG3: FFC9H
All the registers are write-only and cannot be read.
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Figure 3.6 (4). Timer 0/Timer 1 Mode Register (T01MOD)
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Figure 3.6 (5). Timer 2/Timer 3 Mode Register (T23MOD)
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Figure 3.6 (6). 8-Bit Timer Flip-flop Control Register (TFFCR)
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Figure 3.6 (7). Timer Operation Control Register (TRUN)
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Figure 3.6 (8). Timer Register Double Buffer Control Register (TRDC)
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➃ Comparator
The operation of 8-bit timers will be described below:
A comparator compares the value in the up-counter
with the values to which the timer register is set. When
they match, the up-counter is cleared to zero and an
interrupt signal (INTT0 ~ INTT3) is generated. If the
timer flip-flop inversion is enabled, the timer flip-flop is
inverted at the same time.
(1)
8-bit timer mode
Four interval timers 0, 1, 2, and 3 can be used independently as an 8-bit interval timers. All interval timers
operate in the same manner, thus only the operation of
timer 1 will be explained below.
➄ Timer flip-flop (timer F/F)
➀ Generating interrupts in a fixed cycle
The status of the timer flip-flop is inverted by the match
detect signal (comparator output) of each interval timer
and the value can be output to the timer output pins TO1
(also used as P55) and TO3 (also used as P57).
A timer F/F is provided for each pair of timer 0 and timer 1
as well as that of timer 2 and timer 3 and is called TFF1
and TFF3. TFF1 is output to TO1 pin, while TFF3 is output
to TO3 pin.
To generate timer 1 interrupt at constant intervals
using using timer 1 (INTT1), first stop timer 1 then set
the operation mode, input clock, and synchronization
to T01MOD and TREG1, respectively. Then, enable
interrupt INTT1 and start the counting of timer 1.
Example: To generate timer 1 interrupt every 40
microseconds at fc = 16MHz, set each register in the following manner.
Use the following table for selecting the input clock:
Table 3.6 (1) 8-bit Timer Interrupt Cycle and Input Clock
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Interrupt cycle
(at fc = 16MHz)
Resolution
0.5µs ~ 128ms
0.5µs
øT1 (8/fc)
2µs ~ 512ms
2µs
øT16 (32/fc)
8µs ~ 2.048ms
8µs
øT256 (128/fc)
128µs ~ 32.768ms
128µs
øT256 (2048/fc)
Input clock
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➁ Generating a 50% duty square wave pulse
The timer flip-flop is inverted at constant intervals, and
its status is output to timer output pin (TO1).
Example: To output a 3.0µs square wave pulse from
TO1 pin at fc = 16MHz, set each register in
the following procedures. Either timer 0 or
timer 1 may be used, but this example uses
timer 1.
Figure 3.6 (9). Square Wave (50% Duty) Output Timing Chart
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➂ Making timer 1 count up by match signal from timer 0
comparator
Set the 8-bit timer mode, and set the comparator output
of timer 0 as the input clock to timer 1.
Figure 3.6 (10)
➃ Output inversion with software
The value of timer flip-flop (timer F/F) can be inverted,
independent of the timer operation.
Writing “00” to TFFCR <FF1C1, 0> inverts the value of
TFF1, and writing “00” into TFFCR <FF3C1,0> inverts
TFF3.
➄ Initial setting of timer flip-flop (timer F/F)
The value of timer F/F can be initialized to “0” or “1”,
independent of timer operation.
For example, write “10” in TFFCR <FF1C1,0> to
clear TFF1 to “0”, while write “01” in TFFCR
<FF3C1,0> to set TFF1 to “1”.
(2)
16-bit timer mode
A 16-bit interval timer is configured by using the pair of
timer 0 and timer 1 or that of timer 2 and timer 3.
As the above two pairs operate in the same manner,
only the case of combining timer 0/timer 1 is discussed.
To make a a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 0/timer 1 mode register T01MOD <T01M1,0> to “0,1”.
When set in 16-bit timer mode, the overflow output of
timer 0 will become the input clock of timer 1, regardless of the set value of T01MOD <T1CLK1,0>. Table
3.6 (2) shows the relation between the cycle of timer
(interrupt) and the selection of input clock.
Note: The value of timer F/F and timer register cannot
be read.
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Table 3.6 (2) 16-bit Timer (Interrupt) Cycle and Input Clock
Interrupt cycle
(at fc = 16MHz)
Resolution
0.5µs ~ 32.768ms
0.5µs
øT1 (8/fc)
2µs ~ 131.072ms
2µs
øT16 (32/fc)
8µs ~ 524.288ms
8µs
øT256 (128/fc)
The lower 8 bits of the timer (interrupt) cycle are set by
the timer register TREG0, and the upper 8 bits are set
by TREG1. Note that TREG0 always must be set first.
(Writing data into TREG0 disables the comparator
temporarily, and the comparator is restarted by writing
data into TREG1.)
Setting example: To generate interrupt INTT1 every
0.5 seconds at fc = 16MHz, set the
following values for timer registers
TREG0 and TREG1.
When counting by using øT16
(8µs @16MHz),
0.5s ÷ 8µs = 62500 =
F424H
Therefore, set TREG1 = F4H and
TREG0 = 24H, respectively.
80
Input clock
The comparator match signal is output from timer 0 each
time the up-counter matches UC0, where the up-counter UC0
is not cleared.
With the timer 1 comparator, the match detect signal is
output at each comparator timing when up-counter UC1 and
TREG1 values match. When the match detect signal is output
simultaneously from both comparators of timer 0 and timer 1,
the up-counters UC0 and UC1 are cleared to “0”, and the
interrupt INTT1 is generated. If inversion is enabled, the value
of the timer flip-flop TFF1 is inverted.
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TMP90CM38
Example: When TREG1 = 04H and TREG0 = 80H
Figure 3.6 (11)
(3)
8-bit PPG (Programmable Pulse Generation) Mode
Square wave pulse can be generated at any frequency
and duty by timer 0 or timer 2. The output pulse may
As an example, the case of timer 0 will be explained
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be either low-active or high-active.
In this mode, timer 1 and timer 3 cannot be used.
Timer 0 outputs pulse to TO1 pin, (also used as P55),
and timer 2 outputs to TO3 pin (also used as P57).
below. (Timer 2 also functions in the same way).
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In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit upcounter (UC0) matches the timer registers TREG0 and
TREG1.
However, it is required that the set value of TREG0 is
smaller than that of TREG1.
Though the up-counter (UC1) of timer 1 cannot be
used in this mode, timer 1 can be used for counting by
setting TRUN <T1RUN> to “1”.
Figure 3.6 (12) shows the block diagram for this mode.
Figure 3.6 (12). Block Diagram of 8-bit PPG Mode
When the double buffer of TREG0 is enabled in this
mode, the value of register buffer will be shifted in
TREG0 each time TREG1 matches UC0.
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Use of the double buffer makes easy the handling of
low duty waves (when duty is varied).
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TMP90CM38
Example: Generating 1/4 duty 50KHz pulse (@fc =
16MHz)
• Calculate the value to be set for timer register
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To obtain the frequency 50KHz, the pulse cycle t
should be: 1/50KHz = 20µs.
Given øT1 = 0.5µs (@ 16MHz)
20µs ÷ 0.5µs = 40
Consequently, to set the timer register 1 (TREG1) to
TREG1 = 40 = 28H and the duty to 1/4, t x 1/4 = 20µs
x 1/4 5µs
5µs ÷ 0.5µs = 10
Therefore, set timer register 0 (TREG0) to TREG0 = 10
= 0AH.
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(4)
8-bit PWM (Pulse Width Modulation) Mode
This mode is valid only for timer 0 and timer 2. In this
mode, maximum two PWMs of 8-bit resolution
(PWM0 and PWM2) can be output.
PWM pulse is output to TO1 pin (also used as P55)
when using timer 0, and to TO3 pin (also used as P57)
when using timer 2.
Timer 1 and timer 3 can also be used as 8-bit timer.
As an example, the case of timer 0 will be explained
below. (Timer 2 also operates in the same way.)
Timer output is inverted when up-counter (UC0)
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matches the set value of timer register TREG0 or when
2n - (n = 6, 7, or 8; specified by T01MOD
<PWM0,10>) counter overflow occurs. Up-counter
UC0 is cleared when 2n - 1 counter overflow occurs.
For example, when n = 6, 6-bit PWM will be output,
while when n = 7, 7-bit PWM will be output.
To use this PWM mode, the following conditions must
be satisfied.
(Set value of timer register) < (Set value of 2n - 1 counter
overflow)
(Set value of timer register) ≠ 0
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TMP90CM38
Figure 3.6 (13) shows the block diagram of this mode.
Figure 3.6 (13). Block Diagram of 8-bit PWM Mode
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In this mode, the value of register buffer will be shifted
in TREG0 2n - 1 overflow is detected when the double
buffer of TREG0 is enabled.
86
Use of the double buffer makes easy the handling of
small duty waves.
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TMP90CM38
Table 3.6 (3) PWM Cycle and the Setting of 2n - 1 Counter
PWM cycle (@ fc = 16MHz)
Formula
øT4 (32/fc)
øT16 (128/fc)
26 - 1
(26 - 1) x øTn
31.5µs
126µs
504µs
7-1
(27 - 1) x øTn
63.5µs
254µs
1.01ms
8-1
(28 - 1) x øTn
127µs
510µs
2.04ms
2
2
(5)
øT1 (8/fc)
Table 3.6 (4) shows the list of 8-bit timer modes.
Table 3.6 (4) Timer Mode Setting Registers
Register name
T01MOD (T23MOD)
TFFCR
Name of bit in register
T01M
(T32M)
PWM1
(PWM3)
T1CLK
(T3CLK)
T0CLK
(T2CLK)
FF1IS
(FF3IS)
Function
Timer Mode
PWM cycle
Upper timer input
clock
Lower timer
Input clock
Timer F/F invert
signal select
01
–
–
External clock
øT1, øT16, øT256
(01, 10, 11)
–
External clock
øT1, øT16, øT256
(01, 01, 10, 11)
0: Lower timer
output
1: Upper timer
output
16-bit timer mode
8-bit timer x 2 channels
00
–
Lower timer match
øT1, øT16, øT256
(01, 01, 10, 11)
8-bit PPG x 1 channel
10
–
–
External clock
øT1, øT16, øT256
(01, 01, 10, 11)
–
8-bit PWM x 1 channel
11
26 - 1, 27 - 1, 28 - 1
(01, 10, 11)
–
External clock
øT1, øT16, øT256
(01, 01, 10, 11)
–
8-bit timer x 1 channel
11
–
øT1, øT14, øT16
(01, 10, 11)
–
Output disabled
(Note) –: Don’t care
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• Lower timer external input clock has T2CLK. But it does not have T0CLK.
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3.7 Multi-Function 16-bit Timer/Event Counter (Timer 4)
The TMP90CM38 contains one multifunctional 16-bit timer/
event counter with the following operation modes:
• Frequency measurement
• Pulse width measurement
• Time differential measurement
• 16-bit timer
• 16-bit event counter
• 16-bit programmable pulse generation (PPG)
Figure 3.7 (1) shows the block diagram of 16-bit timer/
event counter.
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TMP90CM38
Figure 3.7 (1). Block Diagram of 16-Bit Timer/Event Counter (Timer 4)
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TMP90CM38
Timer/event counter con sists of 16-bit up-counter, two 16bit timer registers, two 16-bit capture registers, two comparators, register buffer, capture input controller, a timer flip-flop
and the control circuit.
Timer/event counter is controlled by 4 control registers:
T4MOD, T4FFCR, TRUN, and TRDC. TRUN register includes
8-bit timer controller. For TRUN and TRDC registers, see Figure 3.6 (7) and Figure 3.6 (8).
Figure 3.7 (2). 16-Bit Timer/Event Counter (Timer 4) Control/Mode Register (1/2)
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Figure 3.7 (2). 16-Bit Timer/Event Counter (Timer 4) Control/Mode Register (2/2)
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Figure 3.7 (3). 16-Bit Timer/Event Counter Timer Flip-flop Control Register
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➀ Up-counter (UC16)
UC16 is a 16-bit binary counter which counts up
according to the input clock specified by T4MOD
<T4CLK1,0> register.
As the input clock, one of the internal clocks øT1 (8/
fc), øT4 (32/fc), and øTI6 (128/fc) from 9-bit prescaler
(also used as 8-bit timer), and external clock from TI4
pin (commonly used as P46/INT1 pin) can be selected.
When reset, it will be initialized to <T4CLK1,0> = 00 to
select TI4 input mode. Counting, stop, or clearing of
the counter in controlled by timer operation control
register TRUN <T4RUN>.
When clearing is enabled, up-counter UC16 will be
cleared to zero each time it coincides matches the
timer register TREG5. The “clear enable/disable” is set
TREG4 timer register is of double buffer structure,
which is paired with register buffer. TREG4 controls
whether the double buffer should be enabled or disabled, using the timer register double buffer control
register TRDC <TR4DE>; disable when <TR4DE> = 0,
while enable when <TR4DE> = 1.
When the double buffer is enabled, the timing to transfer data from the register buffer to the timer register is
at the match between the up-counter and TREG5.
When reset, it will be initialized to <TR4DE> = 0,
whereby the double buffer is disabled. To use the double buffer, write data in the register buffer.
TREG4 and register buffer 4 are allocated to the same
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by T4MOD <CLE>.
If clearing is disabled, the counter operates as a freerunning counter.
➁ Timer registers (TREG4 and TREG5)
These two 16-bit registers are used to set the value of
the counter. When the value of up-counter UC16
matches the set value of this timer register, the comparator match detect signal will become active.
Setting data for timer register (TREG4 and TREG5) is
executed using 16-bit transfer instruction od using 8bit transfer instruction twice for lower 8 bits and upper
8 bits in order.
memory addresses FFCFH and FFD0H. When
<TR4DE> = 1, the value is written into only the register
buffer.
➂ Capture register (CAP1 and CAP2)
These 16-bit registers are used to hold the values of
the up-counter UC16.
Data in the capture registers should be read by a 2byte data load instruction or two 1-byte data load
instruction, from the lower 8 bits followed by the upper
8 bits.
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TMP90CM38
➃
Capture input control circuit
➄ Comparators (CP4, CP5)
This circuit controls the timing to latch the value of upcounter UC16 into CAP1 and CAP2. The latch timing
of capture register is controlled by register T4MOD
<CAPM1,0>.
These are 16-bit comparators which compare the upcounter UC16 value with the set value of TREG4 or
TREG5 to detect the match. When a match is
detected, the comparators generate an interrupt
INTT4 and INTT5, respectively. The up-counter UC16
is cleared only when UC16 matches TREG5. (The
clearing of up-counter UC16 can be disabled by setting T4MOD <CLE> = 0.)
• When T4MOD <CAPM1, 0> = 00
Capture function is disabled. Disable is the default on
reset.
• When T4MOD <CAPM1, 0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin
(commonly used as P53/INT1) input, while data is
loaded to CAP2 at the rise edge of TI5 pin (commonly
used as P47/INT2) input. (Time difference measurement)
• When T4MOD <CAPM1, 0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin
input, while to CAP2 at the fall edge. Only in this setting, interrupt INT1 occurs at fall edge. (Pulse width
measurement)
• When T4MOD <CAP1, 0> = 11
Data is loaded to CAP1 at the rise edge of timer flipflop TFF1, while to CAP2 at the fall edge. (Frequency
measurement)
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAPIN>, the current value of up-counter
will be loaded to capture register CAP1. It is necessary
to keep the prescaler in RUN mode (TRUN <PRRUN>
to be “1”).
94
➅ Timer flip-flop (TFF4)
This flip-flop is inverted by the match detect signal
from the comparators (CP4 and CP5) and the latch
signals to the capture registers (CAP1 and CAP2). Disable/enable of inversion can be set for each element
by T4FFCR <CAP2T4, CAP1T4, EQ5T4, EQ4T4>.
TFF4 will be inverted when “00” is written in T4FFCR
<TFF4C1,0>. Also, it is set to “1” when “10” is written,
and cleared to “0” when “10” is written. The value of
TFF4 can be output to the timer output pin TO4 (commonly used as P51).
➆ Timer flip-flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator CP5 and the latch signal to the
capture register CAP2. TFF5 will be inverted when
“00” is written in T4FFCR <TFF5C1,0>. Also, it is set
to “1” when “10” is written, and cleared to “0” when
“10” is written. The value of TFF5 can be output to the
timer output pin TO5 (commonly used as P52).
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TMP90CM38
(1)
16-bit Timer Mode
ister TREG5 to generate the interrupt INTT5.
In this example, the interval time is set in the timer reg-
(2)
16-bit Event Counter Mode
In timer mode as described in above (1), the timer can be
used as an event counter by selecting the external clock
(TI4 pin input) as the input clock. To read the value of
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the counter, first perform “software capture” once and
read the captured value.
The counter counts at the rising edge of TI4 pin input.
TI4 pin can also be used as P53/INT1.
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(3)
16-bit Programmable Pulse Generation (PPG) Mode
The PPG mode is entered by inversion of the timer flipflop TFF4 that is to be enabled bu the match of the up-
When the double buffer of TREG4 is enabled in this
mode, the value of register buffer 4 will be shifted in
TREG4 at match with TREG5. This feature makes
easy the handling of low duty waves (when duty rate is
varied).
(4)
Application examples of capture function
The loading of up-counter (UC16) vaules into the capture registers CAP1 and CAP2, the timer flip-flop TFF4
inversion due to the match detection by comparators
CP4 and CP5, and the output of the TFF4 status to
TO4 pin can be enabled or disabled. Combined with
interrupt function, they can be applied in many ways,
for example.
➀ One-shot pulse output by using external trigger
pulse
➁ Frequency measurement
➂ Pulse width measurement
➃ Time difference measurement
96
counter UC16 with the timer register TREG4 or 5 and
to be output to TO4 (also used as P51). In this mode,
the following conditions must be satisfied.
➀ One-shot pulse output from the rising edge of external trigger pulse.
Set the up-counter UC16 in free-running mode with the
internal input clock, input the external trigger pulse
from TI4 pin, and load the value of up-counter into capture register CAP1 at the rise edge of the TI4 pin. Then
set to T4MOD <CAPM1,0> = 01.
When the interrupt INT1 is generated at the rise edge
of TI4 pin, set the CAP1 value (c) plus a delay time (d)
to TREG4 (= c + d), and set the above set value (c + d)
plus a one-shot pulse width (p) to TREG5 (= c + + d +
p). When the interrupt INT1 occurs the T4FFCR register should be set that the TFF4 inversion is enabled
only when the up-counter value matches TREG4 or 5.
When interrupt INTT5 occurs, this inversion will be disabled.
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Figure 3.7 (4). One-Shot Pulse Output (with Delay)
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TMP90CM38
When delay time is unnecessary, invert timer flip-flop
TFF4 when the up-counter value is loaded into loaded
into capture register 1 (CAP1), and set the CAP1 value
(c) plus the one-shot pulse width (p) to TREG5 when
the interrupt INT1 occurs. The TFF4 inversion should
be enabled when the up-counter (UC16) value
matches TREG5, and disabled when generating the
interrupt INTT5.
Figure 3.7 (5). One-Shot Pulse Output (without Delay)
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TMP90CM38
➁ Frequency measurement
The frequency of the external clock can be measured in
this mode. The clock is input through the TI4 pin, and
its frequency is measured by the 8-bit timers (Timer 0
and Timer 1) and the 16-bit timer/event counter (Timer
4).
The TI4 pin input should be selected for the input clock
of Timer 4. The value of the up-counter is loaded into
the capture register CAP1 at the rise edge of the timer
flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and
CAP2 at its fall edge.
The frequency is is calculated by the difference
between the loaded values in CAP1 and CAP2 when
the interrupt (INTT0 or INTT1) is generated by either 8bit timer.
Figure 3.7 (6). Frequency Measurement
For example, if the value for the level “1” width of TFF1
of the 8-bit timer is set to 0.5 sec. and the difference
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between CAP1 and CAP2 is 100, the frequency will be
100/0.5 [sec.] = 200[Hz].
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TMP90CM38
➂ Pulse width measurement
This mode allows to measure the “H” level width of an
external pulse. While keeping the 16-bit timer/event
counter counting (free-running) with the internal clock
input, the external pulse is input though the TI4. Then
the capture function is used to load the UC16 values
into CAP1 and CAP2 at the rising edge and falling
edge of the external trigger pulse, respectively. The
interrupt INT1 occurs at the falling edge of TI4.
The pulse width is obtained from the difference between
the values of CAP1 and CAP2 and the internal clock cycle.
For example, if the internal clock is 0.8 microseconds
and the difference between CAP1 and CAP2 is 100,
the pulse width will be 100 x 0.8 = 80 microseconds.
Figure 3.7 (7). Pulse Width Measurement
Note:
100
Only in this pulse width measuring mode (T4MOD <CAPM1, 0> =
10), external interrupt INT1 occurs at the falling edge of TI4 pin input. In
other modes, it occurs at the rising edge.
The width of “L” level can be measured from the difference between the first C2 and the second C1 at the
second INT1 interrupt.
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➃ Time difference measurement
This mode is used to measure the difference in time
between the rising edges of external pulses input
through TI4 and TI5.
Keep the 16-bit timer/event counter (Timer 4) counting
(free-running) with the internal clock, and load the
UC16 value into CAP1 at the rising edge of the input
pulse to TI4. Then the interrupt INT1 is generated.
Similarly, the UC16 value is loaded into CAP2 at the rising
edge of the input pulse to TI5, generating the interrupt
INT2.
The time difference between these pulses can be
obtained from the difference between the time counts
at which loading the up-counter value into CAP1 and
CAP2 has been done.
Figure 3.7 (8). Time Difference Measurement
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3.8 Stepping Motor Control/Pattern Generation Ports
(P2 and P9)
TMP90CM38 contains 2 channels (M0 and M1) of 4-bit hardware stepping motor control/pattern generation ports (herein
after called SMC) which actuate in synchronization with the (8bit/16-bit) timers. The SMC’s ports (M0 and M1) are shared by
4-bit I/O ports P2 and P9.
Channel 0 (M0) is synchronous with 8-bit timer 0 or timer
1, and channel 1 (M1) is synchronous with 8-bit timer 2 or
timer 3 or 16-bit timer 4, to update the output.
The SMC ports are controlled by three control registers
P29CR, P29FR, and TRDC, and can select either stepping
motor control mode or pattern generation mode.
write mode or 4-bit write mode. In 4-bit write mode,
writing the SMC is executed only on the 4-bit shift
alternate register, and SMC functions as a pattern
generation port.
To use SMC as a stepping motor control port, select
the method of excitation and the method to control the
direction of rotation by P29FR <M0M>/<M1M> and
P29FR <CCW0>/<CCW1>, respectively.
(3)
With TRDC <M1T>, select a time which synchronizes
SMC channel 1 (M1). When <M1T> = 0, M1 is synchronous with timer 2 or timer 3, while when <M1T>
= 1 it is synchronous with timer 4.
3.8.1 Control Registers
(1)
Ports 2 and 9 I/O Selection Register (P29CR)
(4)
This register specifies either input or output for each
bit of the 4-bit I/O ports 6 and 7. When reset, all bits of
P29CR are cleared to “0”, so that port 2 and port 9
function as input ports. To use port 6 and port 7 as
SMC, set all bits of P29CR to “1”, specifying them as
output pins.
P29CR is a write-only register and so cannot be read.
Port 9
Port 2 and 9 function control register (P29FR)
This register is used for setting port 2 and port 9 as
SMC. To use port 2 and port 9 as SMC, set P29FR
<M0S>/<M1S> to “1”.
With P29 <PAT0>/<PAT1>, set SMC in either 8-bit
102
Port 2
This is a 4-bit I/O port allocated to address FFA4.
The lower 4 bits are assigned as port 6, while the
upper 4 bits function as the shifter alternate register
SA6 which is used in pattern generation mode or to
drive the stepping motor by 1-2 excitation.
(5)
(2)
Selecting the channel 1 synchronizing time (TRDC)
This is a 4-bit I/O port allocated to address FFB3.
The lower 4 bits are assigned as port 7, while the
upper 4 bits function as the shifter alternate register
SA7 which is used in pattern generation mode or to
drive the stepping motor by 1-2 excitation.
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Figure 3.8 (1). Port 2 and Port 9 I/O Selection Register (P29CR)
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Figure 3.8 (2a). Port 2 and Port 9 Function Control Register (P29FR)
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Figure 3.8 (2b). Port 2 and 9 Function Control Register (P29FR)
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Figure 3.8 (3). Timer Register Double Buffer Control Register (TRDC)
Figure 3.8 (4). Port 2 and Port 9
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3.8.2 Pattern Generation Mode
SMC functions as a pattern generation port according to the
setting of P29FR <PAT1>/<PAT0>. In this mode, becuase writing from CPU is executed only on the shifter alternate register,
writing ports 2 and 9 can be done during the interrupt opera-
tion of the timer for shift trigger and a pattern can be output,
synchronous with the timer .
In this mode, P29FR <M1M>/<M0M> must be always set
to “1”.
Figure 3.8 (5) shows the block diagram of this mode.
Figure 3.8 (5). Pattern Generation Mode Block Diagram (Port 2)
In this pattern generation mode, only writing the output
latch is disabled by hardware, but other functions do the same
operation as 1-2 excitation in stepping motor control port
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mode. Accordingly, the data shifted by trigger signal from a
timer must be written before the next trigger signal is output.
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3.8.3 Stepping Motor Control Mode
(1)
4-Phase 1-Step/2-Step Excitation
Figure 3.8 (6) and Figure 3.8 (7) show the output
waveforms of 4-phase 1 excitation and 4-phase 2
excitation, respectively when channel 0 is selected.
Figure 3.8 (6). Output Waveforms of 4-Phase 1-step Excitation (Normal Rotation and Reverse Rotation)
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Figure 3.8 (7). Output Waveforms of 4-Phase 2-step Excitation (Normal Rotation)
The operation when channel 0 is selected is explained
below.
The output latch of M0 (also used as P2) rotates at the rising
edge of the TFF1 trigger pulse (that inverts the value of TFF1) and
is output to the port.
The direction of shift is specified by P29FR <CCW0>:
Normal rotation (M00→M01→M02→M03), when <CCW0>
is set to “0”; reverse rotation (M00←M01←M02←M03) when
“1”. 4-phase 1-step excitation can be selected when only one
bit is set to “1” during the initialization of port 6, while 4-phase
2-step excitation will be selected when two consecutive bits
are set to “1”.
Figure 3.8 (8). shows the block diagram.
Figure 3.8 (8). Block Diagram of 4-Phase 1-step/2-step Excitation (Normal Rotation)
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TMP90CM38
(2)
4 Phase 1-2 Step Excitation
1-2 step excitation when channel 0 is selected.
Figures 3.8 (9) shows the output waveforms of 4-phase
Figure 3.8 (9). Output Waveforms of 4-Phase 1-2 step Excitation (Normal Rotation and Reverse Rotation)
The initialization for 4-phase 1-2 step excitation is as follows.
By rearranging the initial value “b7 b6 b5 b4 b3 b2 b1 b0”
to “b3 b7 b2 b6 b1 b5 b0 b4”, the consecutive 3 bits are set
to “1” and other bits are set to “0” (positive logic).
For example, if b3, b7 and b2 are set to “1” provided the initial value becomes “10001100”, obtaining the waveforms as
shown in Figure 3.8 (9).
To get an output waveform of negative logic, set values
1’s and 0’s of the initial value should be inverted. For example,
110
to change the output waveform shown in Figure 3.8 (9) into
negative logic, change the initial value to “011110011”.
The operation will be explained below for channel 0.
The output latch of M0 (shared by P2) and the shifter alternate
register (SA6) for stepping motor control are shifted at the
rising edge of trigger signal from the timer to be output to the
port. The direction of shift is set by P29FR <CCW0>.
Figure 3.8 (10) shows the block diagram.
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Figure 3.8 (10). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)
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Setting Example: To drive channel 0 (M0) by 4-phase 1-2
step excitation (normal rotation) when
3.8.4 Trigger Signal From Timer
The trigger signal from the timer which is used by SMC is not
equal to the reverse trigger signal of each timer flip-flop (TFF1,
timer 0 is selected, set each register as
follows.
TFF3, TFF4, and TFF5) and differs as shown in Table 3.8 (1)
depending on the operation mode of the timer.
Table 3.8 (1) 8-Bit Timers 0 and 1 (Same for timers 2 and 3)
TFF1 inversion
SMC shift
8-bit timer mode
Selected by TFFCR0 (FF1IS) when the up-counter value matches
TREG0 or TREG1 value
←
16-bit timer mode
When the up-counter value matches with both TREG0 and TREG1
values (The value of up-counter = TREG1*28 + TREG0)
←
PPG output mode
When the up-counter value matches with both TREG0 and TREG1
When the up counter value matches TREG1 value (PPG cycle)
PWM output mode
When the up-counter value matches TREG0 value at PWM cycle.
Trigger signal for SMC shift is not output.
Note: To shift SMC, TFFCR <FF1IE> must be set to “1” to enable TFF1 inversion.
Channel 1 of SMC can by synchronized with the 16-bit
timer. In this case, the SMC shift register trigger signal from the
112
16-bit timer is output only when the up-counter value matches
TREG5. Set either T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1”.
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TMP90CM38
3.8.5 Application of SMC and Timer Output
As explained in 3.8.4 “Trigger signal from timer”, the timing to
shift SMC and invert TFF differs depending on the mode of
timer. An application to operate SMC while operating an 8-bit
timer PPG mode will be explained below.
To drive a stepping motor, in addition to the value of each
phase (SMC output), synchronizing signal is often required at
the timing when excitation is changed over. In this application,
noting this fact, port 6 is used as a stepping motor control port
to output a synchronizing signal to the TO1 pin (shared by
P55).
Output Waveforms of 4-Phase 1-Step Excitation
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3.9 Serial Channels
The TMP90CM36 contains three serial channels (SIO0,1,
2).The three serial channels have the following operation
modes.
In mode 1 and mode 2, parity bit can be added. Mode 3
has a wake-up function for making the master controller start
slave controllers in serial link (multi-controller system).
Figure 3.9 (1) shows the data format (1 frame) for each
mode.
Figure 3.9 (1). Data Formats
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The serial channel has a buffer register for transmitting
and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving
operations can be done independently (full duplex).
However, in I/O interface mode, SCLK (serial clock) pin is
commonly used for both transmission and receiving, the channel becomes half-duplex.
The receiving buffer register is of a double buffer structure to
prevent the occurrence of overrun error and provides one
frame of margin before CPU reads the received data. Namely,
the one buffer stores the already received data while the other
buffer receives the next frame data.
In the UART mode, a check function is added not to start
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is
detected to be normal at least twice in three samplings.
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When the transmission buffer becomes empty and
requests the CPU to send the next transmission data, or when
data is stored in the transmission buffer and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs.
Besides, if an overrun error, parity error, or framing error occors
during receiving operation, flag SCCR <OERR, PERR, FERR>
will be set.
In the I/O interface mode, it is possible to input synchronous signals as well as to transmit or receive data by an external clock.
The SIO0 or SIO1 includes a special baud rate generator,
which can set any baud rate can be set by dividing by the frequency of 4 clocks (øT0, øT2, øT8, and øT32) from the internal
prescaler (shared by 8-bit/16-bit timer) by the value of 2 to 16.
Internal clock (SIO2) is able to select in speed from øT0,
øT1, øT4, and øT16.
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(1) Serial Channel (SIO0) (3.8.4 ~ 3.8.6)
SCMOD1, SCCR1, BRGCR1, and P7FR. Transmitted and
received data are stored in register SCBUF1.
3.9.1 Control Registers
The serial channel SIO1 is controlled by 4 control registers
Figure 3.9 (2). Serial Channel Mode Register (SCMOD1)
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Figure 3.9 (3). Serial Channel Mode Register (SCCR1)
Figure 3.9 (4). Serial Transmission/Receiving Buffer Registers (SCBUF1)
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Figure 3.9 (5). Baud Rate Generator Control Registers (BRGCR1)
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Figure 3.9 (6). Port 7 Function Register
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3.9.2 Configuration
Figure 3.9 (7) shows the block diagram of the serial channel.
Figure 3.9 (7). Serial Channel (SIO1) Block Diagram
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➀ Baud rate generator
The relation between the input clock and the source
clock (fc) is as follows.
Baud rate generator comprises of a circuit that generates transmission and receiving clocks that determine
the transfer rate of the serial channel.
The input clock to the baud rate generator, øT0 (fc/4),
øT2 (fc/16), øT8 (fc/64), or øT32 (fc/256) is generated
by the 9-bit prescaler which is shared by the timers.
One of these input clocks is selected by the baud rate
genorator control register BRGCR1 <BG11,01>.
The baud rate generator includes a 4-bit frequency
divider, which divides frequency by 2 to 16 values to
determine the transfer rate.
How to calculate a transfer rate when the baud rate
generator is used is explained below.
øT0
øT2
øT8
øT32
= fc/4
= fc/16
= fc/64
= fc/256
Accordingly, when source clock fc is 12.288MHz,
input clock øT2 (fc/16), and frequency divisor is 5, the
transfer rate in UART mode becomes as follows.
• UART mode
= 12.288 x 106/16/5/16 = 9600 (bps)
Table 3.9 (1) shows an example of the transfer rate in
UART mode.
Also with 8-bit timer 0, the serial channel (SIO1) can get a
transfer rate. Table 3.9 (1) shows an example of baud rate
using timer 2.
Table 3.9 (1) Selection of Transfer Rate (1) (When Baud Rate Generator is Used) Unit: Kbps
Input clock
Frequency clock
øT0
(fc/4)
øT2
(fc/16)
øT8
(fc/64)
øT32
(fc/256)
9.8304MHz
–
2457.600
614.400
153.600
38.400
–
2
76.800
19.200
4.800
1.200
–
4
38.400
9.600
2.400
0.600
–
8
19.200
4.800
1.200
0.300
–
16
9.600
2.400
0.600
0.150
12.288MHz
–
3072.000
786.000
192.000
48.000
–
5
38.400
9.600
2.400
0.600
Source clock
(fc)
–
10
19.200
4.800
1.200
0.300
14.7456MHz
–
3686.400
921.600
230.400
57.600
–
3
76.800
19.200
4.800
1.200
–
6
38.400
9.600
2.400
0.600
–
12
19.200
4.800
1.200
0.300
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Table 3.9 (2) Selection of Transfer Rate (2) (When Timer 0 (Input Clock øT1) is Used)) Unit: Kbps
fc
TREG2
12.288
MHz
12
MHz
9.8304
MHz
8
MHz
6.144
MHz
1H
96
–
76.8
62.5
48
2H
48
–
38.4
31.25
24
3H
32
31.25
–
–
16
4H
24
–
19.2
–
12
5H
19.2
–
–
–
9.6
8H
12
–
9.6
–
6
AH
9.6
–
–
–
4.8
10H
6
–
4.8
–
3
14H
4.8
–
–
–
2.4
How to calculate the transfer rate (when timer 2 is used0)
➂ Receiving counter
Input clock of timer 2
øT1 = fc/8
øT4 = fc/32
øT16 = fc/128
➁ Serial clock generation circuit
This circuit generates the basic clock for transmitting
and receiving data.
1) I/O interface mode
When in SCLK1 output mode with the setting of
SCCR1 <IOC1> = “0”, the basic clock will be generated by dividing by 2 the output of the baud rate generator described before. When in SCLK1 input mode
with the setting of SCCR1 <IOC1> = “1”, the rising
edge or the falling edge will be detected according to
the setting of SCCR1 <SCLK1> register to generate
the basic clock.
2) Asynchronous communication (UART) mode
122
According to the setting of SCMOD1 <SC11,01>, the
above baud rate generator clock, internal clock ø1 (fc/
2) (312.5 Kbaud at 10MHz), or the match detect signal
from timer 2 will be selected to generate the basic clock
SIOCK.
The receiving counter is a 4-bit binary counter used in
asynchronous communication (UART) mode and
counts up by SIOCLK1 clock. 16 pulses of SIOCLK1
are used for receiving 1 bit of data, and the data is
sampled three times at the 7th, 8th and 9th clock.
With the three samples, the received data is evaluated
by the rule of majority.
For example, if the sampled data is “1”, “0” and “1” at
7th, 8th and 9th clock, respectively, the received data
is evaluated as “1”. The sampled data “0”, “0”, and “1”
is evaluated that the received data is “0”.
➃ Receiving control
1) I/O interface mode
When in SCLK1 output mode with the setting of
SCCR1 <IOC1> = “0”, RxD1 signal will be sampled at
the rising edge of shift clock which is output to SCLK
pin.
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When in SCLK1 input mode with the setting of SCCR1
<IOC1> = “1”, RxD1 signal will be sampled at the rising edge or falling edge of SCLK1 input according to
the setting of SCCR1 <SCLK1> register.
2) Asynchronous communication (UART) mode
The receiving control has a circuit for detecting the start
bit by the rule of majority. When two or more “0” are
detected during 3 samples, it is recognized as normal
start bit and the receiving operation is started.
Data being received are also evaluated by the rule of
majority.
➄ Receiving buffer
To prevent overrun from occurring, the receiving buffer
has a double structure. Received data are stored one
bit by one bit in the receiving buffer 1 (shift register
type). When 7 bits or 8 bits of data rae stored in the
receiving buffer 1, the stored data are transferred to
another receiving buffer 2 (SCBUF1), generating an
interrupt INTRX1. The CPU reads only receiving buffer
2 (SCBUF1). Even before the CPU reads the receiving
buffer 2 (SCBUF1), the received data can be stored in
➆ Transmission controller
1) I/O interface mode
In SCLK1 output mode with the setting of SCCR1
<IOC1> = “0”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge of shift
clock which is output from SCLK1 pin.
In SCLK1 input mode with the setting of SCCR1
<IOC1> = “0”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge or falling
edge of SCLK input according to the setting of SCCR1
<SCLK1> register.
2) Asynchronous communication (UART) mode
When the transmission data are written in the trans-
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receiving buffer 1 . However, unless the receiving
buffer 2 (SCBUF1) is read before all bits of the next
data are received by the receiving buffer 1, an overrun
error occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of
receiving buffer 2 and SCCR1 <RB81> is still preserved.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SCCR0 <RB81>.
When in the 9-bit UART, the wake-up function of the
slave controllers is enabled by setting SCMOD1
<WU1> to “1”, and interrupt INTRX occurs only when
SCCR1 <RB81> is set to “1”.
➅ Transmission counter
Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK1
clock, generating TxDCLK1 every 16 clock pulses.
mission buffer sent from the CPU, transmission starts
at the rising edge of the next TxDCLK1, generating a
transmission shift clock TxDSFT1.
Hand-shake function
The TMP90CM38 supports a hand-shake function by
the connection of CTS of one TMP90CM38 and RTS0
of the other device.
The hand-shake function allows receiving/transmitting
data on a frame basis to prevent overrun errors. This
function is enabled or disabled by the control register
SCCR <CTSE>.
When the last bit (parity bit or MSB) of 1-frame data is
received by the receiving unit, the RTS pin turns to the
“H” level to request the transmission unit to halt transmission.
When the CTS pin turned to the “H” level, the trans123
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mission unit halts transmission, after completing the
current data transmission, until the pin turns to the “L”
level. At this time, the interrupt INTTX is generated, to
request the CPU to transfer data. Then the data is written into the transmission buffer, and the transmission
unit is placed in the standby until the CTS pin turned to
the “L” level.
When the received data are read by the CPU, the RTS
pin returns to the “L” level, requesting that the transmission is restarted.
Figure 3.9 (8). Hand-shake Function
Figure 3.9 (9). Hand-shake CTS (clear to send) Signal
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⑧ Transmission buffer
2) Parity error (SCCR1 <PERR1>)
Transmission buffer SCBUF1 shifts out and sends the
transmission data written from the CPU from the least
significant bit (LSB) in order, using transmission shift
clock TxDSFT1 which is generated by the transmission
control. When all bits are shifted out, the transmission
buffer becomes empty and generates INTTX1 interrupt.
The parity generated for the data shifted in receiving
buffer 2 (SCBUF1) is compared with the parity bit
received from the RxD1 pin. If they are not equal, a
parity error occurs.
3) Framing error (SCCR1 <FERR1>)
⑨ Parity control circuit
When serial channel control register SCCR1 <PE1> is
set to “1” , it is possible to transmit and receive data
with parity. However, parity can be added only in 7-bit
UART or 8-bit UART mode. With SCCR1 <EVEN1>
register, even (odd) parity can be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
SCBUF, and data are transmitted after being stored in
SCBUF1 <TB71> when in 7-bit UART mode while in
SCMOD1 <TB81> in 8-bit UART mode. <PE1> and
<EVEN1 > must be set before transmission data are
written in the transmission buffer.
For receiving, data are shifted in the receiving buffer 1,
and parity is added after the data are transferred in the
receiving buffer 2 (SCBUF1), and then compared with
<RB71> of SCBUF1 when in 7-bit UART mode and
with SCCR1 <RB81> when in 8-bit UART mode. If
they are not equal, a parity error occurs, and SCCR1
<PERR1> flag is set.
The stop bit of received data is sampled three times
around the center. If the majority results is “0”, a framing error occurs.
11
1) UART mode
Receiving
Mode
Three error flags are provided to increase the reliability
of receiving data.
1) Overrun error (SCCR1 <OERR1>)
If all bits of the next data are received in receiving buffer
1 while valid data are still stored in receiving buffer 2
(SCBUF1), an overrun error will occur.
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9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity,
7 Bit
Interrupt timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Framing error
timing
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Over-run error
timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of stop bit
Note:
➉ Error flag
Generation Timing
Framing error occurs after an interrupt has occurred. Therefore, to
check for framing error during interrupt operation, it is necessary to
wait for 1 bit period of time.
Transmitting
Mode
Interrupt timing
9 Bit
Just before last
bits transmitted
8 Bit + Parity
8 Bit, 7 Bit + Parity,
7 Bit
←
←
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3.9.3 Operational Description
(1)
Mode 0 (I/O Interface Mode)
This mode is used to increase the number of I/O pins of
TMP90CM36 for transmitting or receiving data to or from
the external shifter register.
This mode incudes SCLK1 output mode to output
synchronous clock SCLK1 and SCLK1 input mode to
input external synchronous clock SCLK1.
Figure 3.9 (10). I/O Interface Mode
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➀
Transmission
In SCLK1 output mode, 8-bit data and synchronous
clock are output from TxD1 pin and SCLK1 pin,
respectively, each time the CPU writes data in the
transmission buffer. When all data is output, IRF2
<IRFTX1> will be set to generate INTTX1 interrupt.
Figure 3.9 (11). Transmitting Operation in I/O Interface Mode (SCLK1 Output Mode)
In SCLK1 output mode, 8-bit data are output from
TxD1 pin and SCLK1 input becomes active while data
are written in the transmission buffer by CPU.
Figure 3.9 (12). Transmitting Operation in I/O Interface Mode (SCLK1 Input Mode)
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➁
Receiving
In SCLK1 output mode, received data are read by the
CPU, and synchronous clock is output from SCLK1
pin and the next data are shifted in the receiving buffer
1 whenever the receive interrupt flag IRF2 <IRFRX1> is
cleared. When 8-bit data are received, the data will be
transferred in the receiving buffer 2 (SCBUF1), and
<IRFRX1> will be set again to generate INTRX1 interrupt.
Figure 3.9 (13). Receiving Operation in I/O Interface Mode (SCLK1 Output Mode)
In SCLK1 input mode, received data are read by the
CPU, and the next data is shifted in the receiving
buffer 1 when SCLK1 input becomes active while the
receive interrupt flag <IRFRX> is cleared. When 8-bit
data are received, the data will be shifted in the receiving buffer 2 (SCBUF1), and <IRFRX1> will be set again
to generate INTRX1 interrupt.
Figure 3.9 (14). Receiving Operation in I/O Interface Mode (SCLK1 Input Mode)
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(2)
Mode 1 (7-Bit UART Mode)
The 7-bit mode can be set by setting serial channel mode
register SCMOD1 <SM11, 01> to “01”.
In this mode, a parity bit can be added, and the addi-
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tion of a parity bit can be enabled or disabled by serial
channel control register.
SCCR1 <PE1>, and even parity or odd parity is
selected by SCCR1 <EVEN1> when <PE1> is set to
“1” (enable).
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(3)
Mode 2 (8-Bit UART Mode)
The 8-bit UART mode can be set by setting serial channel
mode register SCMOD1 <SM11, 01> to “10”.
In this mode, a parity bit can be added, the addition of
a parity bit is enabled or disabled by SCCR10 <PE1>.
SCCR1 <PE1>, and even parity or odd parity is
130
selected by SCCR1 <EVEN1> when <PE1> is set to
“1” (enable).
Setting example: When receiving data with the following format, the control registers
should be set as described below.
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(4)
Mode 3 (9-Bit UART Mode)
Wake-up function
The 9-bit UART mode can be specified by setting
SCMOD1 <SM11, 11> to “11”. In this mode, parity bit
cannot be added.
For transmission, the MSB (9th bit) is written in
SCMOD1 <TB81>, while in receiving it is stored in
SCCR1 <RB81> . For writing or reading the buffer, the
MSB is read or written first then SCBUF1.
In 9-bit UART mode, the wake-up function of slave
controllers is enabled by setting SCMOD1 <WU1> to
“1”.
The interrupt INTRX1 occurs only when SCCR1
<RB81> = 1.
Figure 3.9 (15). Serial Link Using the Wake-up Function
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Protocol
cleared to “0”. The MSB (bit 8) SCMOD1 <TB81> is
set to “0”.
➀ Select the 9-bit UART mode for the master and
slave controllers.
➁ Set the SCMOD1 <WU1> bit of each slave controller to “1” to enable data receiving.
➂ The master controller transmits one-frame, including the 8-bit select code of the slave controllers.
The MSB (bit 8) SCMOD1 <TB81> is set to “1”.
➃ Each slave controller receives the above frame, and
clears WU bit to “0” if the above select code
matches its own select code.
➄ The master controller transmits data to the specified
slave controller whose SCMOD1 <WU1> bit is
132
➅ The other slave controllers (with SCMOD1 <WU1>
bit remaining at “1”) ignore the receiving data
because their MSBs (bit 8 or SCCR1 <RB81>) are
set to “0” to disable the interrupt INTRX1.
When the WU1 bit is cleared to “0”, the interrupt
INTRX1 occurs, so that the slave controller can read
the receiving data.
The slave controllers (WU1 = 0) transmit data to the
master controller, and it is possible to indicate the
end of data receiving to the master controller by this
transmission.
Setting example:
To link two slave controllers serially with the master controller,
and use the internal clock ø/1
(fc/2) as the transfer clock .
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3.9.4 Configuration
The serial channels are connected to external circuits through
three-pin serial ports: SCLK2 (P76), TXD2 (P77) and RXD2
(P75).
Figure 3.9 (16). Block Diagram of Serial Channels (SIO2)
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Serial clock SIO2 pulses make the following selections
through the serial channel mode register SCMOD2.
b. (External clock)
➀ Clock Source Selection
<SCLK2> uses the clock pulse externally supplied to
the SCLK2 pin as the serial clock pulse.
<SCLKS2> selects either an internal or external clock
as the clock source.
➁ Shift Edge Selection
a. (Internal clock)
SCMOD2 <CLK1, CLK0> selects the speed of either
øT1 (fc/4), øT1 (fc/8), øT4 (fc/32), or øT16 (fc/128)
serial clock. The serial clock pulse is externally output
from the SCLK2 pin.
The serial clock automatically stops after it ends the
“1-frame” serial operation. It waits until next serial
operation.
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a. Rising edge shift
Data shifts on the serial clock pulses’s rising edge (falls
at the SCLK2 pin).
b. Falling edge shift
Data shifts on the serial clock pulses’s falling edge
(rises at the SCLK2 pin or no falling edge shift in send
mode)
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3.9.5 Explanation of Operations
The send, receive and simultaneous send-receive modes for
SCMOD2 <SMD1, SMD0>.
(1)
Send Mode
The first send data is written into buffer registers
SCBUF after the send mode is set in the command
register. (Data will not be written into the buffers if the
command register is not in send mode.) Then, storing
“1” into serial transfer control registers SCMOD2
<SIOE> starts the send. As the send starts, the send
data is synchronized with serial clock pulses and
sequentially output from the TxD2 pin on the LSB side.
At the same time, the send data is transferred from the
buffer registers to the shift registers. Since the buffer
registers are empty, buffer empty interrupt INTTX2 is
generated to request the next send data.
When the interrupt service program writes the next
send data into the buffer register, the interrupt request
signal isn’t cleared to “0”.
(Internal clock pulse)
(External clock pulses)
In the internal clock operation, data must be stored in
the buffer registers before the next data shift operation
begins. The transfer speed in an interrupt service program is determined by the maximum delay time from
the interrupt request generation to buffer register data
write.
To end a send, the buffer empty interrupt service program disables (clears to “0”) serial transfer control register SCMOD2 <SIO0E> instead of writing the next
send data. When serial transfer control is disabled, the
serial transfer ends when the send data now being
shifted out is finished being sent.
The end of send can be determined by the status of
serial transfer monitor flag SCMOD2 <FFSI>. In the
external clock operation, the serial transfer control register SCMOD2 <SIOE> must be disabled before starting the next send data shift operation.
If the serial transfer control register SCMOD2 <SIOE>
is not disabled before the shift operation begins, operations stop after sending the next send data (dummy).
In the internal clock operations, if all data is sent and
no subsequent data is stored in the register, the serial
clock pulse stops and a wait begins.
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Figure 3.9 (17). Chart of Serial Channel 0 Send Mode Timing
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(2)
Receive Mode
(3)
Setting the command register to receive mode, then
setting serial serial transfer control SCMOD2 <SIOE>
to enable makes receive possible. Shift data is synchronized with serial clock pulses and fetched from
the RxD2 pin. When data is fetched, it is transferred
from the shift register to the buffer register and the
buffer-full interrupt INTRX2 is generated to request a
read of receive data.
When the interrupt service program read the next
receive data from the buffer register, the interrupt
request signal is cleared. The following data continues
to be fetched after the interrupt is generated.
After the interrupt request is cleared, data is transferred from the shift register to the buffer register when
data is fetched.
The first send data is written into buffer registers
SCBUF2 after the send-receive mode is set by the
command register. Setting the serial transfer control
register SCMOD2 <SIOE> to 1 enables receiving or
sending data. Send data is output from the TxD2 pin
on the rising edge of the serial clock pulse, while
receive data is fetched from the RxD2 pin on the falling
edge of the serial clock pulse.
When data is fetched, data is transferred from the shift
registers to the buffer registers and buffer-full interrupt
INTRX2 is genrated to request receive data read.
When the interrupt service program reads the next
receive data from the buffer register, the interrupt
request signal is cleared.
(Internal clock pulses)
(Internal clock pulses)
In the internal clock operation, if the previous receive
data has not been read from the buffer register after
the next data is fetched, the serial clock stops and
waits until the previous data is read.
In the internal clock operation, a wait begins until the
received data is read and the next send data is written.
(External clock pulses)
In the external operation, shift operations are synchronized with externally supplied clock pulses. The data is
read before the next receive data is transferred into the
buffer register. If the previous data has not been read,
the receive data will not be transferred into the buffer
registers and all subsequently input receive data will
be cancelled. The maximum transfer speed of the
external clock operation is determined by the maximum delay time from interrupt request generation to
receive data read.
Rising and falling edge shifts can be selected in the
receive mode. Because data is fetched on the serial
clock pulses’s rising edge in the rising edge shift, the
first shift data must already be input to the RxD2 pin
when the initial serial clock pulses are applied at transfer start.
138
Send-Receive Mode
(External clock pulses)
In the external clock operation, the receive data must
be read and the next send data written before starting
the next shift operation, because the shift operation is
synchronized with the external supplied clock pulses.
The maximum transfer speed of the external clock
operation is determined by the maximum delay time
from interrupt request generation to send data fetch
and receive data write.
Because the same buffer registers are used for send
and receive, always ensure that send data is written
after 8 bits of receive data are fetched.
To end send-receive, disable the serial transfer control
register. When the serial transfer control register is disabled, send-receive ends afetr receive data is organized and transferred to the buffer register.
The program checks the end of send-receive by reading serial transfer monitor flags SCMOD2 <FFSI>.
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TMP90CM38
Figure 3.9 (18) - 1. Chart of Serial Channel ø Send-Receive Mode (Falling Edge Shift) Timing
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Figure 3.9 (18) - 2. Chart of Serial Channel ø Send-Receive Mode (Falling Edge Shift) Timing
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Figure 3.9 (19) - 1. Serial Channel Control Register
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Figure 3.9 (19) - 2. Serial Channel Buffer Registers
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TMP90CM38
3.10 Analog/Digital Converter
The TMP90CM38 contains a high-speed, high-accuracy analog/digital converter (A/D converter) with 8-channel analog
input that features 8-bit sequential comparison.
Figure 3.10 (1) shows the block diagram of the A/D converter. 8-channel analog input pins (AN7 to AN0) are shared by
input-only port P6 and so can be used as input port.
Figure 3.10 (1). Block Diagram of A/D Converter
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3.10.1 Control Registers
Figure 3.10 (2). A/D Conversion Mode Register (ADMOD)
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Figure 3.10 (3). A/D Conversion Result Register (ADREG0 ~ 3)
Figure 3.10 (4). A/D Converter Channel Select Register
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TMP90CM38
3.10. 2 Operation
(1)
Analog Reference Voltage
High analog reference voltage is applied to the AVCC
pin, and the low analog voltage is applied to AVSS pin.
The reference voltage between AVCC and AVSS is
divided by 256 using ladder resistance, and compared
with the analog input voltage for A/D conversion.
(2)
(3)
(5)
There are two A/D conversion speed modes: high
speed mode and low speed mode. The selection is
executed by ADMOD <ADCS> register.
When reset, ADMOD <ADCS> will be initialized to “0”,
so that high speed conversion mode will be selected.
(6)
• A/D conversion single mode
Analog input channel is selected by ADMOD
<ADCH1,0>, ADMOD <ADCH2>. However, which
channel to select depends on the operation mode of
the A/D converter.
In fixed analog input mode, one channel is selected by
ADMOD <ADCH1,0>, ADMOD <ADCH2> among
three pins: AN0 to AN3.
In analog input channel scan mode, the number of
channels to be scanned from AN0 is specified by
ADMOD <ADCH1,0>, ADMOD <ADCH2>, such as
AN0 ➱ AN1, AN0 ➱ AN1 ➱ AN2, and AN0 ➱ AN1 ➱
AN2 ➱ AN3 or the number of channels to be scanned
from AN4 is such as AN4 ➱ AN5, AN4 ➱ AN5 ➱ AN6,
AN4 ➱ AN5 ➱ AN6 ➱ AN7.
When reset, A/D conversion channel register will be
initialized to ADMOD <ADCH1,0> = 00, ADCH
<ADCH2> = 0 so that AN0 pin will be selected.
The pins which are not used as analog input channel
can be used as ordinary input port P5.
ADMOD <EOCF> for A/D conversion end will be set to
“1”, ADMOD <ADBF> flag will be reset to “0”, and
INTAD interrupt will be enabled when A/D conversion
of specified channel ends in fixed conversion channel
mode or when A/D conversion of the last channel
ends in channel scan mode.
Interrupt requesting flip-flop is cleared only by resetting
operation or reading the A/D conversion result storing
register and cannot be cleared by instruction.
Starting A/D Conversion
• A/D conversion repeat mode
For both fixed conversion mode and conversion channel scan mode, INTAD will be disabled when in repeat
mode. Always leave the INTE0 <ADIS> flag at “0”.
Write “0” to ADMOD <REPET> to end the repeat
mode. Then, the repeat mode will be exited as soon
as the conversion in progress is completed.
(7)
Storing the A/D Conversion Result
The results of A/D conversion are stored ADREG04 to
ADREG37 registers for each channel. In repeat mode,
the registers are updated whenever conversion ends.
ADREG04 to ADREG37 are read-only registers.
(8)
Reading the A/D Conversion Result
A/D Conversion Mode
Both fixed A/D conversion channel mode and A/D
conversion channel scan mode have two conversion
modes, i.e., single and repeat conversion modes.
In fixed channel repeat mode, conversion of specified
one channel is executed repeatedly.
In scan repeat mode, scanning from AN0 ⋅⋅⋅➱ AN3 or
from AN4, ⋅⋅⋅➱ AN7 is executed repeatedly.
A/D conversion mode is selected by ADMOD <REPET,
SCAN>.
146
A/D Conversion End and Interrupt
Analog Input Channels
A/D conversion starts when A/D conversion register
ADMOD <ADS> is written “1”. When A/D conversion
starts, A/D conversion busy flag ADMOD <ADBF>
which indicates “A/D conversion is in progress” will be
set to “1”.
(4)
A/D Conversion Speed Selection
The results of A/D conversion are stored ADREG04 to
ADREG37 registers. When the contents of one of
ADREG0 to ADREG3 registers are read, ADMOD
<EOCF> will be cleared to “0”.
Setting example:
➀ When the analog input voltage of the AN3 pin pin is A/
D converted and the
results are read in the
memory at FF10H by A/D
interrupt INTAD routine.
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3.11 Watchdog Timer (Looping Detection Timer)
The purpose of the watchdog timer (WDT) is to detect the start
of CPU misoperation due to noise, etc., and bring it back to
normal.
3.11 .1 Configuration
The TMP90CM38 multiplexes the watchdog timer output
(WDTOUT) and P80. P80 (output port) is switched to the
WDTOUT pin and RESET is returned inside the chip by setting
bit WDMOD <RESCR> = “1” of the watchdog timer mode register at address #FFD0H to “1”.
Figure 3.11 (1) shows the WDT block diagram.
Figure 3.11 (1). Watchdog Timer Block Diagram
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The watchdog timer is a 22-stage binary counter that
uses (fc/2) as the input clock.
The binary counter outputs are 216/fc, 218/fc, 220/fc and
22
2 /fc. One of these outputs is used for watchdog timer output
WDTOUT.
WDTOUT outputs “0” to reset the peripheral devices
3.11.2 Control Registers
The watchdog timer (WDT) is controlled by two control registers
(WDMODE and WDCR).
(1)
Watchdog Timer Mode Register (WDMOD
➀ Watchdog timer detection time setting (WDTP)
This is a 2-bit flag used to set the watchdog timer
interrupt time for looping (runaway) detection. This flag
is initialized to WDMOD <WDTP0, 1> = 00 by resets,
which results in a value of 216/fc [sec]. (The number of
states is approximately 32,768.)
➁ Watchdog timer enable/disable control (WDTE)
This bit is initialized to WDTE = 1 by resets, which
enables the watchdog timer.
To disable the watchdog timer, it is only necessary to
clear this bit to “0” and write the disable code (B1H) to the
WDCR register. It is difficult for the watchdog timer to be
disabled by looping.
To disable the watchdog timer after it has been enabled,
it is only necessary to write “1” to the <WDTE> bit.
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when the watchdog timer overflows.
WDTOUT also is connected to RESET inside the
WDTOUT TMP90CM38. In this case, WDTOUT outputs “0” in
a 32/fxtal = 2.0µsec (fxtal = 16MHz) cycle and simultaneously
resets the TMP90CM38.
➂ Watchdog timer out reset connection (RESCR)
This flag is used to set whether or not the
TMP90CM38 will be reset when looping is detected
and whether or not to output WDTOUT.
<RESCR> is set to “1” by reset operations; therefore,
P80 is set as the WDTOUT pin and connected internally to
the RESET pin.
P80 can be set as either the WDTOUT pin or port pin
by overwriting <RESCR>. However, caution is required
because a redundant structure is used to prevent misoperation. The <RESCR> bit is linked to the P38CR
<WDTOUTC> therefore, it is always necessary to write
“1” the <WDTOUTC> when the <RESCR> bit is overwritten.
The <RESCR> bit is set only after “1” is written to the
<WDTOUTC> and then either “0” or “1” is written to
the RESCR bit.
Writing to the <RESCR> bit automatically clears the
<WDTOUTC> to “0”; therefore, when resetting the
<RESCR> bit, again write “1” to the <WDTOUTC>.
149
TMP90CM38
Figure 3.11 (2). Flowchart of P80/WDTOUT Pin Switching
150
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TMP90CM38
Figure 3.11 (3). Watchdog Timer Mode Register
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151
TMP90CM38
(2)
Watchdog Timer Control Register (WDCR)
This register enables and disables the watchdog timer,
and clears the binary counter.
• Enable control
Set WDMOD <WDTE> to “1”.
• Binary counter clear control
• Disable control
The watch timer is disabled by clearing WDMOD
<WDTE> to “0” and then writing the disable code
(B1H) to the WDCR register.
The binary counter is cleared and restarts counting
when the clear code (4EH) is written to WDCR.
Figure 3.11 (4). Watchdog Timer Control Register
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TMP90CM38
3.11.3 Operation
The watchdog timer is a timer that outputs “0” level from the
watchdog timer output pin (WDTOUT) after the detection time
set with WDMOD <WDRP1, 0> elapses. The watchdog timer
binary counter is cleared to “0” before an overflow occurs. If
the CPU misoperates (loops) due to noise, etc., the binary
counter will overflow unless the parity counter clear instruction
is executed. The CPU can be returned to normal operation by
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resetting internally. A reset can be applied to both the
TMP90CM36 and CPU by connecting the WDTOUT pin to the
RESET pins of the peripheral devices.
The watchdog timer again starts operating immediately
after the reset is canceled.
The watchdog timer stops during the IDLE mode and
STOP mode and operates during the RUN mode. The watchdog timer can also be disabled when entering the RUN mode.
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TMP90CM38
4. Electrical Characteristics
TMP90CM38F/TMP90CM38T
4.1 Maximum Ratings
Symbol
VCC
Item
Power supply voltage
Rating
Unit
-0.5 ~ + 7
V
VIN
Input voltage
-0.5 ~ VCC + 0.5
V
∑IOL
Output current (Total)
100
mA
∑IOH
Output current (Total)
-70
mA
PD
F 500
Power dissipation (Ta = 85°C)
mW
T 600
260
°C
TSTG
Storage temperature
-65 ~ 150
°C
TOPR
Operating temperature
-20 ~ 70
°C
TSOLDER
Soldering temperature (10s)
4.2 DC Electrical Characteristics
VCC = 5V ± 10%, TA = -20 ~ 70°C (1 ~ 16MHz)
Typical Values are for TA = 25°C, VCC = 5V.
Symbol
Item
Min
Max
Unit
Conditions
-0.3
0.8
V
–
VIL
Input Low Voltage (P0)
VIL1
P1, P2, P3, P4 , P5, P5, P6, P7, P9, P10
-0.3
0.3VCC
V
–
VIL2
RESET, P81 (INT0), P82 (STBY), NMI
-0.3
0.25VCC
V
–
VIL3
EA
-0.3
0.3
V
–
VIL4
X1
-0.3
0.2VCC
V
–
VIH
Input Low Voltage (P0)
2.2
VCC + 0.3
V
–
VIH1
RESET, P81 (INT0), P82 (STBY), NMI
0.7VCC
VCC + 0.3
V
–
VIH2
RESET, P81 (INT0), P82 (STBY)
0.75VCC
VCC + 0.3
V
–
VIH3
EA
VCC - 0.3
VCC + 0.3
V
–
VIH4
X1
0.8VCC
VCC + 0.3
V
VOL
Output Low Voltage
–
0.45
V
IOL = 1.6mA
VOH
VOH1
VOH2
Output High Voltage
2.4
0.75VCC
0.9VCC
–
–
V
V
V
IOH = -400µA
IOH = -100µA
IOH = -20µA
IDAR
Darlington Drive Current
(8 I/O Pins max)
-1.0
-3.5
mA
VEXT = 1.5V
REXT = 1.1kΩ
–
ILI
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ VCC
ILO
Output Leakage Current
0.05 (Typ)
± 10
µA
0.2 ≤ Vin ≤ VCC - 0.2
Operating Current (RUN)
Idle
35 (Typ)
1.5 (Typ)
50
5
mA
mA
tosc = 16MHz
0.2 (Typ)
40
10
µA
µA
0.2 ≤ Vin ≤ VCC - 0.2
VIL1 = 0.2Vcc,
VIL2 = 0.8Vcc
ICC
STOP (TA = -20 ~ 70°C)
STOP (TA = 0 ~ 50°C)
VSTOP
Power Down Voltage of
(@STOP) (RAM back up)
2.0
6.0
V
RRST
RESET Pull Up Register
50
150
KΩ
–
10
pF
0.4
1.0 (Typ)
V
CIO
Pin Capacitance
VTH
Schmitt width (RESET, P81, P82)
–
testfreq = 1MHz
–
Note: IDAR is guaranteed for up to 8 optional ports.
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TMP90CM38
4.3 AC Electrical Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C
Variable
Symbol
tOSC
12.5MHz Clock
16MHz Clock
Item
Oscillation cycle ( = X)
Unit
Min
Max
Min
Max
Min
Max
62.5
1000
80
–
62.5
–
ns
tAL
A0 ~ A7 effective address→ALE fall
0.5x - 15
–
25
–
16
–
ns
tLA
ALE fall→A0 ~ A7 hold
0.5x - 15
–
25
–
16
–
ns
tLL
ALE pulse width
x - 40
–
40
–
23
–
ns
tLC
ALE fall→RD/WR fall
0.5x - 30
–
10
–
1
–
ns
tCL
RD/WR rise→ALE rise
0.5x - 20
–
20
–
11
–
ns
tACL
A0 ~ A7 effective address→RD/WR fall
x - 25
–
55
–
38
–
ns
tACH
Upper effective address→RD/WR fall
1.5x - 50
–
70
–
44
–
ns
tCA
RD/WR fall→Upper address hold
0.5x - 20
–
20
–
11
–
ns
tADL
A0 ~ A7 effective address→Effective data input
–
3.0x - 35
–
205
–
153
ns
tADH
Upper effective address→Effective data input
–
3.5x - 55
–
225
–
164
ns
tRD
RD fall→Effective data input
–
2.0x - 50
–
110
–
75
ns
2.0x - 40
–
120
–
85
–
ns
0
–
0
–
0
–
ns
tRR
RD Pulse width
tHR
RD rise→Data hold
tRAE
RD rise→Address enable
x - 15
–
65
–
48
–
ns
tWW
WR pulse width
2.0x - 40
–
120
–
85
–
ns
tDW
Effective data→WR rise
2.0x - 50
–
100
–
65
–
ns
tWD
WR rise→Effective data hold
0.5x - 10
–
30
–
21
–
ns
AC Measurement Conditions
• Output level: High 2.2V/Low 0.8V,CL = 50pF
(However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR)
• Input level
High 2.4V/Low 0.45V (AD0 ~ AD7)
High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7)
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TMP90CM38
4.4 A/D Conversion Characteristics
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Symbol
Item
Min
Typ
Max
AVCC
Analog reference voltage
Vcc - 1.5
Vcc
Vcc
AGND
Analog reference voltage
Vss
Vss
Vss
VAIN
Analog input voltage range
Vss
–
Vcc
IREF
Analog reference voltage power supply current
–
0.5
1.0
Total error
(TA = 25°C, Vcc = VREF = 5.0V)
–
–
1.0
Total error
–
–
2.5
Error
(Quantize
error of ± 0.5
LSB not
included)
Unit
V
mA
LSB
4.5 Timer/Counter Input Clock (TI2, TI4)
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Item
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
–
740
–
600
–
ns
tVCKL
Low clock pulse width
4x + 40
–
360
–
290
–
ns
tVCKH
High clock pulse width
4x + 40
–
360
–
290
–
ns
4.6 Interrupt Operation
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Item
Unit
Min
Max
Min
Max
Min
Max
4x
–
320
–
250
–
ns
4x
–
320
–
250
–
ns
8x + 100
–
740
–
600
–
ns
8x + 100
–
740
–
600
–
ns
INT0 Low level pulse width
tINTAL
tINTAH
INT0 High level pulse width
INT1, INT2 Low level pulse width
tINTBL
INT1, INT2 High level pulse width
tINTBH
156
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TMP90CM38
4.7 Serial Channel SIO1 Timing - I/O Interface Mode
(1) SCLK1 Input Mode
VCC = 5V ± 10% TA = -20 ~ 70°C
f = 1 ~ 16MHz
Variable
Symbol
12.5MHz Clock
16MHz Clock
Item
Unit
Min
Max
Min
Max
Min
Max
16x
–
1.28
–
1
–
µs
tSCY/2 - 5x - 50
–
190
–
137
–
ns
5x - 100
–
300
–
212
–
ns
tSCY
SCLK1 cycle
tOSS
Output data →Rising edge of SCLK
tOHS
SCLK1 rising edge→Output data hold
tHSR
SCLK1 rising edge→Input data hold
0
–
0
–
0
–
ns
tSRD
SCLK1 rising edge→ Effective data input
–
tSCY - 5x - 100
–
780
–
587
ns
(2) SCLK1 Output Mode
Variable
Symbol
12.5MHz Clock
16MHz Clock
Item
Unit
Min
Max
Min
Max
Min
Max
tSCY
SCLK cycle (programmable)
16x
8192x
1.28
655.4
1
512
µs
tOSS
Output data setup→SCLK rising edge
tSCY - 2x - 50
–
970
–
725
–
ns
tOHS
SCLK rising edge→Output data hold
2x - 80
–
80
–
45
–
ns
tHSR
SCLK rising edge→Input data hold
0
–
0
–
0
–
ns
tSRD
SCLK rising edge→ Effective data input
–
tSCY - 2x - 150
–
970
–
725
ns
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157
TMP90CM38
4.8 Serial Channel SIO2 Timing
10MHz Clock
Symbol
tSCR
Serial port clock cycle time
tSCL
SCLK2 Low width
tSCH
SCLK2 High width
tSKDO
tSRD
tHSR
158
Item
VariableClock
Condition
SCLK2 → TXD2 (Output data)
delay time
SCLK2 Rising edge to input
Unit
Min
Max
Min
Max
Internal
800
12800
8x
128x
External
1600
–
16x
–
Internal
*
*
*
*
External
*
*
*
*
Internal
*
*
*
*
External
*
*
*
*
Internal
*
–
*
–
External
*
–
*
–
Internal
*
–
*
–
data valid
External
*
–
*
–
Internal
*
–
*
–
rising edge
External
*
–
*
–
Input data hold after SCLK2
ns
ns
ns
ns
ns
ns
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TMP90CM38
4.9 Timing Chart
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159
TMP90CM38
4.10 Serial Channel SIO1 I/O Interface Mode Timing Chart
4.11 Serial Channel SIO2 Timing Chart
160
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TMP90CM38
5. Special Function Register List
The special function registers (SFR) are the input/output ports,
peripheral control registers. These SFR are assigned to 96byte address areas from 0FFA0H ~ 0FFFFH.
(1)
(2)
(3)
(4)
(5)
Input/Output Port
Input/Output Port Control
Timer/Event Counter Control
A/D Converter Control
Interrupt Control
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(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
HDMA Control
WDT Control
Serial Channel Control
Time Base Counter Control
Timing Pulse Generation Control
Capture Control
D/A Converter
PWM Control
161
TMP90CM38
TMP90CM36 Special Function Register List
162
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TMP90CM38
(1) I/O Port
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163
TMP90CM38
(2) I/O Port Control (1/2)
164
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TMP90CM38
(2) I/O Port Control (2/2)
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165
TMP90CM38
(3) Timer/Event Counter Control (1/3)
166
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TMP90CM38
(3) Timer/Event Counter Control (2/3)
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167
TMP90CM38
(3) Timer/Event Counter Control (3/3)
168
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TMP90CM38
(4) A/D Converter Control
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169
TMP90CM38
(5) Interrupt Control
170
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TMP90CM38
(6) HDA Control
(7) WDT Control
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171
TMP90CM38
(8) Serial Channel Control
172
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