NTE NTE7138

NTE7138
Integrated Circuit
Advanced Monitor Video Controller for OSD
Description:
The NTE7138 is an RGB pre–amplifier in a 20–Lead DIP type package designed for color monitor
systems with super VGA performance. It is intended for DC or AC coupling of the color signals to the
cathodes of a CRT.
Features:
D 85MHz Video Controller
D Fully DC Controllable
D 3 Separate Video Channels
D Input Black Level Clamping
D White Level Adjustment for 2 Channels Only
D Brightness Control with Correct Grey Scale Tracking
D Contrast Control for All 3 Channels Simultaneously
D Cathode Feedback to Internal Reference for Cut–Off Control, Which Allows Unstabilized Video
Supply Voltage
D Current Outputs for RGB Signal Currents
D RGB Voltage Outputs to External Peaking Circuits
D Blanking and Switch–Off Input for Screen Protection
D Sync On Green Operation Possible
D On Screen Display (OSD) Facility
Absolute Maximum Ratings:
Supply Voltage (Pin7), VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +8.8V
Input Voltage Range (Pin2, Pin5, Pin8), Vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to VP
External DC Voltage Ranges, Vext
Pin20, Pin17, Pin14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to VP
Pin12, Pin15, Pin18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to +0.7V
Pin1, Pin3, Pin6, Pin11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to VP
Pin9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to VP+0.7V
Pin10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 to VP+0.7V
Average Output Current (Pin14, Pin17, Pin20, Note 1), Io(av) . . . . . . . . . . . . . . . . . . . . . . . 0 to 50mA
Peak Output Current (Pin14, Pin17, Pin20), IOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 100mA
Total Power Dissipation, Ptot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200mW
Electrostatic Handling for All Pins (Note 2), Vesd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500V
Operating Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25° to +150°C
Operating Ambient Temperatrure Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25° to +150°C
Thermal Resistance, Junction–to–Ambient (In Free Air), RthJA . . . . . . . . . . . . . . . . . . . . . . . . 65K/W
Note 1. Signal amplitude of 50mA black–to–white is possible if the average current (including blanking times and signal variation against time) does not exceed 50mA. The maximum power
dissipation of 1200mW has to be considered.
Note 2. Equivalent to discharging a 200pF capacitor through a 0Ω series resistor.
Electrical Characteristics: (VP = 8V, TA = +25°C, Note 3, Note 4 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply
Supply Voltage Range
VP
7.2
8.0
8.8
V
Supply Current
IP
36
48
60
mA
Vi(b–w)
–
0.7
1.0
V
Vl(clamp)
2.8
3.1
3.4
V
Video Signal Inputs (Channels 1, 2 and 3)
Input Voltage (Black–to–White)
DC Voltage During Input Clamping
(Artificial Black + VBE)
DC Input Current
II
No Clamping, Vi = Vl(clamp),
TA = –20° to +70°C
–0.05 +0.05 +0.25
µA
During Clamping,
Vi = Vl(clamp) +0.7V
50
75
120
µA
During Clamping,
Vi = Vl(clamp) –0.7V
–120
–75
–50
µA
1.0
–
6.0
V
2.0
2.25
2.5
V
40
50
60
kΩ
Vi(BC) = 1.0V
–13
–11
–9.5
%
Vi(BC) = 6.0V
30
34
37
%
Pin1 Open–Circuit
–
–
0.8
%
∆VBT
–1.2
0
+1.2
%
Vi(CC)
1.0
–
6.0
V
–
–
VP–1
V
Brightness Control (Note 5)
Input Voltage Range
Vi(BC)
Input Voltage for Nominal Brightness
Input Resistance
Black Level Voltage Change at Voltage
Outputs Referred to Reference Black
Level During Output Clamping
(Vi(HBL) > 1.6V) Related to Output
Signal Amplitude with Nominal 0.7V(P–P)
Input Signal and Nominal Contrast
(Vi(CC) = 4.3V) for Any Gain Setting
Difference of ∆Vbl Between and Two
Channels
Pin1 Open–Circuit
Ri(BC)
∆Vbl
Contrast Control (Note 6)
Input Voltage Range
Maximum Input Voltage
Input Voltage Range for Nominal Contrast
Note 7
–
4.3
–
V
Input Voltage Range for Minimum Contrast
Pin3 and Pin11 Open–Circuit
–
0.7
–
V
Vi(CC) = 4.3V
–5
–1
–0.1
µA
Vi(CC) = 6V, Pin3 and Pin11
Open–Circuit
2.4
3.4
–
dB
Vi(CC) = 1V, Pin3 and Pin11
Open–Circuit
–26
–22
–19
dB
1V < Vi(CC) < 6V, Note 8
–
0
0.5
dB
Input Current
Contrast Relative to Nominal Contrast
Tracking of Output Signals of
Channels 1, 2 &3
Ii(CC)
C/Cnom
∆Gtrack
Delay Between Leading (Falling) Edges of
Contrast Voltage and Voltage Output
Waveforms
tdf(C)
Vi(CC) = 4.3V to 0.7V, Input
Fall Time at Pin6: tf(CC) = 2ns,
Note 9
–
7
20
ns
Delay Between Trailing (Rising) Edges of
Contrast Voltage and Voltage Output
Waveforms
tdr(C)
Vi(CC) = 0.7V to 4.3V, Input
Rise Time at Pin6: tf(CC) = 2ns,
Note 9
–
15
25
ns
Fall Time of Voltage Output Waveform
tf(C)
90% to 10% Amplitude, Input
Fall Time at Pin6: tf(CC) = 2ns,
Note 9
–
6
15
ns
Rise Time of Voltage Output Waveform
tr(C)
10% to 90% Amplitude, Input
Rise Time at Pin6: tf(CC) = 2ns,
Note 9
–
6
15
ns
Electrical Characteristics (Cont’d): (VP = 8V, TA = +25°C, Note 3, Note 4 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1.0
–
6.0
V
3.6
3.75
3.95
V
44
55
66
kΩ
Vi(CC) = 4.3V, Vi(GC) = 6V
2.0
2.6
3.3
dB
Vi(CC) = 4.3V, Vi(GC) = 1V
–5.5
–5.0
–4.5
dB
5.6
5.8
6.1
V
–500
–100
–60
nA
Note 12
0
40
200
mV
TA = –20° to +70°C
0
20
50
mV
0
60
100
mV
Pin3 and Pin11 Open–Circuit,
Vi(CC) = 4.3V, Vi(b–w) = 0.7V
0.69
0.79
0.89
V
During Output Clamping,
TA = –20° to +70°C
1.0
1.2
1.4
V
Gain Control (Channel 1 and Channel 3, Note 10)
Input Voltage
Vi(GC)
Input Voltage for Nominal Gain
Input Resistance
Pin3, Pin11 Open Circuit
Ri(GC)
∆G
Gain Control Difference Relative to
Nominal Gain (Channels 1 and 3 Only)
Feedback Input (Channels 1, 2 and 3, Note 11)
Internal Reference Voltage
Vref(int)
Maximum Output Current
Io(FB)
Black–Level Variation at CRT
Variation of Vref(int) in the Temperature
Range
Variation of Vref(int) with Supply Voltage
∆Vbl(CRT)
∆Vref(T)
During Output Clamping,
Vi(FB) = 3V
∆Vref(int)(VP) 7.2V ≤ VP ≤ 8.8V
Voltage Outputs (Channels 1, 2 and 3)
Nominal Signal Output Voltage
(Black–to–White Value)
Maximum Adjustable Black–Level Voltage
Vo(b–w)
Vblx(max)
Black–Level Voltage During Switch–Off,
Equal to Minimum Adjustable
Black–Level Voltage
Vbl(SO)
Vi(HBL) = VP, RO = 33Ω,
TA = –20° to +70°C
30
45
100
mV
Black–Level Voltage During Test Mode
Vbl(TST)
Vi(HBL) = VP, Vi(CL) = VP,
Pin1 Open–Circuit,
Vi = Vi(clamp), Note 13
0.3
0.7
1.2
V
Note 14
–
50
44
dB
Signal–to–Noise Ratio
S/N
Output Thermal Distortion
dO(th)
Io(b–w) = 50mA, Note 15
–
0.6
1.0
%
Blacl–Level Variation Between
Clamping Pulses
∆Vbl(fl)
Line frequency 30kHz
–
0.5
4.5
mV
Maximum Offset During Sync Clipping
Voffset(max)
Vl < Vl(clamp), Note 16
0
7
15
mV
Variation of Nominal Output Signal
(Black–to–White Value) with
Temperature
∆Vo(b–w)(T)
Pin3 and Pin11 Open–Circuit,
Vi(CC) = 4.3V, Vi(b–w) = 0.7V,
TA = –20° to +70°C
0
2.5
10
%
–
50
–
mA
With Peaking
–
–
100
mA
Current Outputs (Channels 1, 2 and 3, Note 17)
Output Current (Black–to–White Value)
Io(b–w)
Start of HF–Saturation Voltage of
Output Transistors
V20–19,
V17–16,
V14–13
Io = 50mA
–
–
2.0
V
Io = 100mA
–
–
2.2
V
Output Current During Switch–Off
Ibl(SO)
Vi(HBL) = VP, RO = 33Ω
0
20
900
µA
Frequency Response at Voltage Outputs (Note 18)
Gain Decrease by Frequency Response
∆G(f)
70MHz, Single Channel
–
1.3
3.0
dB
Rise Time at Voltage Output
tr(O)
10% to 90% Amplitude,
Input Rise Time = 1ns
–
4.1
5.0
ns
Overshoot of Output Signal Pulse Related
to Actual Output Pulse Amplitude
dVO
Single Channel,
Input Rise Time = 2.5ns,
Vi(b–w) = 0.7V, Vi(CC) = 4.3V,
Pin3 and Pin11 Open–Circuit
–
4
8
%
Electrical Characteristics (Cont’d): (VP = 8V, TA = +25°C, Note 3, Note 4 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
–
–
–20
dB
1.2
1.4
1.6
V
5.8
6.5
6.8
V
Against GND
50
80
110
kΩ
Input Rise Time at Pin9 > 100ns,
Note 20
–
40
60
ns
1.2
1.4
1.6
V
2.6
3.0
3.5
V
VP–1
–
VP
V
–3
–1
–
µA
Crosstalk at Voltage Outputs with Speed Up Circuit (Note 18)
Transient Crosstalk
αct(tr)
Threshold Voltages for Clamping, Blanking and Switch–Off (Note 19)
Threshold for Horizontal Blanking
(Blanking, Output Clamping)
Vi(HBL)
Threshold for Switch–Off (Blanking,
Minimum Black–Level, No Output
Clamping)
Input Resistance
Delay Between Horizontal Blanking
Input and Output Signal Blanking
Threshold for Vertical Blanking
(Blanking, No Input Clamping)
Ri(HBL)
td(Hblank)
Vi(CL)
Note 20
Threshold for Vertical Blanking
(Input Clamping, No Blanking)
Threshold for Test Mode
(No Clamping, No Blanking
See Vbl(TST) Above)
Current
For Test Mode Also,
Vi(HBL) > 6.8V (Switch–Off)
Ii(CL)
Vi(CL) < VP –1V
Vi(CL) ≥ VP –1V
Rise and Fall Time for Clamping Pulse
tr(CL), tf(CL)
Width of Clamping Pulse
tw(clamp)
Delay Between Vertical Blanking Input
and Internal Blanking
td(Vblank)
Note 20
Note 20
µA
–
–
75
ns/V
0.6
–
–
µs
260
320
380
ns
Notes to the Characteristics:
Note 3. All voltages measured to GND (Pin4).
Note 4. Definition of levels:
a) Artificial black level: internal signal level behind input emitter follower during input
clamping and signal clipping. This level is inserted instead of the input signal during
blanking.
b) Reference black level: DC voltage during output clamping at voltage outputs, not
influenced by brightness, contrast or gain setting, adjustable by cut–off stabilization.
c) Cut–off level: corresponding DC voltage at CRT cathode in closed feedback loop.
d) Black level: actual signal black level at either the voltage outputs or cathode, it can
be adjusted by (brightness x gain), it refers to reference black level or cut–off level.
e) Ultra–black level, switch–off level: lowest adjustable reference black level, lowest
signal level at voltage outputs.
f) The minimum guaranteed control range for reference black level is 0.1 to 1.0V. The
ultra–black level is dependent on the external resistor RO at Pin13, Pin16 and Pin19
(voltage outputs) to GND.
Ro
g) Vbl(SO) ≈
x 4.65V
3.5kΩ + Ro
Note 5. Linear control range is 1 to 6V for Vi(BC), independent of supply voltage.
Note 6. Linear control range is 1 to 6V vor Vi(BC), independent of supply voltage. Open Pin6 leads
to maximum contrast setting. It is recommended not to exceed Vi(CC) = VP – 1V to avoid saturation of internal circuitry. For Vi(CC) < Vi(CC) ≈ 0.7V a small negative signal (≈ –40dB) will
appear. For frequency dependency of contrast control, see Note 18.
Note 7. Definition for nominal output signals: input Vi(b–w) = 0.7V, gain Pin3 and Pin11 open–circuit,
contrast control Vi(CC) = Vi(CC)(nom).
Notes to the Characteristics (Cont’d):
A
A1
A
A1
A
A2
x 20 ; log
x 30 ; log
x 30 dB
A10
A2
A10
A3
A20
A3
Ax: signal output amplitude in channel x at any contrast sertting between 1 and 6V.
Ax0: signal output amplitude in channel x at nominal contrast and same gain setting.
Typical step in contrast voltage and response at signal outputs for nominal input signal
Vi(b–w) = 0.7V (OSD fast blanking input/output).
Linear control range is 1 to 6V for Vi(GC), independent of supply voltage.
The internal reference voltage can be measured at Pin18, Pin15 and Pin12 (channel feedback inputs) during output clamping (Vi(HBL) = 2V) in closed feedback loop.
Slow variations of video supply VCRT will be suppressed at CRT cathode by cut–off stabilization. Change of VCRT by 5V leads to specified cghange of cut–off voltage.
The test mode allows testing without input and output clamping pulses. The signal inputs
have to be biased via resistors to the previously measured clamp voltages of approximately
3V (artificial black level + VBE). Signal and brightness blanking is not possible during test
mode. The current outputs should be adjusted by resistors >> R0 from voltage outputs to a
positive voltage (e.g. VP).
The signal–to–noise ratio is calculated by the formula (frequency range 1 to 70MHz):
Note 8. ∆Gtrack = 20 x maximum of
Note 9.
Note10.
Note 11.
Note12.
Note13.
Note14.
log
peak–to–peak value of the nominal signal output voltage
S
= 20 x log
dB
RMS value of the noise output voltage
N
Note15. Large output swing e.g. Io(b–w) = 50mA leads to signal–dependent power dissipation in output
transistors. Thermal VBE variation is compensated.
Note16. Composite signals will not disturb normal operation because an internal clipping circuit cuts
all signal parts below black level.
1
1
Note17. The output current approximately follows the equation Io = Vo
–500µA for
+
RO 2.2kΩ
Vo > Vb(SO) and with RO = external resistor at voltage output to GND. The external RC combination at Pin19, Pin16 and Pin13 (voltage outputs) enables peak currents during transients.
Note18. Frequency responses, crosstalk aznd pulse response have been measured at voltage outputs on a special printed–circuit board with 50Ω line in/out connections and without peaking.
Note19. Crosstalk between any two voltage outputs (e.g. channels 1 and 2).
a) Input conditions: one channel (channel1 ) with nominal input signal and minimum
rise time. The inputs of the other channels capacitively coupled to GND (channels 2
and 3). Gain Pin3 and Pin11 open–circuit.
b) Output conditions: output signal of channel 1 is set by contrast control voltage, to
Vo(b–w) = Vo(VOUT1) = 0.7V, the rise time should be 5ns. Output signal of channel 2 then
is Vo(b–w) = Vo(VOUT2).
V
c) Transient crosstalk: αct(tr) = 20 x log o(VOUT2) db
Vo(VOUT1)
d) Crosstalk as a function of frequency has been measured without peaking circuit, with
nominal input signal and nominla settings.
Note20. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are
generated while the input pulses are higher than the thresholds. Voltages less than –0.1V
at Pin9 and Pin10 can influence black–level control and should be avoided.
Note21. The delay between HBL input pulse (horizontakl blanking) and output signal blanking pulse
and also brightness blanking (∆Vbl), at the voltage outputs, depends on the input rise time
of the HBL pulse. The specified values for td(Hblank) are valid for HBL rise times greater than
100ns only.
Note22. For 75ns/V < tf(CL) < 240ns/V, generation of internal input clamping and blanking pulse is not
defined. Pulses not exceeding the threshold of input clamping (typical 3V) will be detected
as blanking pulses.
Functional Description:
General
The RGB input signals 0.7V(P–P) are capacitively coupled into the NTE7138 from a low ohmic source
and are clamped to an internal DC voltage (artificial black level). Composite signals will not disturb
normal operations because an internal clipping circuit cuts all signal parts below black level. Channels
1 and 3 have a maximum total voltage gain of 7dB (maximum contrast and maximum individual channel gain), channel 2 having 4.4dB (maximum contrast and nominal gain). With the nominal channel
gain of 1dB and nominal contrast setting the nominal balck–to–white output signal is 0.79V(P–P).
Brightness, contrast and gain control is by DC voltage.
Brightness Control
Brightness control yeilds a simultaneous signal black–level shift of the three channels relative to a
reference black level.
For normal brightness (Pin1 open–circuit) the signal black–level is equal to the reference black level.
Contrast Control
Contrast is voltage controlled to affect the three channels simultaneously. To provide the correct white
point, individual gain controls adjust the signals of channels 1 and 3 relative to the reference channels
2. Gain setting also changes contrast to achieve correct grey scale tracking.
Output Stages
The output stages provide both voltage and current outputs. External cascode transistors reduce
power consumption of the IC and prevent breakdown of the output transistors. Signal output currents
and peaking characteristics are determined by external components at the voltage outputs and the
video supply. The channels have separate internal feedback loops which ensure large signal linearity
and marginal signal distortion irrespective of output transistor thermal VBE variation.
Input Clamping
The clamping pulse is for input clamping only. The input signals are at black level during the clamping
pulse and are clamped to an internal artificial black level. The coupling capacitors provide black–level
storage. The threshold for the clamping pulse is higher than that for vertical blanking, thereofre, the
rise and fall times of the clamping pulse need to be faster than 75ns/V during transition from 1 to 3.5V.
Vertical Blanking
The vertical blanking pulse will be detected if the input voltage is higher than the threshold voltage
for approximately 320ns but does not exceed the threshold for the clamping pulse in the time between.
During the vertical blanking pulse the input clamping is disabled to avoid misclamping in the event
of composite input signals. The input signal is blanked and the artificial black level is inserted instead.
Also the brightness is set internally to its nominal value, thus the output signal is at reference balck
level. The DC value of the reference black level will be adjusted by cut–off stabilization.
Horizontal Blanking
During horizontal blanking the output signal is set to reference black level and output clamping is activated. If the voltage exceeds the switch–off threshold, the signal is blanked and switched to ultra–
black level for screen protection and spot suppression during V–flyback.
Ultra–black level is the lowest possible channel output voltage and is not dependent on cut–off stabilization.
Cut–Off and Black–Level Stabilization
For cut–off stabilization (DC coupling to the CRT) and black–level stabilization (AC coupling) the video
signal at the cathode or the coupling capacitor is divided by an adjustable voltage divider and fed to
the channel feedback inputs. During horizontal blanking time this signal is compared with an internal
DC voltage of approximately 5.8V. Any difference will lead to a reference black–level correction by
charging or discharging the integrated capacitor which stores the reference black–level information
between the horizontal blanking pulses.
On Screen Display
For OSD, fast switching of control Pin6 to less than 1V (e.g. 0.7V) blanks the input signals. The OSD
signals can easily be inserted to the external cascode transistor.
Functional Description (Cont’d):
Test Mode
During test mode (Pin9 and Pin10 connected to VP) the black levels at the channel voltage outputs
are set internally to typical 0.7V with nominal brightness and 3V DC at channel signal inputs.
Pin Connection Diagram
Brightness Control 1
Signal Input Ch1 2
Gain Control Ch1 3
GND 4
Signal Input Ch2 5
Contrast Control, OSD Swithc 6
VP 7
Signal Input Ch3 8
Horizontal Blanking, Swith Off 9
Input Clamping, Vertical Blanking, 10
Test Mode
20
20
19
18
17
16
15
14
13
12
11
Current Output Ch1
Voltage Output Ch1
Feedback Ch1
Current Output Ch2
Voltage Output Ch2
Feedback Ch2
Current Output Ch3
Voltage Output Ch3
Feedback Ch3
Gain Control Ch3
11
.280 (7.12) Max
1
10
.995 (25.3) Max
.300 (7.62)
.280
(7.1)
.100 (2.54)
.125 (3.17) Min
.385 (9.8)