STD95NH02L N-CHANNEL 24V - 0.0039Ω - 80A DPAK ULTRA LOW GATE CHARGE STripFET™ MOSFET Table 1: General Features TYPE STD95NH02L ■ ■ ■ Figure 1: Package VDSS RDS(on) ID 24 V < 0.005Ω 80(*) A TYPICAL RDS(on) = 0.0039Ω @ 10 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 DESCRIPTION The STD95NH02L is based on the latest generation of ST’s proprietary STripFET™ technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements in high-frequency DC-DC converters. It’s therefore ideal for high-density converters in Telecom and Computer applications. 1 DPAK TO-252 (Suffix “T4”) Figure 2: Internal Schematic Diagram APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS Table 2: Order Codes PART NUMBER MARKING PACKAGE PACKAGING STD95NH02LT4 D95NH02L DPAK TAPE & REEL Rev. 2 September 2004 1/11 STD95NH02L Table 3: Absolute Maximum ratings Symbol Vspike(1) VDS VDGR Parameter Value Unit Drain-source Voltage Rating 30 V Drain-source Voltage (VGS = 0) 24 V Drain-gate Voltage (RGS = 20 kΩ) 24 V ± 20 V Drain Current (continuous) at TC = 25°C 80 A Drain Current (continuous) at TC = 100°C 68 A Drain Current (pulsed) 320 A Total Dissipation at TC = 25°C 100 W Derating Factor 0.67 W/°C Single Pulse Avalanche Energy 600 mJ -55 to 175 °C 1.5 °C/W VGS Gate- source Voltage ID (*) ID IDM (2) PTOT EAS (3) Tstg Tj Storage Temperature Max. Operating Junction Temperature (1) Garanted when external Rg = 4.7 Ω and tf < tf max. (2) Pulse width limited by safe operating area. (3) Starting Tj = 25°C, ID = 40A, VDD = 22V (*) Value limited by wires Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W Tl Maximum Lead Temperature For Soldering Purpose 275 °C ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol 2/11 Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 40 A VGS = 5 V, ID =40 A V(BR)DSS Min. Typ. Max. 24 Unit V 1 10 µA µA ±100 nA V 1 0.0039 0.0055 0.005 0.009 Ω Ω STD95NH02L ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic Symbol gfs (4) Parameter Test Conditions Forward Transconductance VDS = 10 V, ID = 10 A Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 15V, f = 1 MHz, VGS = 0 td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Qg Qgs Qgd Min. Typ. Max. Unit 30 S 2070 990 90 pF pF pF VDD = 12 V, ID = 40 A, RG= 4.7 Ω VGS = 10 V (see Figure 16) 20 110 47 20 ns ns ns ns Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 12 V, ID = 80 A, VGS = 5 V (see Figure 19) 17 7.6 6.8 nC nC nC Qoss (5) Output Charge VDS = 19 V, VGS = 0 V 22.6 nC Qgls (6) Third-Quadrant Gate Charge VDS < 0 V, VGS = 5 V 15 nC Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain 1.8 Ω RG Table 7: Source Drain Diode Symbol ISD ISDM VSD (4) trr Qrr IRRM Max. Unit Source-drain Current Parameter 80 A Source-drain Current (pulsed) 320 A 1.3 V Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. ISD = 40A, VGS = 0 ISD = 80A, di/dt = 100 A/µs, VDD =20 V, Tj = 150°C (see Figure 16) 42 50.4 2.4 ns nC A (4). Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (5). Qoss = Coss*∆ Vin, Coss = Cgd+Cds. See Appendix A. (6). Gate charge for Syncronous Operation. 3/11 STD95NH02L Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/11 STD95NH02L Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature 5/11 STD95NH02L Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/11 STD95NH02L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 2.20 2.40 0.087 TYP. MAX. 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.90 0.025 0.035 B2 5.20 5.40 0.204 0.213 C 0.45 0.60 0.018 0.024 C2 0.48 0.60 0.019 0.024 D 6.00 6.20 0.236 0.244 E 6.40 6.60 0.252 0.260 G 4.40 4.60 0.173 0.181 H 9.35 10.10 0.368 0.398 L2 0.8 0.031 L4 0.60 1.00 0.024 0.039 V2 0o 8o 0o 0o P032P_B 7/11 STD95NH02L DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 12.1 0.476 B1 1.6 MIN. MAX. D 1.5 D1 1.5 E 1.65 1.85 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 P0 3.9 4.1 0.153 0.161 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R 40 W 15.7 * on sales type 8/11 inch 0.059 0.063 0.059 0.065 0.073 1.574 16.3 0.618 0.641 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 STD95NH02L Appendix A: Buck Converter Power Losses Estimation DESCRIPTION The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: - Very low RDS(on) to reduce conduction losses - Small Qgls to reduce the gate charge losses - Small Coss to reduce losses due to output capaci tance - Small Qrr to reduce losses on SW1 during its turn-on - The Cgd/C gs ratio lower than Vth /VGG ratio especially with low drain to source voltage to avoid the cross conduction phenomenon The high side (SW1) device requires: - Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate - Small Qg to have a faster commutation and to reduce gate charge losses - Low RDS(on) to reduce the conduction losses Parameter δ Qgsth Qgls Pconduction Pswitching Pdiode Pdiode PQoss Pconduction Pswitching High Side Switch (SW1) Low Side Switch (SW2) RDS(on)SW1* I2L *δ RDS(on)SW2* I2L *(1− δ ) Vin *(Qgsth(SW1)+ Qgd(SW1)) *f * IL Ig Zero Voltage Switching Recovery Not Applicable Conduction Not Applicable Vf(SW2) * IL * t deadtime*f Pgate(QG ) Qg(SW1)* Vgg * f Qgls(SW2)* Vgg * f PQoss Vin *Qoss(SW1)*f Vin *Qoss(SW2)*f 2 2 Pdiode 1 Vin * Qrr(SW2)*f Meaning Duty-Cycle Post Threshold Gate Charge Third Quadrant Gate Charge On State Losses On-off Transition Losses Conduction and Reverse Recovery Diode Losses Gate Drive Losses Output Capacitance Losses 9/11 STD95NH02L Table 8: Revision History Date Revision 27-Aug-2004 10-Sep-2004 1 2 10/11 Description of Changes First Release. Values changed in table 7 STD95NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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