ETC STD55NH2LL

STD55NH2LL
N-CHANNEL 24V - 0.008 Ω - 55A DPAK/IPAK
ULTRA LOW GATE CHARGE STripFET™ POWER MOSFET
TARGET DATA
TYPE
STD55NH2LL
■
■
■
■
■
■
■
■
VDSS
RDS(on)
ID
24 V
< 0.010 Ω
55 A
TYPICAL RDS(on) = 0.008 Ω @ 10 V
TYPICAL RDS(on) = 0.011 Ω @ 4.5 V
RDS(ON) * Qg INDUSTRY’s BENCHMARK
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
LOW THRESHOLD DEVICE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1")
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
3
3
1
2
1
IPAK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
INTERNAL SCHEMATIC DIAGRAM
DESCRIPTION
The STD55NH2LL is based on the latest generation of
ST's proprietary STripFET™ technology. An innovative
layout enables the device to also exhibit extremely low
gate charge for the most demanding requirements as
high-side switch in high-frequency DC-DC converters. It's
therefore ideal for high-density converters in Telecom
and Computer applications.
APPLICATIONS
■ SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC CONVERTES
Ordering Information
SALES TYPE
STD55NH2LLT4
STD55NH2LL-1
MARKING
D55NH2LL
D55NH2LL
PACKAGE
TO-252
TO-251
PACKAGING
TAPE & REEL
TUBE
ABSOLUTE MAXIMUM RATINGS
Symbol
Vspike(1)
VDS
VDGR
VGS
ID
ID
IDM(2)
Ptot
EAS(3)
Tstg
Tj
Parameter
Drain-source Voltage Rating
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Operating Junction Temperature
Value
30
24
24
± 18
55
39
220
60
0.4
TBD
Unit
V
V
V
V
A
A
A
W
W/°C
mJ
-55 to 175
°C
September 2003
This is preliminary information on a new product forseen to be developped. Details are subject to change without notice
1/10
STD55NH2LL
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
2.5
100
275
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating TC = 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 18V
V(BR)DSS
Min.
Typ.
Max.
24
Unit
V
1
10
µA
µA
±100
nA
Max.
Unit
ON (4)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
VGS = 4.5 V
ID = 27.5 A
ID = 27.5 A
Min.
Typ.
1
V
0.008
0.011
0.010
0.014
Ω
Ω
Typ.
Max.
Unit
DYNAMIC
Symbol
Test Conditions
gfs (4)
Forward Transconductance
VDS = 20 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Gate Input Resistance
RG
2/10
Parameter
ID = 27.5 A
Min.
TBD
S
VDS = 10V f = 1 MHz VGS = 0
860
450
56
pF
pF
pF
f = 1 MHz Gate DC Bias = 0
Test Signal Level = 20 mV
Open Drain
1.5
Ω
STD55NH2LL
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
td(on)
tr
Turn-on Delay Time
Rise Time
ID = 27.5 A
VDD = 10 V
RG = 4.7 Ω
VGS = 10 V
(Resistive Load, Figure 3)
TBD
TBD
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
0.44V ≤ VDD ≤ 10V,
VGS= 4.5 V
9
TBD
TBD
Output Charge
VDS= 10 V
Qoss (5)
ID= 55 A
VGS= 0 V
Max.
Unit
ns
ns
12
TBD
nC
nC
nC
nC
SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
ID = 27.5 A
VDD = 10 V
RG = 4.7Ω,
VGS = 10 V
(Resistive Load, Figure 3)
Typ.
Max.
TBD
TBD
Unit
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM
Source-drain Current
Source-drain Current (pulsed)
VSD (4)
trr
Qrr
IRRM
Test Conditions
Forward On Voltage
ISD = 27.5 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
di/dt = 100A/µs
ISD = 55 A
VDD = 20 V
Tj = 150°C
(see test circuit, Figure 5)
(1) Garanted when external Rg=4.7 Ω and tf < tfmax.
(2) Pulse width limited by safe operating area
(3) Starting Tj = 25 oC, ID = 25A, VDD = 15V
Min.
Typ.
VGS = 0
Max.
Unit
55
220
A
A
1.3
V
TBD
TBD
TBD
ns
nC
A
(4) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(5) Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Appendix A
.
.
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STD55NH2LL
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/10
STD55NH2LL
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
5/10
STD55NH2LL
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL "A"
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL "A"
L4
0068772-B
6/10
STD55NH2LL
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STD55NH2LL
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is er moved to allow for a safer working junction
temperature.
The low side (SW2) device requires:
•
•
•
•
•
Very low RDS(on) to reduce conduction losses
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires:
•
Small Rg and Ls to allow higher gate current peak and to limit the voltage
feedback on the gate
•
Small Qg to have a faster commutation and to reduce gate charge losses
•
Low RDS(on) to reduce the conduction losses.
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STD55NH2LL
Pconduction
Pswitching
Low Side Switch (SW2)
R DS(on)SW1 * I 2L * d
R DS(on)SW2 * I 2L * (1 − d )
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
IL
Ig
Zero Voltage Switching
Recovery
Not Applicable
Conduction
Not Applicable
Vf(SW2) * I L * t deadtime * f
Pgate(Q G )
Q g(SW1) * Vgg * f
Q gls(SW2) * Vgg * f
PQoss
Vin * Q oss(SW1) * f
Vin * Q oss(SW2) * f
2
2
Pdiode
Parameter
d
Qgsth
Qgls
Pconduction
Pswitching
Pdiode
Pgate
PQoss
1
High Side Switch (SW1)
1
Vin * Q rr(SW2) * f
Meaning
Duty-cycle
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
Dissipated by SW1 during turn-on
9/10
STD55NH2LL
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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