STMICROELECTRONICS STL80NF3LL

STL80NF3LL
N-CHANNEL 30V - 0.0045Ω - 80A PowerFLAT™ ( 6X5 )
STripFET™ II MOSFET
PRODUCT PREVIEW
Figure 1: Package
Table 1: General Features
TYPE
STL80NF3LL
■
■
■
■
■
■
VDSS
RDS(on)
ID
30 V
< 0.0055 Ω
20 A (2)
TYPICAL RDS(on) = 0.0045 Ω @ 10V
IMPROVED DIE-TO-FOOTPRINT RATIO
VERY LOW PROFILE PACKAGE (1mm MAX)
VERY LOW THERMAL RESISTANCE
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
PowerFLAT™( 6x5 )
DESCRIPTION
The STL80NF3LL utilizes the second generation
of STMicroelectronics unique “Single Feature
Size™” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. Such features make it the
best choice in high efficiency DC-DC converters
for Telecom and Computer industries. The Chipscaled PowerFLAT™ package allows a significant
board space saving, still boosting the performance.
Figure 2: Internal Schematic Diagram
APPLICATIONS
HIGH-EFFICIENCY DC-DC CONVERTERS
■ SYNCHRONOUS RECTIFICATION
■
TOP VIEW
Table 2: Order Codes
Part Number
Marking
Package
Packaging
STL80NF3LL
L80NF3LL
PowerFLAT™ (6x5)
TAPE & REEL
Rev. 3
June 2005
This is a preliminary information on a new product now in development. Details are subjet to change without notice
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STL80NF3LL
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
Unit
30
V
± 16
V
Drain Current (continuous) at TC= 25°C
80
A
Drain Current (continuous) at TC= 100°C
50
A
VDS
Drain-source Voltage (VGS= 0)
VGS
Gate- source Voltage
ID (1)
ID (1)
IDM (3)
Drain Current (pulsed)
320
A
Drain Current (continuous) at TC= 25°C
20
A
PTOT (2)
Total Dissipation at TC= 25°C
4
W
PTOT (1)
Total Dissipation at TC= 25°C
80
W
0.03
W/°C
– 55 to 150
°C
Thermal Resistance Junction-Case (Drain)
1.56
°C/W
Thermal Operating Junction-pcb
31.3
°C/W
ID (2)
Derating Factor(2)
Tstg
Tj
Storage Temperature
Max. Operating Junction Temperature
Table 4: Thermal Data
Rthj-C
Rthj-pcb (2)
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 5: On /Off
Symbol
Parameter
Test Conditions
V(BR)DSS
Drain-source Breakdown
Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 16 V
VGS(th)
Gate Threshold Voltage
VDS= VGS, ID= 250µA
RDS(on)
Static Drain-source On
Resistance
Min.
Typ.
Max.
30
Unit
V
1
10
± 10
1
µA
µA
nA
V
VGS= 10 V, ID= 10 A
0.0045
0.0055
Ω
VGS= 4.5 V, ID= 10 A
0.0055
0.007
Ω
Table 6: Dynamic
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Symbol
Parameter
gfs (4)
Forward Transconductance
Test Conditions
VDS= 10V, ID= 10 A
VDS= 25V, f= 1 MHz, VGS= 0
Min.
Typ.
Max.
Unit
37
S
2160
pF
Ciss
Input Capacitance
Coss
Output Capacitance
614
pF
Crss
Reverse Transfer
Capacitance
98
pF
RG
Gate Input Resistance
4.1
Ω
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
STL80NF3LL
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 7: Switching On
Symbol
Parameter
Test Conditions
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
VDD= 15 V, ID= 10 A
RG = 4.7Ω, VGS = 4.5V
(see Figure 15)
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD= 15V, ID= 10 A, VGS= 4.5 V
(see Figure 17)
Min.
Typ.
Max.
23.5
39
47.5
37
Unit
ns
ns
ns
ns
26
7
12
35
nC
nC
nC
Typ.
Max.
Unit
Table 8: Source Drain Diode
Symbol
ISD
Parameter
Test Conditions
Min.
Source-drain Current
20
A
ISDM (3)
Source-drain Current (pulsed)
80
A
VSD (4)
Forward On Voltage
ISD= 20 A, VGS= 0
1.3
V
Reverse Recovery Time
Reverse RecoveryCharge
Reverse Recovery Current
ISD= 20 A, di/dt= 100 A/µs,
VDD= 15 V, Tj = 150°C
(see Figure 16)
trr
Qrr
IRRM
39
45
2.3
ns
nC
A
(1) The value is rated according Rthj-C .
(2) When mounted on FR-4 board of 1in², 2oz Cu., t<10sec
(3) Pulse width limited by safe operating area.
(4) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
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STL80NF3LL
Figure 3: Safe Operating Area
Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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STL80NF3LL
Figure 9: Gate Charge vs Gate-source Voltage
Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized BVDSS vs Temperature
Figure 11: Normalized On Resistance vs Temperature
Figure 14: Source-Drain Diode Forward Characteristics
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STL80NF3LL
Figure 15: Switching Times Test Circuit For
Resistive Load
Figure 16: Test Circuit For Diode Recovery
Times
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Figure 17: Gate Charge Test Circuit
STL80NF3LL
PowerFLAT™ (6x5) MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
0.80
0.83
0.93
0.031
0.032
0.036
A1
0.02
0.05
0.0007
0.0019
A3
0.20
A
b
0.35
0.40
0.007
0.47
0.013
0.015
D
5.00
0.196
D1
4.75
0.187
D2
4.15
4.20
4.25
0.163
0.165
E
6.00
0.236
E1
5.75
0.226
E2
3.43
3.48
3.53
E4
2.58
2.63
2.68
e
L
0.135
1.27
0.70
0.80
0.018
0.167
0.137
0.139
0.103
0.105
0.050
0.90
0.027
0.031
0.035
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STL80NF3LL
Table 9: Revision History
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Date
Revision
18-Apr-2005
20-Jun-2005
1
2
22-Jun-2005
3
Description of Changes
First Release.
Updated mechanical data
New RG value on table 6
STL80NF3LL
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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