FAIRCHILD FPBL15SH60

FPBL15SH60
FPBL15SH60
Smart Power Module (SPM)
General Description
Features
FPBL15SH60 is an advanced smart power module (SPM)
that Fairchild has newly developed and designed to provide
very compact and low cost, yet high performance ac motor
drives mainly targeting high speed low-power inverterdriven application like washing machines. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced current
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
integrated under-voltage lock-out protection. The high
speed built-in HVIC provides opto-coupler-less IGBT gate
driving capability that further reduce the overall size of the
inverter system design. In addition the incorporated HVIC
facilitates the use of single-supply drive topology enabling
the FPBL15SH60 to be driven by only one drive supply
voltage without negative bias.
• UL Certified No. E209204
• 600V-15A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection
• Single-grounded power supply due to built-in HVIC
• Typical switching frequency of 15kHz
• Inverter power rating of 0.75kW / 100~253 Vac
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
• Adjustable current protection level by varying series
resistor value with sense-IGBTs
Applications
• AC 100V ~ 253V three-phase inverter drive for small
power (0.75kW) ac motor drives
• Home appliances applications requiring high switching
frequency operation like washing machines drive system
• Application ratings:
- Power : 0.75kW / 100~253 Vac
- Switching frequency : Typical 15kHz (PWM Control)
- 100% load current : 5A (Irms)
- 150% load current : 7.5A (Irms)
External View and Marking Information
Top View
Bottom View
57 mm
55 mm
Marking
Device Name
Version, Lot Code
Fig. 1.
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Integrated Power Functions
•
600V-15A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 10, 15 and 16.
• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC)
Control supply circuit under-voltage (UV) protection
• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply)
• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Top View
VS(U)
VB(U)
VCC(UH)
IN(UH)
VCC(L)
COM(L)
IN(UL)
IN(VL)
IN(WL)
VFO
CFOD
CSC
VS(V)
VB(V)
VCC(VH)
IN(VH)
COM(H)
RSC
NC
VS(W)
VB(W)
NC
NC
VCC(WH)
IN(WH)
W
V
U
N
P
Fig. 2.
Pin Descriptions
Pin Number
1
Pin Name
VCC(L)
Pin Description
Low-side Common Bias Voltage for IC and IGBTs Driving
2
COM(L)
3
IN(UL)
Signal Input Terminal for Low-side U Phase
4
IN(VL)
Signal Input Terminal for Low-side V Phase
5
IN(WL)
Signal Input Terminal for Low-side W Phase
6
VFO
7
CFOD
Capacitor for Fault Output Duration Time Selection
8
CSC
Capacitor (Low-pass Filter) for Short-current Detection Input
9
RSC
Resistor for Short-circuit Current Detection
10
NC
No Connection
No Connection
Low-side Common Supply Ground
Fault Output Terminal
11
NC
12
NC
No Connection
13
W
Output Terminal for W Phase
14
V
Output Terminal for V Phase
15
U
Output Terminal for U Phase
16
N
Negative DC–Link Input
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Pin Descriptions (Continued)
Pin Number
17
Pin Name
P
Pin Description
Positive DC–Link Input
Signal Input Terminal for High-side W Phase
18
IN(WH)
19
VCC(WH)
20
VB(W)
High-side Bias Voltage for W Phase IGBT Driving
21
VS(W)
High-side Bias Voltage Ground for W Phase IGBT Driving
22
COM(H)
23
IN(VH)
24
VCC(VH)
25
VB(V)
High-side Bias Voltage for V Phase IGBT Driving
26
VS(V)
High-side Bias Voltage Ground for V Phase IGBT Driving
27
IN(UH)
Signal Input Terminal for High-side U Phase
28
VCC(UH)
29
VB(U)
High-side Bias Voltage for U Phase IGBT Driving
30
VS(U)
High-side Bias Voltage Ground for U Phase IGBT Driving
High-side Bias Voltage for W Phase IC
High-side Common Supply Ground
Signal Input Terminal for High-side V Phase
High-side Bias Voltage for V Phase IC
High-side Bias Voltage for U Phase IC
Internal Equivalent Circuit and Input/Output Pins
(29) VB(U)
(1) VCC(L)
VCC
VB
Vcc
HO
IN
(28) VCC(UH)
(27) IN(UH)
VS COM
(2) COM(L)
COM(L)
(3) IN(UL)
IN(UL)
(4) IN(VL)
IN(VL)
(5) IN(WL)
IN(WL)
(6) VFO
V(FO)
(30) VS(U)
Uout
(25) VB(V)
Vout
VB
Vcc
HO
IN
VS COM
(8) CSC
(23) IN(VH)
(22) COM(H)
(26) VS(V)
Wout
(7) CFOD
(24) VCC(VH)
(20) VB(W)
C(FOD)
C(SC)
(9) RSC
VB
Vcc
HO
IN
(19) VCC(WH)
(18) IN(WH)
VS COM
(10) NC
(21) VS(W)
(11) NC
(12) NC
W
(13)
V
(14)
U
(15)
N
(16)
P
(17)
Note
1. Inverter low-side ( (1) - (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving,
current sensing and protection functions.
2. Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals.
3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
Fig. 3.
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Absolute Maximum Ratings
Inverter Part (TC = 25°C,
Unless Otherwise Specified)
Item
Symbol
VDC
Supply Voltage
Supply Voltage (Surge)
VPN(Surge)
Collector-Emitter Voltage
Condition
Applied to DC - Link
Rating
450
Applied between P- N
VCES
Unit
V
500
V
600
V
A
Each IGBT Collector Current
± IC
TC = 25°C (Note Fig. 4)
15
Each IGBT Collector Current (Peak)
± ICP
TC = 25°C (Note Fig. 4)
30
A
Collector Dissipation
PC
TC = 25°C per One Chip
47
W
Operating Junction Temperature
TJ
(Note 1)
-55 ~ 150
°C
Note
1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation.
Control Part (TC = 25°C,
Unless Otherwise Specified)
Item
Control Supply Voltage
Symbol
Condition
Applied between VCC(H) - COM(H), VCC(L) - COM(L)
VCC
High-side Control Bias Voltage
VBS
Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W)
Input Signal Voltage
VIN
Applied between IN(UH), IN(VH), IN(WH) - COM(H)
IN(UL), IN(VL), IN(WL) - COM(L)
Fault Output Supply Voltage
VFO
Applied between VFO - COM(L)
Fault Output Current
IFO
Sink Current at VFO Pin
Current Sensing Input Voltage
VSC
Applied between CSC - COM(L)
Rating
18
Unit
V
20
V
-0.3 ~ 6.0
V
-0.3~VCC+0.5
V
5
mA
-0.3~VCC+0.5
V
Total System
Item
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
Module Case Operation Temperature
Symbol
Condition
VDC(PROT) Applied to DC - Link,
VCC = VBS = 13.5 ~ 16.5V
TJ = 125°C, Non-repetitive, less than 6µs
TC
Storage Temperature
TSTG
Isolation Voltage
VISO
©2002 Fairchild Semiconductor Corporation
Note Fig. 4
60Hz, Sinusoidal, AC 1 minute, Connection
Pins to Heat-sink Plate
Rating
400
Unit
V
-20 ~ 100
°C
-55 ~ 150
°C
2500
Vrms
Rev. C, February 2002
FPBL15SH60
Case Temperature (TC) Detecting Point
VS(U)
VB(U)
VCC(UH)
IN(UH)
VCC(L)
COM(L)
IN(UL)
IN(VL)
IN(WL)
VFO
CFOD
CSC
VS(V)
VB(V)
VCC(VH)
IN(VH)
COM(H)
RSC
NC
VS(W)
VB(W)
NC
NC
Ceramic
Substate
VCC(WH)
IN(WH)
W
V
U
N
P
Fig. 4. Tc Measurement Point
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
Thermal Resistance
Item
Junction to Case Thermal
Resistance
Contact Thermal
Resistance
Symbol
Condition
Rth(j-c)Q Each IGBT under Inverter Operating Condition
(Note 2)
Min. Typ.
-
Max.
2.61
Unit
°C/W
Rth(j-c)F
Each FWDi under Inverter Operating Condition
(Note 2)
-
-
3.73
°C/W
Rth(c-f)
Ceramic Substrate (per 1 Module)
Thermal Grease Applied
-
-
0.06
°C/W
Max.
2.8
Unit
V
Note
2. For the measurement point of case temperature (Tc), please refer to Fig. 4.
Electrical Characteristics
Inverter Part (Tj = 25°C, Unless Otherwise Specified)
Item
Collector - Emitter
Saturation Voltage
Symbol
VCE(SAT) VCC = VBS = 15V
VIN = 0V
Condition
IC = 15A, Tj = 25°C
-
-
2.9
V
IC = 15A, Tj = 25°C
-
-
2.3
V
-
-
2.1
V
-
0.39
-
µs
-
0.12
-
µs
-
0.53
-
µs
-
0.16
-
µs
(Note 3)
-
0.1
-
µs
VCE = VCES, Tj = 25°C
-
-
250
µA
VFM
VIN = 5V
Switching Times
tON
VPN = 300V, VCC = VBS = 15V
IC = 15A, Tj = 25°C
VIN = 5V ↔ 0V, Inductive Load
(High-Low Side)
IC = 15A, Tj = 125°C
tOFF
tC(OFF)
trr
Collector - Emitter
Leakage Current
ICES
Typ.
-
IC = 15A, Tj = 125°C
FWDi Forward Voltage
tC(ON)
Min.
-
Note
3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition
internally. For the detailed information, please see Fig. 5.
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Absolute Maximum Ratings
FPBL15SH60
t rr
100% IC
VCE
IC
IC
V IN
VCE
V IN
t ON
90% IC
10% IC
10% VCE
VIN(ON)
t OFF
t C(ON)
V IN(OFF)
(a) Turn-on
tC(OFF)
10% VCE
10% IC
(b) Turn-off
Fig 5. Switching Time Definition
VCE : 100V/div.
IC : 5A/div.
time : 100ns/div.
(a) Turn-on
IC : 5A/div.
VCE : 100V/div.
time : 100ns/div.
(b) Turn-off
Fig. 6. Experimental Results of Switching Waveforms
Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), TC=25°°C
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
Control Part (Tj = 25°C, Unless Otherwise Specified)
Item
Control Supply Voltage
Symbol
Condition
Applied between VCC(H),VCC(L) - COM
VCC
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
Min.
13.5
Typ. Max. Unit
15
16.5
V
13.5
15
16.5
V
VCC(L) - COM(L)
-
-
26
mA
VCC = 15V
IN(UH, VH, WH) = 5V
VCC(U), VCC(V), VCC(W) COM(H)
-
-
130
uA
IQBS
VBS = 15V
IN(UH, VH, WH) = 5V
VB(U) - VS(U), VB(V) -VS(V),
VB(W) - VS(W)
-
-
420
uA
VFOH
VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up
4.5
-
-
V
VFOL
VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up
-
-
1.1
V
PWM Input Frequency
fPWM
TC ≤ 100°C, TJ ≤ 125°C
-
15
-
kHz
Allowable Input Signal
Blanking Time Considering
Leg Arm-Short
tdead
-20°C ≤ TC ≤ 100°C
1.5
-
-
us
High-Side Bias Voltage
VBS
Quiescent VCC Supply
Current
IQCCL
VCC = 15V
IN(UL, VL, WL) = 5V
IQCCH
Quiescent VBS Supply
Current
Fault Output Voltage
Sensing Voltage
of IGBT Current
Short Circuit Trip Level
VSC(ref) TJ = 25°, VCC = 15V (Note 4)
VSEN -20°C ≤ TC ≤ 100°C, @ RSC = 82 Ω and
IC = 15A (Note Fig. 7)
Supply Circuit UnderVoltage Protection
UVCCR
Reset Level
UVBSD
Detection Level
UVCCD
TJ ≤ 125°C
Reset Level
UVBSR
Fault-Out Pulse Width
tFOD
Detection Level
VCC = 15V, C(sc) = 1V
CFOD = 33nF (Note 5)
ON Threshold Voltage
VIN(ON) High-Side
OFF Threshold Voltage
VIN(OFF)
ON Threshold Voltage
VIN(ON) Low-Side
OFF Threshold Voltage
VIN(OFF)
0.45
0.51
0.56
V
0.37
0.45
0.56
V
11.5
12
12.5
V
12
12.5
13
V
7.3
9.0
10.8
V
8.6
10.3
12
V
1.4
1.8
2.0
ms
Applied between IN(UH), IN(VH),
IN(WH) - COM(H)
-
-
0.8
V
3.0
-
-
V
Applied between IN(UL), IN(VL),
IN(WL) - COM(L)
-
-
0.8
V
3.0
-
-
V
Note
4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be
selected around 56 Ω in order to make the SC trip-level of about 20A.
Please refer to Fig. 7 which shows the current sensing characteristics according to sensing resistor RSC.
5. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F]
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Electrical Characteristics
FPBL15SH60
90
SC Trip Current ISC [A]
80
70
60
50
40
30
20
10
10
20
30
40
50
60
70
80
90
Sensing Resistor RSC [Ω ]
Fig. 7. Relationship between Sensing Resistor and SC Trip Current
for Short-Circuit Protection
(ISC = 82 × Rating Current(15A) / RSC)
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
Item
Mounting Torque
Limits
Condition
Mounting Screw: M3
(Note 6 and 7)
Ceramic Flatness
Units
Recommended 10kg•cm
Min.
8
Typ.
10
Max.
12
Kg•cm
Recommended 0.98N•m
0.78
0.98
1.17
N•m
0
-
+100
um
-
56
-
g
(Note Fig. 8)
Weight
Fig. 8. Flatness Measurement Position of The Ceramic Substrate
Note
6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction.
7. Avoid one side tightening stress. Fig.9 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to
be damaged.
4
2
1
3
Fig. 9. Mounting Screws Torque Order (1 → 2 → 3 → 4)
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Mechanical Characteristics and Ratings
Item
Symbol
Value
Condition
Min.
-
Typ.
300
Max.
400
Unit
Supply Voltage
VPN
Applied between P - N
Control Supply Voltage
VCC
Applied between VCC(H) - COM(H),
VCC(L) - COM(L)
13.5
15
16.5
V
High-Side Bias Voltage
VBS
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.5
15
16.5
V
Blanking Time for Preventing
Arm-short
tdead
For Each Input Signal
1.5
-
-
us
fPWM
TC ≤ 100°C, TJ ≤ 125°C
15
-
kHz
PWM Input Signal
-
V
Input ON Threshold Voltage
VIN(ON)
Applied between UIN,VIN, WIN - COM
0 ~ 0.65
V
Input OFF Threshold Voltage
VIN(OFF)
Applied between UIN,VIN, WIN - COM
4 ~ 5.5
V
ICs Internal Structure and Input/Output Conditions
RBS
CBSC
CBS
DBS
P
15V Line
VB(UH,VH,WH)
VCC(UH,VH,WH)
UV
DETECT
LEVEL
SHIFT
5V Line
RP
CBP15
IN(UH,VH,WH)
R
R
S Q
PULSE
FILTER
PULSE
GENERATOR
VS (UH,VH,WH)
COM
CPH
HVIC
VCC(L)
5V Line
RP
BANDGAP
REFERENCE
RPF
IN(UL,VL,WL)
U,V,W
LVIC
UV
DETECT
PULSE
GENERATOR
(HYSTERISIS)
TIME
DELAY
UV
LATCH_UP
UV
PROTECTION
BUFFER
SC
PROTECTION
OUTPUT
(UL,VL,WL)
SOFT_OFF
CONTROL
VFO
CPL
FAULT OUTPUT
DURATION
CPF
SC
LATCH_UP
TIME
DELAY
SC
DETECTION
CFOD
CFOD
N
CSC
RF
RSC
Note
1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs
2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs
3. Each IC has under voltage detection and protection function.
4. The logic input is compatible with standard CMOS or LSTTL outputs.
5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
SPM gating input pin.
6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 10.
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Recommended Operating Conditions
FPBL15SH60
Time Charts of SPMs Protective Function
Input Signal
Internal IGBT
Gate-Emitter Voltage
Control Supply Voltage
P3
P5
UV
detect
P1
P2
UV
reset
P6
Output Current
P4
Fault Output Signal
P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : Fault signal generation
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 11. Under-Voltage Protection (Low-side)
Input Signal
Internal IGBT
Gate-Emitter Voltage
Control Supply Voltage
VBS
P3
P5
UV
detect
P1
P2
UV
reset
P6
Output Current
Fault Output Signal
P4
P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : No fault signal
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 12. Under-Voltage Protection (High-side)
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
P5
Input Signal
P6
Internal IGBT
Gate-Emitter Voltage
SC Detection
P1
P4
P7
Output Current
P2
SC Reference
Voltage (0.5V)
Sensing Voltage
RC Filter Delay
P8
P3
Fault Output Signal
P1 : Normal operation - IGBT ON and conducting currents
P2 : Short-circuit current detection
P3 : IGBT gate interrupt / Fault signal generation
P4 : IGBT is slowly turned off
P5 : IGBT OFF signal
P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation
P7 : IGBT OFF state
P8 : Fault-output reset and normal operation start
Fig. 13. Short-circuit Current Protection (Low-side Operation only)
5V-Line
FPBL15SH60
4.7k Ω
4.7k Ω
4.7k Ω
100 Ω
CPU
IN (UH) , IN (VH) , IN(WH)
100 Ω
IN (UL) , IN (VL) , IN (WL)
100 Ω
VFO
1nF
1nF
0.47nF
1.2nF
COM
Note
It would be recommended that by-pass capacitors for the gating input signals, IN(XX) should be placed on the SPM pins and on the both sides of CPU and SPM
for the fault output signal, VFO, as close as possible.
Fig. 14. Recommended CPU I/O Interface Circuit
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
One-leg Diagram of FPBL15SH60
15V-Line
P
20Ω
0.1uF
220uF
Vcc
VB
IN
HO
COM VS
Inverter
Output
Vcc
0.1uF
1000uF
IN
OUT
COM
N
Fig. 15. Recommended Bootstrap Operation Circuit and Parameters
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
Gating VL
Gating WL
Gating UH
CPU
Gating VH
Fault
Gating WH
CBPF
RS RS RS
RS RS RS RS
VB(U) (29)
5V line
(1) VCC(L)
RP
RP
RP
(2) COM(L)
RP
(3) IN(UL)
(4) IN(VL)
VCC
VB
Vcc
HO
IN
COM(L)
IN(UL)
Uout
VB(V) (25)
Vout
VB
Vcc
HO
IN
VS COM
(6) VFO
CSC
(8) CSC
RF
(9) RSC
RP
RP
RP
C(FOD)
DBS
RBS
CPH CPH CPH
IN(VH) (23)
COM(H) (22)
VB(W) (20)
Wout
CBSC CBS
VCC(VH) (24)
VS(V) (26)
V(FO)
(7) CFOD
5V line
IN(UH) (27)
VS(U) (30)
IN(VL)
IN(WL)
CFOD
RBS
VS COM
(5) IN(WL)
CPF CPL CPL CPL
DBS
VCC(UH) (28)
CBSC CBS
DBS
RBS
VCC(WH) (19)
VB
Vcc
HO
IN
C(SC)
IN(WH) (18)
15V line
VS COM
RSC
VS(W) (21)
(10) NC
(11) NC
CBSC CBS
CSPC15
CSP15
(12) NC
(13) W
(14) V
(15) U
(16) N
(17) P
CDCS
M
-
Vdc
+
Note
1. RPCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input
pin.
2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
possible.
3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please
refer to Fig. 14.
4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(L)(pin2). (Example : if CFOD = 5.6 nF,
then tFO = 300 µs (typ.)) Please refer to the note 5 for calculation method.
6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed
depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor
should be used across each power supply connection terminals.
7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 µs. RF should be at least 30 times larger than RSC. (Recommended
Example: RSC = 56 Ω, RF = 3.9kΩ and CSC = 1nF)
9. Each capacitor should be mounted as close to the pins of the SPM as possible.
10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noninductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended.
11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and
the relays. It is recommended that the distance be 5cm at least
Fig. 16. Application Circuit
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
FPBL15SH60
Gating UL
FPBL15SH60
Detailed Package Outline Drawings
©2002 Fairchild Semiconductor Corporation
Rev. C, February 2002
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Advance Information
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This datasheet contains the design specifications for
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©2002 Fairchild Semiconductor Corporation
Rev. H4