TDA9106A LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS PRELIMINARY DATA .. .. . .. .. . . . .. .. .. .. HORIZONTAL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : HORIZONTAL POSITION, FREQUENCY GENERATOR FOR BURN-IN MODE Combined with ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9106A allows to built fully I2 C bus controlled computer display monitors, thus reducing the number of external components to a minimum value. VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP GEOMETRY TRACKING WITH V-POS & AMP I2C CONTROLS : V-AMP, V-POS, S-CORR, C-CORR GENERAL SYNC PROCESSOR HOR. & VERT. SYNC OUTPUT FOR MCU HOR. & VERT. BLANKING OUTPUTS 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE HORIZONTAL MOIRE OR DAC OUTPUT DESCRIPTION The TDA9106A is a monolithic integrated circuit assembled in 42 pins shrunk dual in line plastic package.This IC controlsall the functionsrelated to the horizontal and vertical deflection in multimodes or multi-frequency computer display monitors. The internal sync processor, combinedwith thevery powerful geometry correction block are making the TDA9106Asuitablefor very high performancemonitors with very few external components. It is particularly well suited for high-end 15” and 17” monitors. SHRINK42 (Plastic Package) ORDER CODE : TDA9106A PIN CONNECTIONS S/G 1 42 GND MOIRE 2 41 SDA PLL1INHIB 3 40 SCL PLL2C 4 39 5V HREF 5 38 H/HVIN HFLY 6 37 HLOCKOUT HGND 7 36 HOUT FC2 8 35 VSYNCOUT FC1 9 34 TEST C0 10 33 VSYNCIN R0 11 32 VFOCUS PLL1F 12 31 EWOUT HLOCKCAP 13 30 VFLY HPOS 14 29 VOUT XRAY 15 28 VDCOUT HFOCUSCAP 16 27 VCAP HFOCUS 17 26 VREF V CC 18 25 VAGCCAP GND 19 24 VGND HOUTEM 20 23 VBLKOUT HOUTCOL 21 22 HBLKOUT November 1997 This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice. 9106A-01.EPS I2C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pincushion, Keystone, Corner Correction, Top/bottom Corner Correction Balance) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) HORIZONTAL AND VERTICAL DYNAMIC FOCUS (Horizontal Focus Amplitude, Horizontal Focus Symmetry) 1/30 TDA9106A PIN CONNECTIONS Name 1 S/G Function Sync on green input 2 MOIRE 3 PLL1 INHIB Moire output 4 PLL2C Second PLL Loop Filter 5 HREF Horizontal Section Reference Voltage (to filter) 6 HFLY Horizontal Flyback Input (positive polarity) 7 HGND Horizontal Section Ground 8 FC2 VCO Low Threshold filtering Capacitor 9 FC1 VCO High Threshold filtering Capacitor 10 C0 Horizontal Oscillator Capacitor TTL-Compatible input for PLL1 inhibition 11 R0 12 PLL1F Horizontal Oscillator Resistor 13 HLOCKCAP 14 HPOS Horizontal Centering Output (to filter) 15 XRAY X-RAY protection input (with internal latch function) 16 HFOCUSCAP 17 HFOCUS 18 VCC First PLL Loop Filter First PLL Lock/Unlock Time Constant Capacitor Horizontal Dynamic Focus Oscillator Capacitor Horizontal Dynamic Focus Output Supply Voltage (12V Typ) General Ground (related to VCC) 19 GND 20 HOUTEM Horizontal Drive Output (internal transistor emitter) 21 HOUTCOL Horizontal Drive Output (int. trans. open collector) 22 HBLKOUT Horizontal Blanking Output (see activation table) 23 VBLKOUT Vertical Blanking Output (see activation table) 24 VGND 25 VAGCCAP 26 VREF Vertical Section Reference Voltage (to filter) 27 VCAP Vertical Sawtooth Generator Capacitor 28 VDCOUT Vertical Position Reference Voltage Output 29 VOUT Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any) 30 VFLY Vertical Flyback Input (positive polarity) 31 EWOUT East/West Pincushion Correction Parabola Output (with Corner corrections if any) 32 VFOCUS Vertical Dynamic Focus Output 33 VSYNCIN TTL-compatible Vertical Sync Input (for separated H&V) 34 TEST 35 VSYNCOUT 36 HOUT 37 HLOCKOUT 38 H/HVIN Vertical Section Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Not to be used - Test pin TTL Vertical Sync Output (Extracted VSYNC in case of S/G or TTL Composite HV Inputs) TTL Horizontal Sync Output (To be used for frequency measurement) First PLL Lock/Unlock Output (5V unlocked - 0V locked) TTL-compatible Horizontal Sync Input 39 5V 40 SCL I2C-Clock input 41 SDA I C-Data input 42 GND Ground (Related to 5V) 2/30 Supply Voltage (5V Typ.) 2 9106A-01.TBL Pin TDA9106A QUICK REFERENCE DATA Autosynch Frequency (for given R0 and C0) Value Unit 15 to 150 kHz 1 to 4.5 FH ± Horizontal Sync Polarity Input YES Polarity Detection (on both Horizontal and Vertical Sections) YES TTL Composite Synch or Sync on Green YES Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES 2 I C Control for H-Position ± 10 XRay Protection YES Fixed Horizontal Duty Cycle % 48 % I C Free Running Adjustment NO F0 2 Stand-by Function YES Two Polarities H-Drive Outputs YES Supply Voltage Monitoring YES PLL1 Inhibition Possibility YES Blanking Outputs (both Horizontal and Vertical) YES Vertical Frequency 35 to 200 Hz Vertical Autosync (for 150nF) 50 to 165 Hz Vertical S-Correction YES Vertical C-Correction YES Vertical Amplitude Adjustment YES Vertical Position Adjustment YES East/West Parabola Output YES Pin Cushion Correction Amplitude Adjustment YES Keystone Adjustment YES Corner and Corner Balance Adjustments YES Internal Dynamic Horizontal Phase Control YES Side Pin Balance Amplitude Adjustment YES Parallelogram Adjustment YES Tracking of Geometric Corrections YES Reference Voltage (both on Horizontal and Vertical) YES Dynamic Focus (both Horizontal and Vertical) YES 2 YES 2 YES I C Horizontal Dynamic Focus Amplitude Adjustment I C Horizontal Dynamic Focus Keystone Adjustment Type of Input Sync Detection (supplied by 5V Digital Supply) YES Horizontal Moiré Output YES I2C Controlled H-Moiré Amplitude YES Frequency Generator for Burn-in YES Fast I2C Read/Write 400 kHz 3/30 9106A-02.TBL Parameter Horizontal Frequency 7 HGND 1 9106A-02.EPS GND 42 SCL 40 SDA 41 5V 39 TEST 34 VGND 24 VREF 26 VSYNCIN 33 H/HVIN 38 S/G HOUT 36 VSYNCOUT 35 VBLKOUT 23 HBLKOUT 22 VFLY 30 5 HREF GND 19 VREF HFLY PLL1INHIB VFLY PLL1F I2C INTERFACE RESET GENERATOR VREF BLANKING GENERATOR HPOSFILTER 11 Safe Freq. 2 bits S AND C CORRECTION VCO 10 R0 9 VPOS 7 bits 8 32 29 28 X2 X Key Bal 6 bits X2 20 HOUTCOL 21 X 7 bits X2 6 bits HFOCUS CAP MOIRE 31 EWOUT 2 17 HFOCUS 16 15 X-RAY 18 VCC TDA9106 CORNER CORRECTION (2 x 6 bits) VSYNC MOIRE PROCESSOR 5 BITS X2 SAFETY PROCESSOR HOUT BUFFER HOUTEM Amp & Keyst 2 x 5 bits H-FLY H-SAWTOOTH GENERATOR PHASE SHIFTER Spin Bal 6 bits 4 25 VAMP 7 bits GEOMETRY TRACKING PHASE COMPARATOR 6 27 VERTICAL OSCILLATOR RAMP GENERATOR SYNC PROCESSOR 6 bits SYNC INPUT SELECT (2 bits) 6 bits HLOCKOUT LOCK/UNLOCK IDENTIFICATION PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits) HLOCKCAP 37 13 C0 VCAP 14 FC1 VAGCCAP 12 FC2 VDCOUT VSYNC HFLY VOUT LOCK PLL2C VFOCUS 4/30 3 TDA9106A BLOCK DIAGRAM TDA9106A ABSOLUTE MAXIMUM RATINGS Parameter Value Unit 13.5 V VCC Supply Voltage (Pin 18) VDD Supply Voltage (Pin 39) 5.7 V VIN Max Voltage on Pin 6 Pins 15, 21, 22, 23 Pin 1 Pin 4 Pins 3, 33,34,37,38,40,41 Pin 16 Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30 1.8 12 3.6 4 5 6 8 V V V V V V V 2 kV VESD ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ EIAJ Norm,200pF Discharge through 0Ω 300 V Tstg Storage Temperature -40, +150 o C Tj Junction Temperature +150 o C 0, +70 o C Toper Operating Temperature 9106A-03.TBL Symbol Symbol Rth (j-a) Parameter Value Junction-ambient Thermal Resistance Max. Unit o 65 C/W 9106A-04.TBL THERMAL DATA SYNCHRO PROCESSOR Operating Conditions Symbol Parameter Test Conditions Min. HsVR Horizontal Sync Input Voltage Pin 38 0 MinD Minimum Horizontal Input Pulses Duration Pin 38 0.7 Mduty Maximum Horizontal Input Signal Duty Cycle Pin 38 Typ. Max. 5 Unit V µs 25 5 % VsVR Vertical Sync Input Voltage Pin 33 0 VSW Minimum Vertical Sync Pulse Width Pin 33 5 V VSmD Maximum Vertical Sync Input Duty Cycle Pin 33 15 % VextM M ax i m um V er t ic al Syn c W i dt h on T T L H/Vcomposite or S/G Pins 1, 38 750 µs Max. Unit µs Electrical Characteristics (VDD = 5V, Tamb = 25oC) Parameter Test Conditions Min. Typ. VSGDC S/G Clamped DC Level Pin 1, I1 = -1µA 1 V ISGbias Internal Diode Bias Current Pin 1, V1 = 1.6V 10 µA VSGTh Slicing Level (see application design choice) Pin 1 0.2 VINTH H o r iz on t al a n d V ert i cal I npu t V o lta ge (Pins 33,38) Low Level High Level RIN Horizontal and Vertical Pull-Up Resistor Pins 33,38 200 kΩ VOut Output Voltage (Pins 35,36,37) Low level High Level 0 5 V V TfrOut Falling and Rising Output CMOS Buffer Pins 35,36,37 Cout = 20pF 100 ns VHlock Horizontal 1st PLL Lock Output Status (Pin 37) Locked Unlocked 0 5 V V VoutT Extracted Vsync Integration Time (% of TH) on H/V Composite or S/G Pin 35, C0 = 820pF 35 % V 0.8 2.2 26 V V 5/30 9106A-05.TBL Symbol TDA9106A I2C READ/WRITE Electrical Characteristics (VDD = 5V,Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit I2C PROCESSOR Fscl Maximum Clock Frequency Pin 40 400 kHz Tlow Low period of the SCL Clock Pin 40 1.3 µs Thigh High period of the SCL Clock Pin 40 0.6 µs Vinth SDA and SCL Input Threshold Pins 40,41 VACK Acknowledge Output Voltage on SDA input with 3mA Pin 41 2.2 V 0.4 V Max. Unit See also I2C Table Control and I2C Sub Address Control HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. VCO R0(Min.) Minimum Oscillator Resistor Pin 11 6 C0(Min.) Minimum Oscillator Capacitor Pin 10 390 F(Max.) Maximum Oscillator Frequency kΩ pF 150 kHz OUTPUT SECTION I6m HOI1 HOI2 Maximum Input Peak Current Pin 6 2 mA Horizontal Drive Output Maximum Current Pin 20 Pin 21 Sourced current Sunk current 20 20 mA mA Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit V SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage Pin 18 10.8 12 13.2 VDD Supply Voltage Pin 39 4.5 5 5.5 ICC Supply Current Pin 18 IDD 50 V mA Supply Current Pin 39 VREF-H Horizontal Reference Voltage Pin 5, I = 5mA 7.4 8 8.6 VREF-V Vertical Reference Voltage Pin 5, I = 5mA 7.4 8 8.6 V IREF-H Max. Sourced Current on VREF-H Pin 5 5 mA IREF-V Max. Sourced Current on VREF-V Pin 26 5 mA 6/30 mA V 9106A-05.TBL 5 TDA9106A HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 1st PLL SECTION HpolT Polarity Integration Delay VVCO VCO Control Voltage (Pin12) 0.75 VREF-H = 8V f0 fH(Max.) ms VREF-H / 6 6.2 V V Vcog VCO Gain (Pin 12) R0 = 6.49kΩ, C0 = 820pF, dF/dV = 1/11R0C0 17 kHz/V Hph Horizontal Phase Adjustment % of Horizontal Period ±10 % Horizontal Phase Decoupling Output Minimum Value Typical Value Maximum Value Sub-Address 01, Pin 14 Byte x1111111 Byte x1000000 Byte x0000000 2.8 3.4 4.0 V V V Free Running Frequency R0 = 6.49kΩ, C0 = 820pF, f0 = 0.97/8R0C 0 22.3 kHz -150 ppm/C Hphmin Hphtyp Hphmax f0 dF0/dT CR PLLinh SFF FC1 FC2 Free Running Frequency Thermal Drift (No drift on external components) PLL1 Capture Range PLL1 Inhibition (Pin3) Safe Forced Frequency SF1 Byte 11xxxxxx SF2 Byte 10xxxxxx VCO Sawtooth Level High FC1=(4.VREF-H)/5 Low FC2=(VREF-H)/5 R0 = 6.49kΩ, C0 = 820pF, from f0+0.5kHz to 4.5F0 fH(Min.) fH(Max.) Typ Threshold = 1.6V PLL ON PLL OFF 23.5 kHz kHz 0.8 V V 100 2 Sub-Address 02 2F0 3F0 Pin 9 To filter Pin 8 To filter 6.4 1.6 V V FBth Hjit Flyback Input Threshold Voltage (Pin 6) 0.65 Horizontal Jitter (see Pins 8-9 filtering) Horizontal Drive Output Duty-Cycle (Pin 20 or 21) (see Note 1) 0.75 V TBD ppm 48 % XRAYth X-RAY Protection Input Threshold Voltage Pin 15 8 V Vphi2 Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4) Low Level High Level 1.6 4.0 V V VSCinh Threshold Voltage To Stop H-Out,V-Out when V CC < VSCinh Pin 18 7.5 V IHblk Maximum Horizontal Blanking Output Current I22 VHblk Horizontal Blanking Output Low Level (Blanking ON) V22 with I22 = 10mA HDvd HDem Horizontal Drive Output Low Level (Pin 20 to GND) High Level (Pin 21 to VCC=12V) V21-V20, IOUT = 20mA V20, IOUT = 20mA 9.5 10 mA 0.25 0.5 V 1.1 10 1.7 V V Notes : 1. Duty Cycle is the ratio of power transistor OFF time to period. Power transistor is OFF when output transistor is OFF. 2. Initial Condition for Safe Operation Start Up (Max. duty cycle). 7/30 9106A-05.TBL 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION TDA9106A HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit HORIZONTAL DYNAMIC FOCUS SECTION HDFst Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level HfocusCap = C0 = 820pF, fH = 90kHz, Pin 16 HDFdis Horizontal Dynamic Focus Sawtooth Discharge Width Driven by Hfly HDFDC Bottom DC Output Level RLOAD = 10kΩ, Pin 17 TDHDF DC Output Voltage Thermal Drift HDFamp Horizontal Dynamic Focus Amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 Sub-Address 03, Pin 17, fH = 90kHz, Keystone Typ Horizontal Dynamic Focus Keystone Sub-Address 04, fH = 90kHz, Typ Amp B/A A/B A/B HDFKeyst Min A/B Byte xxx11111 Typ Byte xxx10000 Max A/B Byte xxx00000 2 4.7 V V 500 ns 2 V 200 ppm/C 1 1.5 3 VPP VPP VPP 3.5 1.0 3.5 MOIRE OUTPUT Minimum Output Resistor Pin 2 VMOIRE Output Voltage (moire off), Subaddress 0F Pin 2, RMOIRE = 2kΩ Byte 0xx00000 Byte 0xx10000 Byte 0xx11111 8/30 2 kΩ 0.2 1.1 2.0 V V V 9106A-05.TBL RMOIRE TDA9106A VERTICAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Unit 6.5 V OUTPUTS SECTION VEWM Maximum EW Output Voltage Pin 31 VEWm Minimum EW Output Voltage Pin 31 1.8 VDFm Minimum Vertical Dynamic Focus Output Voltage Pin 32 1.8 V R LOAD Minimum Load for less than 1% Vertical Amplitude Drift Pin 25 65 MΩ V Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit VERTICAL RAMP SECTION Voltage at Ramp Bottom Point VREF-V=8V, Pin 27 2 V VRT Voltage at Ramp Top Point (with Sync) VREF-V Pin 27 5 V VRTF Voltage at Ramp Top Point (without Sync) Pin 27 VRT0.1 V VSTD Vertical Sawtooth Discharge Time Duration (Pin 27) With 150nF Cap 80 µs VFRF Vertical Free Running Frequency (see Notes 3 & 4) COSC (Pin 27) = 150nF Measured on Pin27, 100 Hz ASFR AUTO-SYNC Frequency C27 = 150nF ±5% See Note 5 RAFD Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude C27 = 150nF 50Hz < f and f < 165Hz 200 Rlin Ramp Linearity on Pin 27 (see Notes 3 & 4) 2.5 < V27 and V27 < 4.5V 0.5 Vpos Vertical Position Adjustment Voltage (Pin28) Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 3.2 3.5 3.8 IVPOS Max Current on Vertical Position Output Pin 28 VOR Vertical Output Voltage (peak-to-peak on Pin 29) Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111 DC Voltage on Vertical Output See Note 6, Pin 29 VoutDC 50 3.65 165 Hz TBD ppm/Hz % 3.3 ±2 3.5 2.25 3 3.75 V V V mA 2.5 V V V 3.5 V VOI Vertical Output Maximum Current (Pin29) ±5 mA dVS Max Vertical S-Correction Amplitude x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Subaddress 07 ∆V/VPP at T/4 ∆V/VPP at 3T/4 -4 +4 % % Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR SubAddress 08 Byte x1000000 Byte x1100000 Byte x1111111 -3 0 3 % % % Ccorr VflyTh Vertical Flyback Threshold Pin 30 VflyInh Inhibition of Vertical Flyback Input See Note 7, Pin 30 1 7.5 V V Notes : 3. With Register 07 at Byte x0xxxxxx (Vertical S-Correction Control) then the S correction is inhibited, consequently the sawtooth has a linear shape. 4. With Register 08 at Byte x0xxxxxx (Vertical C - Correction Control) then the C correction is inhibited, consequently the sawtooth has a linear shape. 5. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 6. VOUTDC = (7/16).VREF-V. Typically 3.5V for Vertical reference voltage typical value (8V). 7. When Pin 30 ( VREF-V) - 0.5V, Vfly input is inhibited and vertical blanking on vertical blanking output is replaced by vertical sawtooth discharge time. 9/30 9106A-05.TBL VRB TDA9106A VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit DC Output Voltage with Typ Vpos,Keystone, Corner and Corner Balance Inhibited Pin 31, see Figure 1 2.5 V EAST/WEST FUNCTION TDEWDC DC Output Voltage Thermal Drift See Note 8 100 ppm/C EWpara Parabola Amplitude with Vamp Max, V-Pos Typ, Keystone, Corner and Corner Balance Inhibited Subaddress 09 Byte 1x111111 Byte 1x100000 Byte 1x000000 2.6 1.4 0 V V V Parabola Amplitude Function of V-AMP Control (tracking between V-AMP and E/W) with Typ Vpos, Keystone, Corner and Corner Balance Inhibited, EW Typ Amplitude (see Note 9) Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 0.45 0.8 1.4 V V V Keystone Adjustment Capability with Typ Vpos, Corner and Corner Balance Inhibited, EW Inhibited and Vertical Amplitude Max (see Note 9 and Figure 4) Subaddress 0A Byte 10000000 Byte 11111111 1 1 VPP VPP Intrinsic Keystone Function of V-POS Control (tracking between V-POS and EW) with Corner and Corner Balance Inhibited, EW Max Amplitude and Vertical Amplitude Max (see Note 9) A/B Ratio B/A Ratio Subaddress 06 Max Corner Correction Amplitude with Vamp Max, V-POS Typ, EWamp, Keystone and Corner Balance Inhibited (see Note 9) Subaddress 0B ∆EWout at T/6, 5T/6 Byte x1111111 Byte x1000000 +0.2 -0.2 V V Max Corner Balance Correction Amplitude with Vamp Max, V-POS Typ, EWamp, Keystone and Corner Inhibited Subaddress 0C (see Note 9) Byte 01111111 ∆EWout at T/4 ∆EWout at 3T/4 +0.2 -0.2 V V Byte 01000000 ∆EWout at T/4 ∆EWout at 3T/4 -0.2 +0.2 V V EWtrack KeyAdj KeyTrack Corner Max Corner BalMax Byte x0000000 Byte x1111111 0.5 0.5 INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION SPBpara SPBtrack ParAdj Partrack Side Pin Balance Parabola Amplitude (Figure 2) with Vamp Max, V-POS Typ and Parallelogram Inhibited (see Notes 9 & 10) Subaddress 0D Byte x1111111 Byte x1000000 1.4 -1.4 %TH %TH Side Pin Balance Parabola Amplitude function of Vamp Control (tracking between Vamp and SPB) with SPB Max, V-POS Typ and Parallelogram Inhibited (see Notes 9 & 10) Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 0.5 0.9 1.4 %TH %TH %TH Parallelogram Adjustment Capability with Vamp Max, V-POS Typ and SPB Inhibited (see Notes 9, 10 & 11) Subaddress 0E Byte x1111111 Byte x1000000 1.4 -1.4 %TH %TH Intrinsic Parallelogram Function of Vpos Control (tracking between V-Pos and DHPC) with Vamp Max, SPB Max and Parallelogram Inhibited (see Notes 9 & 10) A/B Ratio B/A Ratio Subaddress 06 Byte x0000000 Byte x1111111 Notes : 8. These parameters are not tested on each unit. They are measured during our internal qualification 9. Refers to Notes 3 & 4 from last section. 10.TH is the Horizontal PLL Period Duration. 11.Figure 2 is representing effect of dynamic horizontal phase control. 10/30 0.5 0.5 9106A-05.TBL EWDC TDA9106A VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit VERTICAL DYNAMIC FOCUS FUNCTION VDFDC DC Output Voltage with V-Pos Typ See Figure 3 6 V DC Output Voltage Thermal Drift See Note 12 100 ppm/C VDFAMP Parabola Amplitude Function of Vamp (tracking between Vamp and VDF) with V-Pos Typ (see Figure 3) (see Note 13) Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 0.9 1.6 2.5 V V V Parabola Assymetry Function of VPos Control (tracking between V-Pos and VDF) with Vamp Max. (see Note 13) Subaddress 06 Byte x0000000 Byte x1111111 0.5 0.5 VDFKEY 9106A-05.TBL TDVDFDC Notes : 12. Parameter not tested on each unit but measured during our internal qualification procedure including batches coming from corners of our process and also temperature characterization. 13. S and C corrections are inhibited so the output sawtooth has a linear shape. Figure 1 : E/W Output Figure 2 : Dynamic Horizontal Phase Control Output B B 9106A-03.EPS EWPARA A EWDC Figure 3 : Vertical Dynamic Focus Function SPBPARA Figure 4 : DHPCDC 9106A-04.EPS A Keystone Effect on E/W Output (PCC Inhibited) A B Keyadj 9106-06A.EPS VDFAMP 9106A-05.EPS VDFDC 11/30 TDA9106A TYPICAL VERTICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification Picture Image 2.25V 10000000 Vertical Size 05 29 3.75V 11111111 Vertical Position DC Control 06 28 x0000000 x1000000 x1111111 3.2V 3.5V 3.8V x0xxxxxx Inhibited Vertical S Linearity 07 ∆V 29 x1111111 VPP x1000000 Vertical C Linearity 08 VPP ∆V ∆V = 3% V PP 29 ∆V x1111111 VPP ∆V = 3% V PP 12/30 9106A-06.TBL / 9106A-07.EPS TO 9106A-13.EPS ∆V = 4% V PP TDA9106A GEOMETRY OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification EWamp Typ. 3.75V 2.75V 10000000 Trapezoid Control 0A Picture Image 2.5V 31 3.75V 2.75V 11111111 2.5V Keystone Inhibited Pin Cushion Control 1x000000 09 2.5V 0V 31 2.5V 1x111111 SPB Inhibited x1000000 0E x1111111 Parallelogram Inhibited Side Pin Balance Control 1.4% TH 3.7V 1.4% TH 3.7V 1.4% TH X10000000 0D Internal 1.4% TH x1111111 Vertical Dynamic Focus 3.7V Internal 9106A-07.TBL / 9106A-14.EPS TO 9106A-22.EPS Parrallelogram Control 3.7V 6V 32 2.5V 13/30 TDA9106A GEOMETRY OUTPUT WAVEFORMS (continued) Sub Address Pin Byte EWamp Typ. Specification Corner effect without Corner x1111111 Corner Control 0B 31 01000000 EWamp Typ. 10000000 Corner Balance Control 0C Picture Image Corner effect Corner effect 31 Corner effect 11111111 Note : The specification of output voltage is indicated on 3.75VPP vertical sawtooth output condition.The output voltage depends on vertical sawtooth output voltage. 14/30 9106A-07.TBL / 9106A-23.EPS TO 9106A-30.EPS Function TDA9106A I2C BUS ADDRESS TABLE Sub Address Definition Slave Address (8C) : Write Mode D8 D7 D6 D5 D4 D3 D2 D1 0 x x x x 0 0 0 0 Horizontal Drive Selection 1 x x x x 0 0 0 1 Horizontal Position 2 x x x x 0 0 1 0 Safety Frequency 3 x x x x 0 0 1 1 Synchro Priority / Horizontal Focus Amplitude 4 x x x x 0 1 0 0 Refresh / Horizontal Focus Keystone 5 x x x x 0 1 0 1 Vertical Ramp Amplitude 6 x x x x 0 1 1 0 Vertical Position Adjustment 7 x x x x 0 1 1 1 S Correction 8 x x x x 1 0 0 0 C Correction 9 x x x x 1 0 0 1 E/W Amplitude A x x x x 1 0 1 0 E/W Keystone B x x x x 1 0 1 1 Cbow Corner C x x x x 1 1 0 0 Spin Corner D x x x x 1 1 0 1 Side Pin Balance E x x x x 1 1 1 0 Parallelogram F x x x x 1 1 1 1 Moire Control Amplitude Slave Address (8D) : Read Mode 0 D8 D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Synchro and Polarity Detection 15/30 TDA9106A I2C BUS ADDRESS TABLE (continued) Table : Register Map D8 D7 D6 D5 D4 D3 D2 D1 [0] [0] WRITE MODE 00 Blk Sel 1, Blk [0] 01 Xray 1, reset [0] 02 Safety Frequency 1, on 1, F0 x 2 [0], off [0], F0 x 3 03 04 05 HDrive 0, off [1], on Horizontal Phase Adjustment [1] Sync Priority 0, Vextr 0, S/G [1], Vin [1], H/V Detect Refresh [0], off Vramp 0, off [1], on 06 [1] C Select 1, on [0] 08 [0] [0] [0] Horizontal Focus Amplitude [1] [0] [0] [0] [0] Horizontal Focus Keystone [1] [0] [0] [0] [0] Vertical Ramp Amplitude Adjustment [1] S Select 1, on [0] 07 09 EW Sel 0, off [1] 0A EW Key 0, off [1] [1] 0B Test H 1, on [0], off Cbow Sel 1, on [0] 0C Test V 1, on [0], off Spin Sel 1, on [0] [0] [0] [0] [0] [0] [0] [0] Vertical Position Adjustment [0] [0] [0] S Correction [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] C Correction [1] [0] [1] [0] [0] [0] East/West Amplitude [0] East/West Keystone 0D SPB Sel 0, off [1] 0E Parallelo 0, off [1] 0F [0] [0] [0] [0] Cbow Corner [1] [0] [0] [0] Spin Corner [1] [0] [0] [0] Side Pin Balance [1] [0] [0] [0] Parallelogram [1] Moire 1, on [0], off [0] [0] [0] Moire Control [0] [0] [0] READ MODE 00 Hlock 0, on [1], no [ ] initial value 16/30 Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection H/V pol V pol [1], negative [1], negative Vext det [0], no det Synchro Detection H det V det [0], no det [0], no det TDA9106A OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are respectively 12V and 5V. Perfect operationis obtained if VCC and VDD are maintened in the limits : 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputsof the circuit are inhibited if VCC is less than 7.5V typically. In the same manner,VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C Control Table for power on reset). In order to have a verygood powersupply rejection, the circuit is internally powered by several internal voltage references (the unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal one. If needed,these voltage references can be used (until load is less than 5mA).Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connectedto ground,in order to minimize the noise and consequently the “jitter” on vertical and horizontal output signals. I.2 - I2C Control TDA9106A belongs to the I2C controlled device family, instead of being controlled by DC voltages on dedicated control pins, each adjustment can be realized through the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1 byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address(7 bits-8C) and the read/write bit (0 write - 1 read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the thirdbyte the corresponding data byte.It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress.It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 14 adjustment capabilities : 1 for Horizontal part, 4 for Vertical one, 2 for E/W correction, 2 for original Corner correction, 2 for the Dynamic Horizontal phase control,1 for Moire option and 2 for Horizontal Dynamic Focus. 20 bits are also dedicated to several controls (ON/OFF, Horizontal Safety Frequency, Synchro Priority, Detection Refresh and Xray reset). I.4 - Read Mode During read mode the second byte transmits the reply information. The reply byte contains Horizontal and Vertical Lock/Unlock status, Xray activated or not, the Horizontal and Vertical polarity detection. It also contains Synchro detection status that is useful for µP to assign Sync priority. A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and SCL) to high impedance. 2 See I C Subaddress and control tables. I.5 - Synchro Processor The internal Sync Processor allows the TDA9106A to accept any kind of input synchro signals : - separated Horizontal & Vertical TTL-compatible sync signals, - composite Horizontal &Vertical TTL-compatible sync signals, - sync on green or composite video signal. 17/30 TDA9106A OPERATING DESCRIPTION (continued) H/V det V det Sync priority Subaddress 03 D8 D7 Figure 5 1.6V R C S/G 1 1kΩ IREF (Typ.) = 10µA Comment TDA9106 Synchro type Yes Yes 1 1 Separated H & V Yes No 0 1 Composite TTL H&V No No 0 0 Sync on Green Of course, when choice is done, one can refresh the synchro detections and verify that extracted Vsync is present and that no synchro type change occured. Synchro processor is also giving synchro polarity information. I.7 - IC status TheIC can inform the MCUeither the 1st Horizontal PLLor Vertical sectionare locked or not, and if Xray has been activated. This last status permits to the MCU : - reset the Xray internal latch decreasing the VCC supply - directly reset throw the I2C interface. 18/30 I.8 - Synchro Inputs Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysterisis to avoid erratic detection. It includes pull up resistor to VDD. Vertical sync extractor is included for composite sync or composite video.Applicationengineer must adapt resistor R and capacitor C dedicated to its application. Resistor R is fixed by detection threshold wanted : R < (VTHRESHOLD / IREF) Then C is determined by maximum pulse width to detect (in general, vertical sync width) : RC > (max pulse width) I.9 - Synchro Processor Outputs Synchro processor delivers on 3 TTL-compatible CMOS outputs the following signals : - Hout as follow : Sync Mode Separated TTL Composite S/G Hout Mode Horizontal TTL Composite Composite Hout Polarity Same as Input Same as Input Negative - Vsyncout is either vertical extracted pulse output or Vsyncin input. It keeps the input polarity. - Hlockoutis theHorizontal1st PLLstatus: 0Vwhen locked. It permits MCU to adjust free running frequency and optimizes the IC performance. 9106A-31.EPS I.6 - Sync Identification Status TDA9106Ais able to feed back to the MCU (thanks to I2C) the Sync input status (sync identification) so that the MCU can chooseSync priority throughI 2C. As extracted Vertical sync pulse is performedwhen choice already occured and when 12V is supplied, we recommend to use the deviceas following :(that means that even in Power management mode the IC is able to inform MCU on detected synchro signals due to its 5V supply). First, refresh Synchrodetection by I2C. Then check the status of H/V det and Vdet by I2C read. Sync priority choice should be : Table 1 : Sync Priority Choice TDA9106A OPERATING DESCRIPTION (continued) II - HORIZONTAL PART II.1 - Internal Input Conditions Horizontal part is internally fed by synchro processor with a digital signal. corresponding to horizontal synchro pulses or to TTL composite input. Concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7µs. 9106A-32.EPS Figure 6 An other integration is able to extract vertical pulse of composite synchroif duty cycle is more than 25% (typically d = 35%). C TRAMEXT d d The last feature performed is the equalizing pulses removingto avoidparasitic pulseson phasecomparator input which is intolerent to wrong or missing pulse. 9106A-33.EPS Figure 7 designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a “charge pump”, composed of two current sources sunk and sourced (I = 1mA Typ. when locked, I = 140µA when unlocked). This difference between lock/unlock permits a smooth catching of horizontal frequency by PLL1. This effectis reinforcedby an internaloriginal slow down system when PLL1 is locked avoiding Horizontal too fast frequency change. The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A “CRC” filter is generally used (see Figure 8). PLL1 is internally inhibited during extractedvertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 9). For particular synchro type, MCU can drive Pin 3 to high level (TTL compatible input) to inhibit PLL1. It can also be used to avoid PLL1 locking on synchro inputs if a “dangerous”mode is detected by the MCU. The VCO uses an externalRC network. It delivers a linear sawtooth obtainedby chargeand discharge of the capacitor, by a current proportionnal to the currentin the resistor. Typicalthresholdsofsawtoothare 1.6Vand 6.4V. Thesetwo levels are accessibleto be filtered as on Figure 10 to improve jitter. Figure 8 PLL1F 12 9106A-34.EPS II.2 - PLL1 The PLL1 is composed of a phase comparator, an externalfilter and a voltagecontrolledoscillator (VCO). The phase comparator is a “phase frequency”type 19/30 TDA9106A OPERATING DESCRIPTION (continued) Figure 9 : PLL1 Block Diagram H-LOCKCAP PLL1INHIB PLL1F LOCK/UNLOCK STATUS 13 S/G 1 LOCKDET VSYNCIN 33 H/HVIN 38 3 12 R0 C0 11 10 TRAMEXT SMFE * High SYNC PROCESSOR CHARGE PUMP COMP1 E2 PLL INHIBITION VCO Low H-POS OSC 14 PHASE ADJUST * SMFE : Safety Frequency Mode Enable I2C HPOS Adj. 9106A-35.EPS TRAMEXT Figure 10 : Details of VCO I0 9 2 6.4V RS FLIP FLOP I0 Loop Filter 12 47nF 47nF 8 1.6V 4 I0 11 6.4V 9106A-36.EPS 10 R0 C0 1.6V 0 0.875T T The control voltage of the VCO is typically comprised between 1.33V and 6V (see Figure 10). The theorical frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. The synchro frequency has to be always higher than the free running frequency. As an example for a synchro range from 24kHz to 100kHz, the suggested free running frequency is 23kHz. An other feature is the capability for MCU to force horizontal frequency through I2C to 2xF0 or 3xF0 (for burn in mode or safety requirement).In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is forced to 2.66Vfor 2xF0 or 4.0V for 3xF0. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage I2C adjustable between 2.8V and 4.0V (corresponding to ± 10%) (see Figure 11). This voltage has to be filtered on Pin 14 so as to optimize jitter. 20/30 The TDA9106A also includes a Lock/Unlock identification block which senses in real time wheither PLL1 is locked on the incoming horizontal sync signal or not. The resulting information is available on Hlockout (see Synchro Processor). The block Figure 11 : PLL1 Timing Diagram H Osc Sawtooth 7/8TH 1/8TH 6.4V 2.8V<Vb<4.0V Vb 1.6V Phase REF1 H Synchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A ± T/10 phase adjustment is possible. 9106A-37.EPS (1.3V < V12 < 6V) TDA9106A OPERATING DESCRIPTION (continued) Figure 12 : LOCK/UNLOCK Block Diagram 5V 37 HLOCKOUT From Phase Comparator 20kΩ H-Lock CAP 13 6.5V 220nF NOR1 B 9106A-38.EPS A 6V It is important to notice that Pin 13 is not an output pin but is only used for filtering purpose (see Figure 12). The lock/unlock information is also available throw I2C read. function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drive the charge pump). When PLL1 is locked, on point A there is a very small negative pulse (about 100ns) at each horizontal cycle, so after RC filter, there is a high level on Pin 13 which forces Hlockout to low level. Hysterisis comparator detects locking when Pin 13 is reaching 6.5V and unlocking when Pin 13 is decreasing to 6.0V. When PLL1 is unlocked, the 100ns negative pulse on A becomes much larger and consequently the average level on Pin 13 decreases. It forces Hlockout to go high. The Pin 13 status is approximately the following : - near 0V when there is no H-Sync - between 0 and 4V with H-Sync frequency different from VCO - between 4 to 8 V when VCO frequency reaches H-Sync one (but not already in phase) - near 8V when PLL1 is locked. II.3 - PLL2 Figure 14 : Flyback Input Electrical Diagram 400Ω 7/8TH 9106A-40.EPS 20kΩ GND 0V The PLL2 ensures a constant position of the shaped flyback signal in comparion with the sawtooth of the VCO (Figure 13). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump with ± 0.5mA (typ.) output current. The flyback input is composed of an NPN transistor. This input must be current driven. The maximum rec omma nd ed input current is 2mA (see Figure 14). The duty cycle is fixed and equal to 48% of horizontal-period. Figure 13 : PLL2 Timing Diagram H Osc Sawtooth Q1 HFLY 6 1/8TH 6.4V 4.0V 1.6V Flyback Maximum storage time is about 43.75% - (Tfly/2.TH). Typically, Tfly/TH is around20% thatmeansTs max is around 33.75%. Internally Shaped Flyback II.4 - Output Section Ts Duty Cycle 48% 9106A-39.EPS H Drive The H-drive signal is transmitted to the output througha shapingblock ensuringTs and dutycycle. In order to secure scanning power part operation, the output is inhibited in the following circumstances : 21/30 TDA9106A OPERATING DESCRIPTION (continued) bipolar transistor. Both the collector and the emittor are accessible (see Figure 16). Theoutput Darlington is in off-statewhen the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltage drop of the output darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interfacehas to be designed between the circuit and the power transistor which can be of bipolar or MOS type. Figure 16 : Output stage simplified diagram, showing the two possibilities of connection 21 VCC H-DRIVE 20 VCC 21 9106A-41.EPS H-DRIVE 20 - VCC too low - Xray protection activated - During horizontal flyback - I2C bit control (voluntary inhibition by MCU). The output stage is composed of a NPN Darlington II.5 - X-RAY Protection The activation of the X-Ray protection is obtained by application of a high level on the X-Ray input (Pin 15 > 8V). The consequenciesof X-Ray protection are : - inhibition of H-Drive output - activation of horizontal blanking output. - activation of vertical blanking output. The reset of this protection is obtained either by VCC switch off or I2C resetby MCU (see Figure 17). Figure 17 : Safety Functions Block Diagram VCC Checking I2C Drive on/off HORIZONTAL OUTPUT INHIBITION VCC Ref XRAY Protection VCC off or I C Reset S R Horizontal Flyback I2C Blanking 0.7V HORIZONTAL BLANKING OUTPUT I2C SFME Horizontal Unlock Horizontal Free Running Detection Vertical Flyback Vertical Sync Vertical Sawtooth Retrace Vertical Free Running Status Vertical Unlock I2C Ramp on/off 22/30 VERTICAL OUTPUT INHIBITION Q LOGIC BLOCK VERTICAL BLANKING OUTPUT 9106A-42.EPS XRAY 2 I2C Ramp on/off TDA9106A OPERATING DESCRIPTION (continued) Figure 18 Horizontal Flyback Internal Trigged Horizontal Flyback 4.7V Horizontal Focus Cap Sawtooth 2V 9106A-43.EPS Horizontal Dynamic Focus Parabola Output 400ns 2V Moire Output II.6 - Horizontal Dynamic Focus II.7 - Moire Output TDA9106A delivers an horizontal parabola wave form on Pin 17. This parabola is performed from a sawtoothin phasewith flyback pulse.Thissawtooth is present on Pin 16 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry(keystone)and amplitude are I2C adjustable (see Figure 18).This signal has to be connected to the CRT focusing grids and mixed with vertical dynamic focus. The moire output is intented to correct a beat between horizontal video pixel period and actual CRT pixel width. The moire signal is a combinationof Horizontal and Vertical frequency signals. To achieve a moire cancellation, it has to be connected to any point on the chassis controlling the horizontalposition.We recommend to introducethis Figure 19 : Moire Function Block Diagram H-FLY Ck Q D Rst Q 23 Monostable Ck D Q Q 9106A-44.EPS V-SYNC Figure 20 : Moire Output Waveform EVEN FRAME H V MOIRE ODD FRAME H 9106A-45.EPS V MOIRE 23/30 TDA9106A OPERATING DESCRIPTION (continued) “ Horizontal Controlled Jitter” on the relative ground of PLL2 capacitor where this “controlled jitter” frequency type will directly affect the horizontal position.The amplitude of the signal is I2C adjustable. One point to notice is : (keystone adjustment). - in case H-Moire is not necessary in the applicaCorner and Corner Balance corrections may be tion, H-Moire output (Pin 2) can be turned to as a added to the E/W one. These are respectively 3rd 5 bits digital to analog converter output (0.3V to and 2nd order waveforms. 2.2V V output voltage), In order to keep a good screen geometry for any - in case of no use in application, this pin must be end user preferences adjustment we implemented left high impedance(or resistor to ground). the “geometry tracking”. Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with III - VERTICAL PART maximum vertical amplitude max or min vertical III.1 - Geometric Corrections position and maximum gain on the DAC control may lead to the output stages saturation. This must The principle is represented in Figure 21. be avoided by limiting the output voltage by aproStarting from the vertical ramp, a parabola shaped priate I2C registers values. current is generated for E/W correction, dynamic For E/Wpart and Dynamic Horizontal phase control horizontal phase control correction, and vertical part, a sawtooth shaped differential current in the dynamic Focus correction. following form is generated : The base of the parabola generator is an analog ∆I’ = k’ ⋅ (VOUT - VDCOUT)2 multiplier the output current of which is equal to : Then ∆I and ∆I’ are added together and converted ∆I = k ⋅ (VOUT - VDCOUT)2 into voltage for the E/W part. Where Vout is the vertical output ramp, typically comprised between 2 and 5V, Vdcout is the vertical Each of the four E/W components or the two DyDC output adjustable in the range 3.2V ≥ 3.8V in namic Horizontal phase control ones may be inhiborder to generatea dissymetric parabolaif required ited by their own I2C select bit. Figure 21 : Geometric Corrections Principle 2 32 VDCOUT Vertical Dynamic Focus Output Vertical Ramp VOUT EW amp VDCIN Keystone 31 EW Output Vertical Ramp VOSC Corner VMID VDCOUT Corner Balance To Horizontal Phase VDCOUT Sidepin Balance Output Current Parallelogram 24/30 9106A-46.EPS Sidepin amp TDA9106A OPERATING DESCRIPTION (continued) typically 3.5V K1 is adjustable by EW amplitude I2C register K2 is adjustable by Keystone I2C register K3 is adjustable by Cbow Corner I2C register K4 is adjustable by Spin Corner I2C register The E/W parabola is available on Pin 31 by the way of an emitter follower which has to be biased by an external resistor (10kΩ). It can be DC coupled with external circuitry. The output connection of the vertical Dynamic Focus is the same as the E/W one. This reverse parabola is available on Pin 32. Dynamic Horizontal phase control current drives internally the H-position, moving the Hfly position on the Horizontal sawtooth in the range ± 2.8% Th both on SidePin Balance and Parallelogram. III.3 - Dynamic Horizontal Phase Control IOUT = K5 (VOUT - VDCOUT )2 + K6 (VOUT - VDCOUT) K5 is adjustable by SidePin Balance I2C register K6 is adjustable by Parallelogram I2C register III.4 - Vertical Dynamic Focus VFOCOUT = 6V - 0.7 (VOUT - VDCOUT)2 No adjustment is available for this part except by means of tracking. III.2 - EW 2 EWOUT = 2.5V + K1 (VOUT - VDCOUT) + K2 (VOUT - VDCOUT) + K3 (VOUT - VDCOUT)2 |VOSC - VMID| + K4 (VOUT - VDCOUT) |VOSC - VMID| III.5 - Vertical Sawtooth Generator VOSC is the ramp Pin 27 and VMID the middle of it, Figure 22 : Vertical Part Block Diagram CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 27 S/G 1 25 VSYNCIN 33 SYNC PROCESSOR SAMPLING SAMP. CAP S CORRECTION OSCILLATOR VS_AMP SUB07/6bits POLARITY COR_C SUB08/6bits C CORRECTION Vlow Corner SUB0B/6bits Corner Balance SUB0C/6bits Sawth. Disch. 29 VERT_OUT VERT_AMP SUB05/7bits CORNER PARABOLA GENERATOR 31 EW_OUT EW_CENT EW_AMP SUB0A/6bitsSUB09/6bits SPB_OUT Internal Signal to PLL2 PARAL SUB0E/6bits SPB_AMP SUB0D/6bits 9106A-47.EPS H/HVIN 38 OSC CAP DISCH. 32 V_FOCUS 25/30 TDA9106A OPERATING DESCRIPTION (continued) The vertical part generates a fixed amplitude ramp which can be affectedby S and C correction shape. Then, the amplitude of this ramp is adjustedto drive an external power stage (see Figure 22). The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. Its typical value is : V26 = VREF = 8V The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, Vl (Vl = VREF/4) and VH (VH = 5/8 x VREF). When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 106Hz. Typical free running frequency can be calculated by : f0 (Hz) = 1.6 e−5 ⋅ 1 COSC A negative or positive TTL level pulse applied on Pin 33 (VSYNC) as well as a TTL composite sync on Pin 38 or a Sync on Green signal on Pin 1 can synchronise the ramp in the range [fmin , fmax]. This frequency range depends on the external capacitor connected on Pin 27. A capacitor in the range [150nF, 220nF] ± 5% is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is automaticaly synchronized but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest point of the ramp (Pin 27) is sampled on the sampling capacitor connected on Pin 25 at each clock pulse and a transconductanceamplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant and frequency independant. The read status register enables to have the vertical Lock-Unlock and the vertical Sync Polarity in- 26/30 formations. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Good stability of the internal closed loop is reached by a 470nF ± 5% capacitorvalue on Pin25 (VAGC). Pin 30, VFLY is the vertical flyback input used to generate the vertical blanking signal on Pin 23. If Vfly is not used, (VREF - 0.5), at minimum, must be connected to this input. In such case, the vertical blanking output will be activated by the vertical sync input signal and resetted by the end of vertical sawtooth discharging pulse. III.6 - I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by their Select bit. At the end, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 29 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The DC value of this ramp is kept constant in the frequency range, for any correction applied on it. its typical value is VMID = 7/16 ⋅ VREF. A DC voltage is available on Pin 28 (VDCOUT). It is driven by its own I2C register (vertical Position). Its value is VDCOUT = 7/16 ⋅ VREF ± 300mV. So the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. III.7 - Basic Equations In first approximation,the amplitude of the ramp on Pin 29 (Vout) is : VOUT - VMID = (VOSC - VMID) ⋅ (1 + 0.25 (VAMP)) with VMID = 7/16 ⋅ VREF ; typically 3.5V, the middle value of the ramp on Pin 27 VOSC = V27 , ramp with fixed amplitude VAMP is -1 for minimum vertical amplitude register TDA9106A APPLICATION DIAGRAMS Figure 23 : Demonstration Board +12V CC2 10µF ICC1 - MC14528 CC1 100nF J16 1 J15 +5V CC4 V CC 16 1 TA1 47pF +12V 2 TA2 TB1 15 3 CDA TB2 14 4 IA CDB 13 5 IA IB 12 IB 11 7 QA QB 10 8 GND QB 9 J14 IC3 - STV9422 CC3 PC1 47kΩ 47pF C45 10µF 24 PWM7 22pF C40 R39 4.7kΩ +12V +12V C44 10pF R22 C26 1.5kΩ 1µF R42 100Ω 22pF IC2 TDA9106 R41 100Ω R49 22kΩ +5V 1 R48 1kΩ R29 4.7kΩ SYNC/G GNDD 42 R44 2 MOIRE SDA 41 10kΩ PWM0 1 23 PWM6 PWM1 2 22 TEST FBLK 3 21 B VSYNC 4 20 G HSYNC 5 19 R V DD 6 18 GND PXCK 7 17 RST CKOUT 8 16 SDA XTALOUT 9 15 SCL J13 10kΩ PLLINH SCL 40 L2 10µH +5V C43 47µF C7 X1 8MHz XTALIN 10 4 PLL2C +5V 39 JP1 R20 C7 10Ω 22nF 14 PWM5 PWM2 11 13 PWM4 PWM3 12 1 TILT TP9 3 C42 1µF R43 C39 +5V J10 6 QA 1 4 3 2 1 PC2 47kΩ 33pF C7 33pF L1 10µH +5V C30 100µF C32 100nF TP1 HREF J11 R10 10kΩ R35 10kΩ 5 C25 33pF C33 100nF HREF HSYNC H/HVIN 38 C27 47µF TP17 6 HFLY 7 HGND HLOCKOUT 37 TP10 HOUT 36 TP11 C16 220pF R30 10kΩ R31 C22 33pF J8 R8 10kΩ 1 27kΩ +12V TP15 8 HFLY C21 FC2 9 FC1 R15 1kΩ R17 270kΩ Q1 Q2 BC557 TEST 34 J12 10 C0 820pF 5% R9 470Ω R18 39kΩ Q3 TIP122 TP16 R23 11 R0 E/W POWER STAGE V_FOCUS V_FOCUS 32 6.49kΩ 1% J2 R28 10kΩ 10nF 12 PLL1F 1 D2 1N4148 EWOUT 31 C14 470µF D1 1N4004 C31 R36 1.8kΩ +12V C9 100nF -12V R32 13 HLOCKCAP VFLY 30 C18 100µF 36V 4.7kΩ 220nF 1 J3 TP8 4.7µF C17 E/W 220pF R33 4.7kΩ TP17 VSYNCIN 33 R38 2.2Ω 1W C11 VSYNC C28 J1 R19 270kΩ 1 R34 1kΩ 47nF C13 R37 27kΩ C36 1µF TP12 VSYNCOUT 35 C23 47nF R16 TP7 15kΩ 1µF J7 12kΩ VREF 15 XRAYIN VDCOUT 28 R45 C34 V_FOCUS 820pF 16 H_FOCUSC 17 H_FOCUS 1kΩ 150nF VERTICAL DEFLECTION STAGE C15 +12V C5 100µF VREF VREF 26 R24 10kΩ C6 100nF 18 VCC VAGCCAP 25 470nF 19 GND C2 100nF R5 21 HOUTCOL H_BLKOUT 22 + 12V R21 3.9kΩ TP2 TP8 HBLK VBLK R27 3.9kΩ 3 5 C1 220nF C10 -12V 470µF C8 100nF R11 220Ω 1/2W R47 T1 82Ω 3W G5676-00 L3 10µH +12V C20 1µF R13 1kΩ C35 HORIZONTAL DRIVER STAGE V YOKE R4 1Ω 1/2W 5.6kΩ 100nF V_BLKOUT 23 IC1 TDA8172 4 R3 1.5Ω C3 47µF VGND 24 20 HOUTEM 6 C41 470pF 12kΩ R25 1 1 C12 VCAP 27 33kΩ 7 R1 TP5 J18 1 2 3 2 C4 R2 5.6kΩ 100nF 33kΩ 1 DYNAMIC FOCUS J9 R40 R7 10kΩ TP14 XRAYIN VOUT 29 Q5 BC547 R6 10Ω Q4 BC557 C19 100µF 63V +24V J17 1 2 3 HDRIVE STD Q6 5N20 R12 560Ω R14 22kΩ C24 1nF TP3 TP4 1 J6 27/30 9106A-48.EPS C29 R45 14 HPOS TDA9106A APPLICATION DIAGRAMS (continued) 9106A-49.EPS Figure 24 : PCB Layout 28/30 TDA9106A APPLICATION DIAGRAMS (continued) 9106A-50.EPS Figure 25 : Components Layout 29/30 TDA9106A PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 e3 21 e2 SDIP42 Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70 2.54 Millimeters Typ. 3.81 0.46 1.02 0.25 36.83 13.72 1.778 15.24 3.30 Max. 5.08 4.57 0.56 1.14 0.38 37.08 16.00 14.48 18.54 1.52 3.56 Min. 0.020 0.120 0.0149 0.035 0.0090 1.440 0.60 0.50 0.10 Inches Typ. 0.150 0.0181 0.040 0.0098 1.450 0.540 0.070 0.60 0.130 Max. 0.200 0.180 0.0220 0.045 0.0150 1.460 0.629 0.570 0.730 0.060 0.140 Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 30/30 SDIP42.TBL 1 PMSDIP42.EPS Gage Plane