STS3DPFS40 P-CHANNEL 40V - 0.070Ω - 3A SO-8 STripFET MOSFET PLUS SCHOTTKY RECTIFIER PRELIMINARY DATA MAIN PRODUCT CHARACTERISTICS MOSFET SCHOTTKY VDSS RDS(on) ID 40 V < 0.1 Ω 3A IF(AV) VRRM V F(MAX) 3A 40 V 0.51 V DESCRIPTION This product associates the latest low voltage STripFET in p-channel version to a low drop Schottky diode. Such configuration is extremely versatile in implementing, a large variety of DC-DC converters for printers, portable equipment, and cellular phones. SO-8 INTERNAL SCHEMATIC DIAGRAM MOSFET ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 40 V Drain-gate Voltage (RGS = 20 kΩ) 40 V ± 16 V Gate- source Voltage ID Drain Current (continuos) at TC = 25°C 3 A ID Drain Current (continuos) at TC = 100°C 1.9 A Drain Current (pulsed) 12 A Total Dissipation at TC = 25°C 2 W Value Unit Repetitive Peak Reverse Voltage 40 V RMS Forward Current 20 A IDM (● ) PTOT SCHOTTKY ABSOLUTE MAXIMUM RATINGS Symbol VRRM IF(RMS) Parameter IF(AV) Average Forward Current TL = 125°C δ = 0.5 3 A IFSM Surge Non Repetitive Forward Current tp = 10 ms Sinusoidal 75 A IRRM Repetitive Peak Reverse Current tp = 2 µs F = 1kHz 1 A IRSM Non Repetitive Peak Reverse Current tp = 100 µs 1 A dv/dt Critical Rate Of Rise Of Reverse Voltage 10000 V/µs (•)Pulse width limited by safe operating area November 2000 Note: For the P-CHANNEL MOSFET actual polarity of Voltages and current has to be reversed 1/6 STS3DPFS40 THERMAL DATA Rthj-amb (*)Thermal Resistance Junction-ambient MOSFET 62.5 °C/W Rthj-amb (*)Thermal Resistance Junction-ambient SCHOTTKY Maximum 100 °C/W -65 to 150 °C 150 °C Tstg Tl Storage Temperature Range Junction Temperature (*) Mounted on FR-4 board (Steady State) MOSFET ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 16 V ±100 nA 40 V ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 1.5 A ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS = 10V Min. Typ. Max. Unit 2 3 4 V 0.070 0.1 Ω 3 A DYNAMIC Symbol gfs (1) 2/6 Parameter Test Conditions Min. Typ. Max. Unit 6 S 1190 pF Output Capacitance 200 pF Reverse Transfer Capacitance 56 pF Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 1.5 A C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 Coss Crss STS3DPFS40 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Q gd Gate-Drain Charge Test Conditions Min. VDD = 20 V, I D = 1.5 A RG = 4.7 Ω VGS = 10 V (see test circuit, Figure 3) VDD = 20 V, I D = 3 A, VGS = 10 V Typ. Max. Unit 20 ns 25 ns 24.5 33 nC 4 nC 5.5 nC SWITCHING OFF Symbol Parameter Test Condit ions Min. Typ. td(off) tf Turn-off Delay Time Fall Time VDD = 20 V, ID = 1.5 A, R G = 4.7Ω, VGS = 10 V (see test circuit, Figure 3) 100 22 td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp = 32 V, ID = 3 A, R G = 4.7Ω, VGS = 10 V 20 11 35 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) Parameter Test Conditions Min. Typ. Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 3 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD = 3 A, di/dt = 100A/µs, VDD = 15 V, T j = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current Max. Unit 3 A 12 A 2 V 34 ns 45 nC 2.6 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. SCHOTTCKY STATIC ELETTRICAL CHARACTERISTICS Symbol IR(*) VF(*) Parameter Reversed Leakage Current Forward Voltage Drop Typ. Max. Unit TJ = 25 °C , VR = 30 V TJ = 125 °C , VR = 30 V Test Conditions Min. 0.03 0.2 100 mA mA TJ = 25 °C , IF = 3 A TJ = 125 °C , IF = 3 A 0.42 0.51 0.46 V V 3/6 STS3DPFS40 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STS3DPFS40 SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.003 0.009 0.025 0.033 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch 0.064 0.85 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 c1 45 (typ.) e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 5/6 STS3DPFS40 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6