MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER DESCRIPTION M81019FP is high voltage Power MOSFET and IGBT gate driver for half bridge applications. PIN CONFIGURATION (TOP VIEW) 24 NC 1 FEATURES ¡Floating supply voltage up to 1200V ¡Low quiescent power supply current ¡Separate sink and source current output up to ±1A (typ) ¡Active Miller effect clamp NMOS with sink current up to –1A (typ) ¡Input noise filters ¡Over-current detection and output shutdown ¡High side under voltage lockout ¡FO pin which can input and output Fault signals to communicate with controllers and synchronize the shut down with other phases ¡Pb-free ¡24-Lead SSOP package HIN VB LIN HPOUT FO_RST HNOUT1 CIN HNOUT2 GND FO NC VCC NC LPOUT NC LNOUT1 NC LNOUT2 NC VNO 13 VS 12 APPLICATIONS Power MOSFET and IGBT gate driver for Medium and Micro inverter or general purpose. NC NC Outline: 24P2Q BLOCK DIAGRAM VB UV GND HPOUT HNOUT1 HNOUT2 Logic Filter VS VCC Pulse Generator HIN Interlock & Noise Filter Vreg VREG VCC LIN CIN Vref LPOUT LNOUT1 LNOUT2 Protection Logic + VNO – Filter FO_RST Vref FO Filter Aug. 2009 1 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limitation beyond which destruction of device may occur. All voltage parameters are absolute voltage reference to GND unless otherwise specified. Symbol VB VS VBS VHO VCC VNO VLO VIN VFO VCIN dVS/dt Pd Kq Rth(j-c) Tj Topr Tstg Parameter High side floating supply absolute voltage High side floating supply offset voltage High side floating supply voltage High side output voltage Low side fixed supply voltage Power ground Low side output voltage Logic input voltage FO input/output voltage CIN input voltage Allowable offset voltage slew rate Package power dissipation Linear derating factor Junction-case thermal resistance Junction temperature Operation temperature Storage temperature Test conditions VBS = VB–VS HIN, LIN, FO_RST Ta = 25°C, On PCB Ta > 25°C, On PCB Ratings Unit –0.5 ~ 1224 VB–24 ~ VB+0.5 –0.5 ~ 24 VS–0.5 ~ VB+0.5 –0.5 ~ 24 VCC–24 ~ VCC+0.5 VNO–0.5 ~ VCC+0.5 –0.5 ~ VCC+0.5 –0.5 ~ VCC+0.5 –0.5 ~ VCC+0.5 ±50 1.6 16 60 –40 ~ 125 –40 ~ 100 –40 ~ 125 V V V V V V V V V V V/ns W mW/°C °C/W °C °C °C RECOMMENDED OPERATING CONDITIONS For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND unless otherwise specified. Symbol VB VS VBS VHO Parameter Test conditions High side floating supply absolute voltage High side floating supply offset voltage High side floating supply voltage High side output voltage VCC VNO VLO VIN VFO Low side fixed supply voltage VCIN CIN input voltage VBS > 13.5V VBS = VB–VS Power ground Low side output voltage HIN, LIN, FO_RST Logic input voltage FO input/output voltage Min. VS+13.5 –5 Limits Typ. VS+15 — 13.5 VS 15 — 13.5 –0.5 VNO 0 0 — — — 5 0 — — Max. VS+20 900 20 VS+20 20 5 VCC VCC VCC 5 Unit V V V V V V V V V V Note : For proper operation, the device should be used within the recommend conditions. THERMAL DERATING FACTOR CHARACTERISTIC Package Power Dissipation Pd (W) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 Ambience Temperature (°C) Aug. 2009 2 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER TYPICAL CONNECTION DC+ Rboot Dboot VB VCC 15V HOUT HNOUT1 HIN RGOFF HNOUT2 LIN MCU/DSP Controller RGON HPOUT FO_RST Cboot 5V~15V Vout VS Other Phases DC BUS Voltage M81019FP RFO FO CFO RGON LPOUT GND LNOUT1 RGOFF LNOUT2 CIN LOUT VNO Rshunt RCIN CCIN DC- Note: If HVIC is working in high noise environment, it is recommended to connect a 1nF ceramic capacitor (CFO) to FO pin. Aug. 2009 3 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=VBS (=VB–VS)=15V, unless otherwise specified) Symbol Parameter Test conditions IFS High side leakage current VB = VS = 1200V IBS VBS quiescent supply current HIN = LIN = 0V ICC VCC quiescent supply current HIN = LIN = 0V VOH High level output voltage IO = –20mA, HPOUT, LPOUT VOL Low level output voltage VIH Min. — Limits Typ. — Max. 1.0 — 0.5 0.8 mA Unit µA — 1 1.5 mA 14.5 — — V IO = 20mA, HNOUT1, LNOUT1 — — 0.5 V High level input threshold voltage HIN, LIN, FO_RST 4.0 — — V VIL Low level input threshold voltage HIN, LIN, FO_RST — — 0.6 V IIH High level input bias current VIN = 5V 0.6 1 1.4 mA IIL Low level input bias current VIN = 0V –0.01 0 0.01 mA tFilter Input signals filter time HIN, LIN, FO_RST, FO 80 200 500 ns VIN = 0V 2.0 3.4 5 V VIN = 0V 6.0 7.6 9 V VHNO2 VLNO2 High side active Miller clamp NMOS input threshold voltage Low side active Miller clamp NMOS input threshold voltage tVNO2 Active Miller clamp NMOS filter time VIN = 0V — 400 — ns VOLFO Low level FO output voltage IFO = 1mA — 0.4 0.95 V VIHFO High level FO input threshold voltage 4.0 — — V VILFO Low level FO input threshold voltage — — 0.6 V VBSuvr VBS supply UV reset voltage 10.5 11.3 12.1 V VBSuvt VBS supply UV trip voltage 10 10.8 11.6 V VBSuvh VBS supply UV hysteresis voltage 0.2 0.5 0.8 V tVBSuv VBS supply UV filter time 4 8 16 µs VBSuvh = VBSuvr–VBSuvt VCIN CIN trip voltage 0.4 0.5 0.6 V VPOR POR trip voltage 4 5.5 7.5 V IOH Output high level short circuit pulsed current HPOUT (LPOUT) = 0V, HIN = 5V, PW < 5µs — 1 — A IOL1 Output low level short circuit pulsed current HNOUT1 (LNOUT1) = 15V, LIN = 5V, PW < 5µs — –1 — A Active Miller clamp NMOS output HNOUT2 (LNOUT2) = 15V, LIN = 5V, low level short circuit pulsed current PW < 5µs — –1 — A ROH Output high level on resistance IO = –1A, ROH = (VOH–VO) /IO — 15 — Ω ROL1 Output low level on resistance IO = 1A, ROL1 = VO/IO — 15 — Ω IO = 1A, ROL2 = VO/IO — 15 — Ω IOL2 ROL2 Active Miller clamp NMOS output low level on resistance tdLH(HO) High side turn-on propagation delay HPOUT short to HNOUT1 and HNOUT2, CL = 1nF 1 1.27 1.8 µs tdHL(HO) High side turn-off propagation delay HPOUT short to HNOUT1 and HNOUT2, CL = 1nF 0.9 1.21 1.8 µs tdLH(LO) Low side turn-on propagation delay LPOUT short to LNOUT1 and LNOUT2, CL = 1nF 1 1.39 1.9 µs tdHL(LO) Low side turn-off propagation delay LPOUT short to LNOUT1 and LNOUT2, CL = 1nF 0.9 1.19 1.7 µs tr Output turn-on rise time CL = 1nF — 40 — ns tf Output turn-off fall time CL = 1nF — 40 — ns ∆tdLH Delay matching, high side turn-on tdLH (HO)-tdHL (LO) — 80 — ns ∆tdHL Delay matching, high side turn-off tdLH (LO)-tdHL (HO) — 180 — ns and low side turn-off and low side turn-on Note: Typ is not specified. Aug. 2009 4 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER FUNCTION TABLE (Q: Keep previous status) HIN LIN FO_RST CIN H→L H→L L→H L→H X X X X X X L H L H H L X X L H L L L L X X X X L L L L L L H H X X L L FO (Input) VBS/UV VCC/POR – – – – – – LOUT FO (Output) L L H Q L Q L L L L L H L Q L Q L L L H H H H H L H L H H H H H H H H H H L H H H H H H X X X X L L L – – – HOUT Behavioral status Interlock active CIN tripping when LIN=H CIN not tripping when LIN=L Output shuts down when FO=L VCC power reset VBS power reset VBS power reset is tripping when LIN=H Note1 : “L” status of VBS/UV indicates a high side UV condition; “L” status of VCC/POR indicates a VCC power reset condition. Note2 : In the case of both input signals (HIN and LIN) are “H”, output signals (HOUT and LOUT) keep previous status. Note3 : X (HIN) : L→H or H→L. Other : H or L. Note4 : Output signal (HOUT) is triggered by the edge of input signal. HIN HOUT FUNCTIONAL DESCRIPTION 1. INPUT/OUTPUT TIMING DIAGRAM LIN 50% 50% HIN tr tf 90% 90% tdLH(HO) tdHL(HO) 10% HOUT 10% ∆tdLH ∆tdHL tr LOUT 90% 90% tdLH(LO) tdHL(LO) tf 10% 10% Aug. 2009 5 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 2. INPUT INTERLOCK TIMING DIAGRAM When the input signals (HIN/LIN) are high level at the same time, the outputs (HOUT/LOUT) keep their previous status. But if signals (HIN/LIN) are going to high level simultaneously, HIN signals will get active and cause HOUT to enter “H” status. HIN LIN HOUT LOUT Note1: The minimum input pulse width at HIN/LIN should be to more than 500ns (because of HIN/LIN input noise filter circuit). Note2: If a high-high status of input signals (HIN/LIN) is ended with only one input signal entering low level and another still being in high level, the output will enter high-low status after the delay match time (not shown in the figure above). Note3: Delay times between input and output signals are not shown in the figure above. 3. SHORT CIRCUIT PROTECTION TIMING DIAGRAM When an over-current is detected by exceeding the threshold at the CIN and LIN is at high level at the same time, the short circuit protection will get active and shutdown the outputs while FO will issue a low level (indicating a fault signal). The fault output latch is reset by a high level signal at FO_RST pin and then FO will return to high level while the output of the driver will respond to the following active input signal. HIN LIN CIN FO_RST HOUT LOUT FO Note1 : Delay times between input and output signals are not shown in the figure above. Note2 : The minimum FO_RST pulse width should be more than 500ns (because of FO_RST input filter circuit). Aug. 2009 6 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 4. FO INPUT TIMING DIAGRAM When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/ DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again, the output will respond to the following active input signal. HIN LIN FO HOUT LOUT Note1: Delay times between input and output signals are not shown in the figure above. Note2: The minimum FO pulse width should be more than 500ns (because of FO input filter circuit). 5. LOW SIDE VCC SUPPLY POWER RESET SEQUENCE When the VCC supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (HOUT/ LOUT) become “L”. As soon as the VCC supply voltage goes higher than the power reset trip voltage, the outputs will respond to the following active input signals. VCC VPOR voltage HIN LIN HOUT LOUT Note1: Delay times between input and output signals are not shown in the figure above. Aug. 2009 7 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 6. HIGH SIDE VBS SUPPLY UNDER VOLTAGE LOCKOUT SEQUENCE When VBS supply voltage drops below the VBS supply UV trip voltage and the duration in this status exceeds the VBS supply UV filter time, the output of the high side is locked. As soon as the VBS supply voltage rises above the VBS supply UV reset voltage, the output will respond to the following active HIN signal. VBSuvr VBSuvr VBS VBS supply UV hysteresis voltage VBSuvt VBS supply UV filter time HIN LIN HOUT LOUT Note1: Delay times between input and output signals are not shown in the figure above. 7. POWER START-UP SEQUENCE At power supply start-up the following sequence is recommended when bootstrap supply topology is used. (1). Apply VCC. (2). Make sure that FO is at high level. (3). Set LIN to high level and HIN to low level so that bootstrap capacitor could be charged. (4). Set LIN to low level. VCC FO Note: If two power supply are used for supplying Note: VCC and VBS individually, it is recommended Note: to set VCC first and then set VBS. HIN LIN LOUT Aug. 2009 8 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 8. ACTIVE MILLER EFFECT CLAMP NMOS OUTPUT TIMING DIAGRAM The structure of the output driver stage is shown in following figure. This circuit structure employs a solution for the problem of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on due to the parasitic Miller capacitor in power switches. VBS/VCC Cres P1 VOUT VPG/VN1G VIN=0 (from HIN/LIN) high dv/dt N1 N2 Cies VS/VNO VN2G Active Miller Effect Clamp NMOS When HIN/LIN is at low level and the voltage of the VOUT (IGBT gate voltage) is below active Miller effect clamp NMOS input threshold voltage, the active Miller effect clamp NMOS is being turned on and opens a low resistive path for the Miller current through Cres. VIN VPG P1 ON P1 OFF P1 ON VN1G N1 OFF N1 ON N1 OFF Active Miller effect clamp NMOS input threshold VOUT VN2G N2 ON N2 OFF N2 OFF TW Active Miller effect clamp NMOS keeps turn-on if TW does not exceed active Miller clamp NMOS filter time Aug. 2009 9 MITSUBISHI SEMICONDUCTORS <HVIC> M81019FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER INTERNAL DIODE CLAMP CIRCUITS FOR INPUT AND OUTPUT PINS VCC VCC VCC HIN LIN FO_RST CIN FO VNO GND GND GND VCC VB VB LPOUT LNOUT1 LNOUT2 HPOUT HNOUT1 HNOUT2 GND VS 5K PACKAGE OUTLINE 24P2Q-A EIAJ Package Code SSOP24-P-300-0.80 JEDEC Code – Weight(g) 0.2 e b2 13 E F Recommended Mount Pad Symbol 1 12 A D G A2 e y A1 b L L1 HE e1 I2 24 Lead Material Cu Alloy c z Z1 Detail F Detail G A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 Dimension in Millimeters Min Nom Max 2.1 – – 0.2 0.1 0 – 1.8 – 0.45 0.35 0.3 0.25 0.2 0.18 10.2 10.1 10.0 5.4 5.3 5.2 – 0.8 – 8.1 7.8 7.5 0.8 0.6 0.4 – 1.25 – – 0.65 – – – 0.8 0.1 – – 0° – 8° – 0.5 – – 7.62 – – 1.27 – Aug. 2009 10