PRELIMINARY < HVIC > M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER DESCRIPTION M81738FP is 1200V high voltage Power MOSFET and IGBT module driver for half bridge applications. PIN CONFIGURATION (TOP VIEW) FEATURES ●Floating supply voltage up to 1200V ● Low quiescent power supply current ● Separate sink and source current output up to ±1A (typ) ● Active Miller effect clamp NMOS with sink current up to 1A (typ) ● Input noise filters (HIN,LIN,FO_RST,FO) ● Over-current detection and output shutdown ● High side under voltage lockout ● FO pin which can input and output Fault signals to communicate with controllers and synchronize the shut down with other phases ● Active clamp (power supply surge clamp) ● 24pin SSOP-Lead package NC NC NC HIN VB LIN FO_RST HPOUT HNOUT1 CIN HNOUT2 GND FO VS NC VCC NC LPOUT NC LNOUT1 NC LNOUT2 NC VNO Outline:24P2Q APPLICATIONS Power MOSFET and IGBT gate driver for Inverter or general purpose. BLOCK DIAGRAM VB Active Clamp Active Clamp HV Levelshift UV+POR HPOUT GND HNOUT Logic Filter VregVCC Levelshift HNOU VS HIN Interlock Delay Noise Filter VCC Oneshot Pulse VC C Vreg Vreg Vreg1 LPOU LIN Delay POR LNOU VregVCC Levelshift LNOU CIN Filter Vreg1 Protection Logic V NO VregVCC Levelshift FO_RST Filter Filter Publication Date : Jan 2012 1 FO PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limitation beyond which destruction of device may occur. All voltage parameters are absolute voltage reference to GND unless otherwise specified. Symbol VB VS VBS VHO VCC VNO VLO VIN VFO VCIN dVS/dt Pd K Rth(j-a) Tj Topr Tstg Parameter High side floating supply absolute voltage High side floating supply offset voltage High side floating supply voltage High side output voltage Low side fixed supply voltage Power ground Low side output voltage Logic input voltage FO input/output voltage CIN input voltage Allowable offset voltage slew rate Package power dissipation Linear derating factor Junction-ambient air thermal resistance Junction temperature Operation temperature Storage temperature Test conditions VBS=VB-VS HIN, LIN, FO_RST VS -GND Ta= 25°C ,On our standard PCB Ta≧25°C ,On our standard PCB On our standard PCB Raitings -0.5～1224 VB -24～VB +0.5 -0.5～24 VS -0.5～VB +0.5 -0.5～24 VCC -24～VCC +0.5 VNO -0.5～VCC +0.5 -0.5～VCC +0.5 -0.5～VCC +0.5 -0.5～VCC +0.5 ±50 ～1.11 ～11.1 ～90 -40～125 -40～100 -40～150 Unit V V V V V V V V V V V/ns W mW/°C °C/W ℃ ℃ ℃ RECOMMENDED OPERATING CONDITIONS For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND unless otherwise specified. Symbol VB VS VBS VHO VCC VNO VLO VIN VFO VCIN Parameter Test conditions High side floating supply absolute voltage High side floating supply offset voltage High side floating supply voltage High side output voltage Low side fixed supply voltage Power ground Low side output voltage Logic input voltage FO input/output voltage CIN input voltage VBS> 13.5V VBS=VB-VS HIN, LIN, FO_RST Min. Limits Typ. Max. VS+13.5 VS+15 VS+20 -5 13.5 VS 13.5 -0.5 VNO 0 0 0 15 15 - 900 20 VS+20 20 5 VCC VCC VCC 5 THERMAL DERATING FACTOR CHARACTERISTIC Package Power Dissipation Pd (W) 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 100 Ambience Temperature (℃) Publication Date : Jan 2012 2 125 150 Unit V V V V V V V V V V PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER TYPICAL CONNECTION Rboot VB VCC 15V MCU/DSP Controller 5V~15V HIN LIN FO_RST Other Phases RGON HPOUT HNOUT1 HOUT RGOFF HNOUT２ Cboot M81019FP M81738FP RFO DC+ Dboot Vout VS FO RGON CFO LPOUT GND CIN LNOUT1 LOUT RGOFF LNOUT２ VNO Rshunt RCIN CCIN DC- Note: If HVIC is working in high noise environment, it is recommended to connect a 1nF ceramic capacitor (CFO) to FO pin. Publication Date : Jan 2012 3 DC BUS Voltage PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER ELECTRICAL CHARACTERISTICS (Ta=25 °C,VCC=VBS(=VB-VS)=15V, unless otherwise specified) Symbol Parameter Test conditions Min. Limits Typ. Max. - - 10 A Unit IFS High side leakage current IBS VBS quiescent supply current HIN = LIN = 0V - 0.5 0.8 mA ICC VCC quiescent supply current HIN = LIN = 0V - 1.0 1.5 mA VOH High level output voltage IO = 0A, HPOUT, LPOUT 14.5 - - V VOL Low level output voltage IO = 0A, HNOUT1, LNOUT1 - - 0.5 V VIH High level input threshold voltage HIN, LIN, FO_RST 2.2 3.0 4.0 V VB = VS = 1200V VIL Low level input threshold voltage HIN, LIN, FO_RST 0.6 1.5 2.1 V IIH High level input bias current VIN = 5V 0.6 1.0 1.4 mA IIL Low level input bias current VIN = 0V 0.00 0.00 0.01 mA tFilter Input signals filter time HIN on-pulse 80 ns 80 200 200 500 HIN off-pulse 500 ns LIN on-pulse 80 200 500 ns LIN off-pulse 80 200 500 ns FO_RST on-pulse 80 200 500 ns FO off-pulse 80 200 500 ns V VHNO2 High side active Miller clamp NMOS input threshold voltage VIN = 0V 2.0 3.4 5.0 VLNO2 Low side active Miller clamp NMOS input threshold voltage VIN = 0V 6.0 7.6 9.0 V tVNO2 Active Miller clamp NMOS filter time VIN = 0V - 400 - ns VOLFO Low level FO output voltage IFO = 1mA - - 0.95 V VIHFO High level FO input threshold voltage 2.2 3.0 4.0 V VILFO Low level FO input threshold voltage 0.6 1.5 2.1 V VBSuvr VBS supply UV reset voltage 10.0 10.8 11.6 V VBSuvt VBS supply UV trip voltage 10.5 11.3 12.1 V VBSuvh VBS supply UV hysteresis voltage 0.2 0.5 0.8 V tVBSuv VBS supply UV filter time 4 8 16 s VCIN CIN trip voltage 0.40 0.5 0.60 V VPOR POR trip voltage 4.0 5.5 7.5 V IOH Output high level short circuit pulsed current HPOUT(LPOUT) = 0V, VIN = 5V, PW ≦ 10s - 1 - A IOL1 Output low level short circuit pulsed current HNOUT1(LNOUT1) = 15V, VIN = 0V, PW ≦ 10s - -1 - A HNOUT2(LNOUT2) = 15V, VIN = 0V, PW ≦ 10s - -1 - A IOL2 Active Miller clamp NMOS output low level short circuit pulsed current VBSuvh = VBSuvr-VBSuvt ROH Output high level on resistance IO = 1A, ROH = (VOH-VO)/IO - 15 - ROL1 Output low level on resistance IO = -1A, ROL1 = VO/IO - 15 - ROL2 Active Miller clamp NMOS output low level on resistance IO = -1A, ROL2 = VO/IO - 15 - tdLH(HO) High side turn-on propagation delay HPOUT short to HNOUT1 and HNOUT2, CL = 1nF 1.00 1.27 1.80 s tdHL(HO) High side turn-off propagation delay HPOUT short to HNOUT1 and HNOUT2, CL = 1nF 0.90 1.21 1.80 s tdLH(LO) Low side turn-on propagation delay LPOUT short to LNOUT1 and LNOUT2, CL = 1nF 1.00 1.39 1.90 s tdHL(LO) Low side turn-off propagation delay LPOUT short to LNOUT1 and LNOUT2, CL = 1nF 0.90 1.19 1.70 s tr Output turn-on rise time CL = 1nF 10 40 80 ns tf Output turn-off fall time CL = 1nF 10 40 80 ns tdLH Delay matching, high side turn-on and low side turn-off tdLH(HO)-tdHL(LO) -100 80 300 ns tdHL Delay matching, high side turn-off and low side turn-on tdLH(LO)-tdHL(HO) -20 180 400 ns Vclamp Active clamp voltage Vcc – GND, VB - VS 24 - - V Note: Typ. is not specified. Publication Date : Jan 2012 4 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER FUNCTION TABLE (Q: Keep previous status) HIN LIN FO_RST CIN L L H H X X X X X X L H L H H L X X L H L L L L X X X X L L L L L L H H X X L L FO VBS/ (Input) UV・POR H H H H X X L X X L L VCC/ POR H H H H H H H L H H HOUT LOUT L L H Q L Q L L L L L H L Q L Q L L L H FO (Output) H H H H L H H H H Behavioral status Interlock active CIN tripping when LIN = H CIN not tripping when LIN = L Output shuts down when FO = L VCC power reset VBS power reset VBS power reset is tripping when LIN = H Note1 :“L” status of VBS/UV indicates a high side UV condition; “L” status of VCC/POR indicates a VCC power reset condition. Note2 : In the case of both input signals (HIN and LIN) are “H”, output signals (HOUT and LOUT) keep previous status. Note3 : X (HIN) : L→H or H → L. Other : H or L. Note4 : Output signal (HOUT) is triggered by the edge of input signal. FUNCTIONAL DESCRIPTION 1. INPUT/OUTPUT TIMING DIAGRAM LIN 50% 50% HIN tf tr 90% 90% tdLH(HO) td HL(HO) 10% HO 10% ⊿tdLH ⊿tdHL tr LO 90% 90% tdLH(LO) tdHL(LO) tf 10% 10% Publication Date : Jan 2012 5 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 2. INPUT INTERLOCK TIMING DIAGRAM When the input signals (HIN/LIN) are high level at the same time, the outputs (HOUT/LOUT) keep their previous status. But if signals (HIN/LIN) are going to high level simultaneously, HIN signals will get active and cause HOUT to enter “H” status. HIN LIN HOUT LOUT Note1 :The minimum input pulse width at HIN/LIN should be to more than 500ns (because of HIN/LIN input noise filter circuit). Note2 :If a high-high status of input signals (HIN/LIN) is ended with only one input signal entering low level and another still being in high level, the output will enter high-low status after the delay match time (not shown in the figure above). Note3 :Delay times between input and output signals are not shown in the figure above. 3. SHORT CIRCUIT PROTECTION TIMING DIAGRAM When an over-current is detected by exceeding the threshold at the CIN and LIN is at high level at the same time, the short circuit protection will get active and shutdown the outputs while FO will issue a low level (indicating a fault signal). The fault output latch is reset by a high level signal at FO_RST pin and then FO will return to high level while the output of the driver will respond to the following active input signal. HIN LIN CIN FO_RST HOUT LOUT FO Note1 : Delay times between input and output signals are not shown in the figure above. Note2 : The minimum FO_RST pulse width should be more than 500ns (because of FO_RST input filter circuit). Publication Date : Jan 2012 6 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 4. FO INPUT TIMING DIAGRAM When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again, the output will respond to the following active input signal. HIN LIN FO HOUT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. Note2 :The minimum FO pulse width should be more than ns (because of FO input filter circuit). 5. LOW SIDE VCC SUPPLY POWER RESET SEQUENCE When the VCC supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (LOUT) become “L”. As soon as the VCC supply voltage goes higher than the power reset trip voltage, the outputs will respond to the following active input signals. VCC VPOR voltage HIN LIN HOUT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. Publication Date : Jan 2012 7 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 6. HIGH SIDE VBS SUPPLY UNDER VOLTAGE LOCKOUT SEQUENCE When VBS supply voltage drops below the VBS supply UV trip voltage and the duration in this status exceeds the VBS supply UV filter time, the output of the high side is locked. As soon as the VBS supply voltage rises above the VBS supply UV reset voltage, the output will respond to the following active HIN signal. VBSuvr VBS VBSuvr VBS supply UV hysteresis voltage VBSuvt VBS supply UV filter time HIN LIN HOUT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. 7. POWER START-UP SEQUENCE At power supply start-up the following sequence is recommended when bootstrap supply topology is used. (1). Apply VCC. (2). Make sure that FO is at high level. (3). Set LIN to high level and HIN to low level so that bootstrap capacitor could be charged. (4). Set LIN to low level. VCC FO HIN LIN LOUT Note : If two power supply are used for supplying VCC and VBS individually, it is recommended to set VCC first and then set VBS. Publication Date : Jan 2012 8 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER 8. ACTIVE MILLER EFFECT CLAMP NMOS OUTPUT TIMING DIAGRAM The structure of the output driver stage is shown in following figure. This circuit structure employs a solution for the problem of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on due to the parasitic Miller capacitor in power switches. V BS/V CC C res V OUT high dv/dt V IN =0 (from HIN/LIN) C ies V S /VNO Active Miller clamp NMOS When HIN/LIN is at low level and the voltage of the VOUT (IGBT gate voltage) is below active Miller effect clamp NMOS input threshold voltage, the active Miller effect clamp NMOS is being turned on and opens a low resistive path for the Miller current through Cres. VIN VPG VN1G P1 OFF P1 ON P1 ON N1 ON N1 OFF N1 OFF Active Miller clamp NMOS input threshold voltage VOUT VN2G N2 ON N2 OFF N2 OFF Tw Active Miller effect clamp NMOS keeps turn-on if TW does not exceed active Miller clamp NMOS filter time Publication Date : Jan 2012 9 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER INTERNAL DIODE CLAMP CIRCUITS FOR INPUT AND OUTPUT PINS V CC V CC V CC HIN LIN FO_RST CIN FO GND GND GND V CC V CC V NO LPOUT LNOUT1 LNOUT2 GND V NO VB VB HPOUT HNOUT1 HNOUT2 VS PACKAGE OUTLINE Publication Date : Jan 2012 10 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER Main Revision for this Edition Revision No. Date Pages Points Publication Date : Jan 2012 11 PRELIMINARY <HVIC> M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER Keep safety first in your circuit designs! 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