L6392 High-voltage high and low side driver Preliminary Data Features ■ High voltage rail up to 600 V ■ dV/dt immunity ± 50 V/nsec in full temperature range ■ Driver current capability: – 270 mA source – 430 mA sink ■ Switching times 75/35 nsec rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS inputs with hysteresis ■ Integrated bootstrap diode ■ Operational amplifier for advanced current sensing ■ Adjustable dead-time ■ Interlocking function ■ Compact and simplified layout ■ Bill of material reduction ■ Flexible, easy and fast design DIP-14 SO-14 Description The L6392 is a high-voltage device, manufactured with the BCD “OFF-LINE" technology. It has a monolitich half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy of interfacing microcont roller/DSP The IC embeds an op amp suitable for advanced current sensing in applications such as field oriented motor control. Application Table 1. March 2008 Device summary Order codes Package Packaging L6392 DIP-14 Tube L6392D SO-14 Tube L6392D013TR SO-14 Tape and reel Rev 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/19 www.st.com 19 Contents L6392 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 L6392 1 Block diagram Block diagram Figure 1. VCC Block diagram BOOTSTRAP DRIVER 4 UV DETECTION FLOATING STRUCTURE from LVG 14 BOOT 13 HVG 12 OUT UV DETECTION HVG DRIVER HIN 3 LEVEL SHIFTER S R LOGIC 5V SHOOT THROUGH PREVENTION LIN 1 VCC SD GND DT LVG DRIVER LVG 10 2 7 5 DEAD TIME VCC OPOUT 6 OPAMP + 8 OP+ OP- 9 3/19 Pin connection 2 L6392 Pin connection Figure 2. Table 2. Pins connection (top view) LIN 1 14 BOOT SD 2 13 HVG HIN 3 12 OUT VCC 4 11 NC DT 5 10 LVG OPOUT 6 9 OP- GND 7 8 OP+ Pin description Pin N# Pin name Type 1 LIN I Low side driver logic input (active low) I Shut down logic input (active low) 2 SD (1) Function 3 HIN I High side driver logic input (active high) 4 VCC P Lower section supply voltage 5 DT I Dead time setting 6 OPOUT O Opamp output 7 GND P Ground 8 OP+ I Opamp non inverting input 9 OP- I Opamp inverting input O Low side driver output 10 LVG (1) 11 NC 12 OUT (1) 13 HVG 14 BOOT Not connected P High side (floating) common voltage O High side driver output P Bootstrapped supply voltage 1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows to omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/19 L6392 3 Truth table Truth table Table 3. Truth table Inputs Note: Outputs SD LIN HIN LVG HVG L X X L L H L L H L H L H L L H H L L L H H H L H X: don’t care 5/19 Electrical data L6392 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum rating Symbol Parameter Value Unit Vout Output voltage Vboot -21 to Vboot +0.3 V VCC Supply voltage - 0.3 to + 21 V Vop+ Opamp non-inverting input -0.3 to VCC +0.3 V Vop- Opamp inverting input -0.3 to VCC +0.3 V Vboot Floating supply voltage VCC - 0.3 to 620 V Vhvg High side gate output voltage Vout - 0.3 to Vboot + 0.3 V VIvg Low side gate output voltage -0.3 to VCC + 0.3 V -0.3 to 15 V 50 V/ns Logic input voltage Vi dVout/dt Allowed output slew rate Ptot Total power dissipation (TA= 85 °C) TBD mW TJ Junction temperature 150 °C Tstg Storage temperature -50 to 150 °C Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to TBD (Human Body Model) 4.2 Thermal data Table 5. Thermal data Symbol Rth(JA) 4.3 Parameter Thermal resistance junction to ambient SO-14 DIP-14 Unit 165 100 °C/W Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin Vout 12 VBS (2) 14 TJ 4 Test condition Min Output voltage (1) Floating supply voltage Switching frequency fsw VCC Parameter (1) TBD HVG, LVG load CL = 1nF Max Unit 580 V TBD V 800 kHz Supply voltage TBD TBD V Junction temperature -40 125 °C 1. If the condition TBDV< Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V to 580 V. 2. VBS = Vboot -Vout 6/19 L6392 Electrical characteristics 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15V; TJ =+25 °C) Symbol ton toff tsd Pin tf Min Typ 5 Max Unit 125 ns 125 ns 125 ns Delay matching, HS and LS turn-on/off MDT tr Test condition High/low side driver turnVout = 0 V 1 vs 10 on propagation delay = Vcc V 3 vs 13 High/low side driver turn- boot CL = 1nF off propagation delay Vi = 0 to 3.3 V 2 vs Shut down to high/low See Figure 3 on page 7 10, 13 side propagation delay MT dt Parameter 40 ns µs µs µs µs Dead time setting range Rdt=0; CL=1 nF; CDT =100 nF Rdt=37 kΩ;CL=1 nF;CDT=100 nF Rdt=136 kΩ;CL=1 nF;CDT=100 nF Rdt=260 kΩ;CL=1 nF;CDT=100 nF Matching dead time Rdt=0 Ω; CL=1 nF; CDT =100 nF Rdt=37 kΩ;CL=1 nF;CDT=100 nF Rdt=136 kΩ;CL=1 nF;CDT=100 nF Rdt=26 0kΩ;CL=1 nF;CDT=100 nF Rise time CL = 1 nF 75 ns Fall time CL = 1 nF 35 ns 10, 13 Figure 3. 0.15 0.5 1.5 2.8 60 TBD TBD TBD ns ns ns ns Timing characteristics LIN 50% 50% tr tf 90% LVG 10% 10% ton HIN 90% toff 50% 50% tr tf 90% HVG 90% 10% 10% ton SD toff 50% 50% tr tf 90% 90% 10% 10% LVG/HVG ton toff 7/19 Electrical characteristics L6392 5.2 DC operation Table 8. DC operation electrical characteristics (VCC = 15 V;TJ = +25 °C) Symbol Pin Parameter Test condition Min Typ Max Unit 700 1400 mV Low supply voltage section Vcc_hys Vcc UV hysteresis Vcc_thON Vcc UV turn ON threshold 11.8 V Vcc_thOFF Vcc UV turn OFF threshold 10.4 V Iqccu 4 Iqcc Undervoltage quiescent supply current VCC = 10 V SD = 5V; LIN = 5V; HIN = GND; RDT = 0 Ω; OP + = GND; OP - = 5 V 110 150 µA Quiescent current VCC = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; OP + = GND; OP - = 5 V 680 1060 µA Bootstrapped supply voltage section VBS_hys VBS UV hysteresis 700 1400 mV VBS_thON VBS UV turn ON threshold 11.6 V VBS_thOFF VBS UV turn OFF threshold 10.2 V IQBSU IQBS 8/19 14 Undervoltage VBS quiescent current VBS = 10 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; OP + = GND; OP - = 5 V 70 110 µA VBS quiescent current VBS = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; OP + = GND; OP - = 5 V 150 210 µA L6392 Table 8. Symbol Electrical characteristics DC operation electrical characteristics (VCC = 15 V;TJ = +25 °C) Pin ILK Rdson Parameter Test condition Min Typ Max Unit 10 µA High voltage leakage current Vhvg = Vout = Vboot = 600 V Bootstrap driver on resistance (1) LVG ON 120 Ω High/low side source short circuit current Vi= Vih (tp < 10 ms) 270 mA High/low side sink short circuit current Vi= Vil (tp < 10 ms) 430 mA Driving buffers section Iso 10, 13 Isi Logic inputs Low level logic threshold voltage Vil 0.83 V 1, 2, 3 Vih High level logic threshold voltage IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINh LIN logic “1” input bias current LIN = 0 V ILINl LIN logic “0” input bias current LIN = 15 V ISDh SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V V 2.21 175 260 µA 1 µA 40 µA 1 µA 100 µA 1 µA 3 6 1 30 2 ISDl 1. RDSon is tested in the following way: RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 9/19 Electrical characteristics Table 9. Symbol OPAMP characteristics (VCC = 15 V, TJ = +25 °C) Pin Vio Iib L6392 Parameter Input offset voltage 8, 9 Test condition Input bias current (1) 15 Input common mode voltage range VOL Output voltage swing - low level Isink = 3.5 mA, RL = 2 kΩ VOH Output voltage swing - high level Isource = 3.5 mA, RL = 2 kΩ GBWP 3 mV 200 nA VCC TBD 0 180 360 mV V Source, Vid = TBD; Vo = TBD 16 30 mA Sink Vid = TBD; Vo = TBD 50 80 mA Slew rate Vi = TBD; RL = 2 kΩ; CL = TBD; unity gain 2.5 3.8 V/µs Gain bandwith product Vo = TBD; RL = 2 kΩ TBD MHz 95 dB 85 dB 100 dB Output short circuit current Large signal voltage gain SRV Power supply rejection ratio Common mode rejection ratio 1. The direction of input current is out of the IC. 10/19 Unit 14.3 Avd CMRR Max 13.5 6 SR Typ VO = TBD; 0 < Vicm < VCC -TBD Vicm Io Min 85 vs Vcc 80 L6392 Waveforms definitions 6 Waveforms definitions Figure 4. Dead time - timing waveforms RLO CKIN G INTE RLO HIN INTE CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CKIN G LIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DT DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DT DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DT DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected togheter and driven by just one control signal 11/19 Typical application diagram L6392 7 Typical application diagram Figure 5. Application diagram BOOTSTRAP DRIVER VCC 4 UV DETECTION FLOATING STRUCTURE from LVG 14 BOOT UV DETECTION H.V. HVG DRIVER HIN 3 LEVEL SHIFTER S 13 HVG 12 OUT Cboot R LOGIC 5V SHOOT THROUGH PREVENTION LIN 1 TO LOAD VCC SD GND DT 2 LVG DRIVER LVG 10 SD LATCH 7 5 DEAD TIME OPAMP OPOUT 6 + 8 9 12/19 OP+ OP- - L6392 8 Bootstrap driver Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6 a). In the L6392 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 6 b. An internal charge pump (Figure 6 b) provides the DMOS driving voltage. 8.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = ------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT >>> CEXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has to supply 1 µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1 V. The internal bootstrap driver gives agreat advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------ R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 13/19 Bootstrap driver L6392 For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 µs. In fact: 30nC V drop = --------------- ⋅ 120Ω ∼ 0.7V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver DBOOT VS BOOT BOOT VS H.V. HVG H.V. HVG CBOOT VOUT VOUT TO LOAD TO LOAD LVG LVG a 14/19 CBOOT b D99IN1067 L6392 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 15/19 Package mechanical data Figure 7. L6392 DIP-14 mechanical data and package dimensions mm DIM. MIN. a1 0.51 B 1.39 TYP. MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 16/19 inch 3.3 1.27 0.130 2.54 0.050 0.100 OUTLINE AND MECHANICAL DATA L6392 Package mechanical data Figure 8. SO-14 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.30 0.004 0.012 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.01 8.55 8.75 0.337 0.344 3.80 4.0 0.150 0.157 D (1) E e 1.27 0.050 H 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0° (min.), 8° (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO-14 0016019 D 17/19 Revision history 10 L6392 Revision history Table 10. 18/19 Document revision history Date Revision Changes 29-Feb-2008 1 Initial release 18-Mar-2008 2 Cover page updated L6392 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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