SMP100LC Trisil™ for telecom equipment protection Features ■ Bidirectional crowbar protection ■ Voltage range from 8 V to 400 V ■ Low capacitance from 20 pF to 45 pF @ 50 V ■ Low leakage current : IR = 2 µA max ■ Holding current: IH = 150 mA min ■ Repetitive peak pulse current: IPP = 100 A (10/1000 µs) SMB (JEDEC DO-214AA) Main applications Any sensitive equipment requiring protection against lightning strikes and AC power faults. These devices are dedicated to central office protection as they comply with the most stressfull standards. Their Low Capacitances make them suitable for xDSL. Description The SMP100LC is a series of low capacitance transient surge arrestors designed for the protection of high data rate communication equipment. Its low capacitance avoids any distortion of the signal and is compatible with digital transmission line cards (xDSL, ISDN...). SMP100LC series tested and confirmed compatible with Cooper Bussmann Telecom Circuit Protector TCP 1.25A. The SMP100LC-xxx with the fuse TCP1.25A or TCP2A is compliant with Telcordia GR1089 (lightning and AC power fault tests), ITU-T K20/K21 (lightning and AC power fault tests), TIA/EIA-IS-968 (formely FCC Part 68 lightning tests), UL60950 (AC power fault tests). Moreover, the use of the TCP1.25A allows the SMP100LC-xxx to be safe for the 2nd level (B criteria) AC power fault tests. March 2007 Order Code Order code Marking SMP100LC-xxx See Section 5 on page 11 Benefits Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. They are used to help equipment to meet main standards such as UL60950, IEC950 / CSA C22.2 and UL1459. They have UL94 V0 approved resin. SMB package is JEDEC registered (DO-214AA). Trisils comply with the following standards GR-1089 Core, ITU-T-K20/K21, VDE0433, VDE0878, IEC61000-4-5 and FCC part 68. Rev 12 1/12 www.st.com 12 Characteristics 1 SMP100LC Characteristics Table 1. Compliant with the following standards STANDARD Peak Surge Voltage (V) GR-1089 Core First level Required Waveform peak current Voltage (A) Current waveform Minimum serial resistor to meet standard (Ω) 2500 1000 2/10 µs 10/1000 µs 500 100 2/10 µs 10/1000 µs 0 0 GR-1089 Core Second level 5000 2/10 µs 500 2/10 µs 0 GR-1089 Core Intra-building 1500 2/10 µs 100 2/10 µs 0 ITU-T-K20/K21 6000 1500 10/700 µs 150 37.5 5/310 µs 0 0 ITU-T-K20 (IEC61000-4-2) 8000 15000 1/60 ns ESD contact discharge ESD air discharge 0 0 4000 2000 4000 2000 4000 4000 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B VDE0433 VDE0878 IEC61000-4-5 Table 2. 1500 800 10/160 µs 10/560 µs 200 100 10/160 µs 10/560 µs 0 0 1000 9/720 µs 25 5/320 µs 0 1.2/50 µs Repetitive peak pulse current (see Figure 1) IFS Fail-safe mode : maximum current (1) I2t Tstg Tj TL 1/20 µs Parameter IPP ITSM 2/12 5/310 µs 8/20 µs 0 0 0 0 0 0 5/310 µs Absolute ratings (Tamb = 25° C) Symbol 1. 10/700 µs 1.2/50 µs 100 50 100 50 100 100 10/700 µs Non repetitive surge peak on-state current (sinusoidal) I2t value for fusing Value 10/1000 µs 8/20 µs 10/560 µs 5/310 µs 10/160 µs 1/20 µs 2/10 µs 8/20 µs t = 0.2 s t=1s t=2s t = 15 mn t = 16.6 ms t = 20 ms Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10 s. in fail safe mode, the device acts as a short circuit 100 400 140 150 200 400 500 5 24 15 12 4 20 21 Unit A kA A A2s -55 to 150 150 °C 260 °C SMP100LC Characteristics Table 3. Thermal Resistances Symbol Parameter Value Unit Rth(j-a) Junction to ambient (with recommended footprint) 100 ° C/W Rth(j-l) Junction to leads 20 ° C/W Table 4. Electrical Characteristics (Tamb = 25° C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VBO Breakover voltage IRM Leakage current IPP Peak pulse current IBO Breakover current IH Holding current VR Continuous reverse voltage IR Leakage current at VR C Capacitance IRM @ VRM Type max. µA IR @ VR (1) Dynamic Static VBO (2) VBO @ IBO (3) max. V µA V IH (4) C(5) C(6) max. max. max. min. typ. typ. V V mA mA pF pF SMP100LC-8 6 8 25 15 NA 75 SMP100LC-25 22 25 40 35 50 (typ.) NA 65 SMP100LC-35 32 35 55 55 NA 55 SMP100LC-65 55 65 85 85 45 90 SMP100LC-90 81 90 120 125 40 80 SMP100LC-120 108 120 155 150 35 75 140 180 175 30 65 30 65 SMP100LC-140 SMP100LC-160 2 126 144 5 160 205 200 800 150 SMP100LC-200 180 200 255 250 30 60 SMP100LC-230 207 230 295 285 30 60 SMP100LC-270 243 270 345 335 30 60 SMP100LC-320 290 320 400 390 25 50 SMP100LC-360 325 360 460 450 25 50 SMP100LC-400 360 400 540 530 20 45 1. IR measured at VR guarantee VBR min ≥ VR 2. See Figure 15: Test circuit 1 for Dynamic IBO and VBO parameters 3. See Figure 16: Test circuit 2 for IBO and VBO parameters 4. See Figure 17: Test circuit 3 for dynamic IH parameter 5. VR = 50 V bias, VRMS =1 V, F = 1 MHz 6. VR = 2V bias, VRMS =1 V, F = 1 MHz 3/12 Characteristics Figure 1. SMP100LC Pulse waveform %IPP Figure 2. ITSM(A) Repetitive peak pulse current 70 tr = rise time (µs) tp = pulse duration time (µs) 100 Non repetitive surge peak on-state current versus overload duration F=50Hz Tj initial = 25°C 60 50 40 50 30 20 10 0 tr Figure 3. t(s) t tp 0 1E-2 On-state voltage versus on-state current (typical values) 1E-1 Figure 4. IT(A) 1E+0 1E+1 1E+2 1E+3 Relative variation of holding current versus junction temperature IH[Tj] / IH[Tj=25°C] 100 2.0 Tj initial = 25°C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 VT(V) Tj(°C) 0.0 10 -25 0 1 Figure 5. 2 3 4 5 6 7 0 25 50 75 100 125 8 Relative variation of breakover voltage versus junction temperature Figure 6. VBO[Tj] / VBO[Tj=25°C] Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25°C] 1.08 2000 1000 1.06 1.04 100 1.02 1.00 10 0.98 Tj(°C) Tj(°C) 1 0.96 -25 4/12 0 25 50 75 100 125 25 50 75 100 125 SMP100LC Figure 7. Application information Variation of thermal impedance junction to ambient versus pulse duration (PCB - FR4, SCu = 35µm, recommended pad layout) Figure 8. Relative variation of junction capacitance versus reverse voltage applied (typical values) C [VR] / C [VR=2V] Zth(j-a)/Rth(j-a) 100 1.4 F =1MHz VRMS = 1V Tj = 25°C 1.2 1.0 0.8 10 0.6 0.4 0.2 tp(s) 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2 1 5 2 10 20 50 100 300 Application information In wireline applications, analog or digital, both central office and subscriber sides have to be protected. This function is assumed by a combined series / parallel protection stage. Figure 9. Examples of protection stages for line cards Ring relay Line Line Ex. Analog line card Protection stage 2 VR(V) 0.0 Protection stage 1 1E-3 Ex. xDSL line card or terminal In such a stage, parallel function is assumed by one or several Trisil, and is used to protect against short duration surge (lightning). During this kind of surges the Trisil limits the voltage across the device to be protected at its break over value and then fires. The fuse assumes the series function, and is used to protect the module against long duration or very high current mains disturbances (50/60Hz). It acts by safe circuit opening. Lightning surge and mains disturbance surges are defined by standards like GR1089, FCC part 68, ITU-T K20. Figure 10. Typical circuits Fuse TCP 1.25A Tip L Tip S Fuse TCP 1.25A SMP100LC-xxx T1 SMP100LC-xxx Gnd Gnd SMP100LC-xxx T2 Fuse TCP 1.25A Ring L Typical circuit for subscriber side Ring S Typical circuit for central office side 5/12 Application information SMP100LC Figure 11. Test method of the board with fuse and Trisil I surge Surge Generator Line side Device to be protected Test board V Oscilloscope Current probe Voltage probe These topologies, using SMP100LC from ST and TCP1.25A from Cooper Bussmann, have been functionally validated with a Trisil glued on the PCB. Following example was performed with SMP100LC-270 Trisil. For more information, see Application Note AN2064. Figure 12. Trisil turns on during lightning strike I surge (100A/div) V (50V/div) Test conditions: 2/10 µs + and - 2.5 and 5 kV, 500 A (10 pulses of each polarity), Tamb = 25° C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements. 6/12 SMP100LC Application information Figure 13. Trisil action while fuse remains operational I surge (2A/div) V (100V/div) Test conditions: 600 V, 3 A, 1.1 s (first level), Tamb = 25° C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements. Figure 14. High current AC power test: the fuse acts like a switch by opening the circuit I surge (10A/div) V (100V/div) Test conditions: 277 V, 25 A (second level), Tamb = 25° C Test result: Fuse safely opened and Trisil OK after test in accordance with GR1089 requirements. 7/12 Application information SMP100LC Figure 15. Test circuit 1 for Dynamic IBO and VBO parameters 100 V / µs, di /dt < 10 A / µs, Ipp = 100 A 2Ω 83 Ω 45 Ω 10 µF U 66 Ω 46 µH 0.36 nF 470 Ω KeyTek 'System 2' generator with PN246I module 1 kV / µs, di /dt < 10 A / µs, Ipp = 10 A 250 Ω 26 µH 60 µF U 47 Ω 46 µH 12 Ω KeyTek 'System 2' generator with PN246I module Figure 16. Test circuit 2 for IBO and VBO parameters K ton = 20ms R1 = 140Ω R2 = 240Ω 220V 50Hz DUT Vout 1/4 IBO measurement TEST PROCEDURE Pulse test duration (tp = 20ms): ● for Bidirectional devices = Switch K is closed ● for Unidirectional devices = Switch K is open VOUT selection: ● Device with VBO < 200V ➔ VOUT = 250 VRMS, R1 = 140Ω ● Device with VBO ≥ 200V ➔ VOUT = 480 VRMS, R2 = 240Ω 8/12 VBO measurement SMP100LC Ordering information scheme Figure 17. Test circuit 3 for dynamic IH parameter R VBAT = - 48 V Surge generator D.U.T This is a GO-NOGO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE 1/ Adjust the current level at the IH value by short circuiting the AK of the D.U.T. 2/ Fire the D.U.T. with a surge current ➔ IPP = 10A, 10/1000µs. 3/ The D.U.T. will come back off-state within 50ms maximum. 3 Ordering information scheme SMP 100 LC - xxx Trisil Surface Mount Repetitive Peak Pulse Current 100 = 100A Capacitance LC = Low Capacitance Voltage 65 = 65V 9/12 Package information 4 SMP100LC Package information Table 5. SMB Dimensions Dimensions Ref. Millimeters Inches E1 D E A1 A2 C L b Min. Max. Min. Max. A1 1.90 2.45 0.075 0.096 A2 0.05 0.20 0.002 0.008 b 1.95 2.20 0.077 0.087 c 0.15 0.40 0.006 0.016 E 5.10 5.60 0.201 0.220 E1 4.05 4.60 0.159 0.181 D 3.30 3.95 0.130 0.156 L 0.75 1.50 0.030 0.059 Figure 18. Footprint (dimensions in mm) 1.62 2.60 1.62 2.18 5.84 10/12 SMP100LC 5 Ordering information Ordering information Part Number 6 Marking SMP100LC-8 PL8 SMP100LC-25 L25 SMP100LC-35 L35 SMP100LC-65 L06 SMP100LC-90 L09 SMP100LC-120 L12 SMP100LC-140 L14 SMP100LC-160 L16 SMP100LC-200 L20 SMP100LC-230 L23 SMP100LC-270 L27 SMP100LC-320 L32 SMP100LC-360 L36 SMP100LC-400 L40 Package Weight Base qty Delivery mode SMB 0.11 g 2500 Tape & reel Revision history Date Revision Changes 09-Nov-2004 9 Absolute ratings values, table 3 on page 2, updated. 07-Dec-2004 10 SMP100LC-320, SMP100LC-360 and SMP100LC-400 addition. 20-Jun-2005 11 Telecom Circuit Protector added in Description. 05-Mar-2007 12 Reformatted to current standards. SMB Package information updated. Standards compliance paragraphs added to Description 11/12 SMP100LC Please Read Carefully: Information in this document is provided solely in connection with ST products. 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