SMP100LC ® TRISIL™ FOR TELECOM EQUIPMENT PROTECTION FEATURES ■ Bidirectional crowbar protection ■ Voltage range from 8V to 400V ■ Low capacitance from 20pF to 45pF @ 50V ■ Low leakage current : IR = 2µA max ■ Holding current: IH = 150 mA min ■ Repetitive peak pulse current: IPP = 100 A (10/1000µs) MAIN APPLICATIONS Any sensitive equipment requiring protection against lightning strikes and power crossing. These devices are dedicated to central office protection as they comply with the most stressfull standards. Their Low Capacitances make them suitable for ADSL. SMB (JEDEC DO-214AA) Table 1: Order Codes Part Number Marking SMP100LC-8 PL8 SMP100LC-25 L25 SMP100LC-35 L35 SMP100LC-65 L06 SMP100LC-90 L09 DESCRIPTION The SMP100LC is a series of low capacitance transient surge arrestors designed for the protection of high debit rate communication equipment. Its low capacitance avoids any distortion of the signal and is compatible with digital transmission line cards (xDSL, ISDN...). SMP100LC series tested and confirmed compatible with Cooper Bussmann Telecom Circuit Protector TCP 1.25A. SMP100LC-120 L12 SMP100LC-140 L14 SMP100LC-160 L16 SMP100LC-200 L20 SMP100LC-230 L23 SMP100LC-270 L27 SMP100LC-320 L32 SMP100LC-360 L36 BENEFITS SMP100LC-400 L40 Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. They are used to help equipment to meet main standards such as UL60950, IEC950 / CSA C22.2 and UL1459. They have UL94 V0 approved resin. SMB package is JEDEC registered (DO-214AA). Trisils comply with the following standards GR1089 Core, ITU-T-K20/K21, VDE0433, VDE0878, IEC61000-4-5 and FCC part 68. June 2005 Figure 1: Schematic Diagram REV. 11 1/10 SMP100LC Table 2: In compliance with the following standards STANDARD Peak Surge Voltage (V) Waveform Voltage Required peak current (A) Current waveform Minimum serial resistor to meet standard (Ω) GR-1089 Core First level 2500 1000 2/10 µs 10/1000 µs 500 100 2/10 µs 10/1000 µs 0 0 GR-1089 Core Second level 5000 2/10 µs 500 2/10 µs 0 GR-1089 Core Intra-building 1500 2/10 µs 100 2/10 µs 0 ITU-T-K20/K21 6000 1500 10/700 µs 150 37.5 5/310 µs 0 0 ITU-T-K20 (IEC61000-4-2) 8000 15000 1/60 ns VDE0433 4000 2000 10/700 µs 100 50 5/310 µs 0 0 VDE0878 4000 2000 1.2/50 µs 100 50 1/20 µs 0 0 IEC61000-4-5 4000 4000 10/700 µs 1.2/50 µs 100 100 5/310 µs 8/20 µs 0 0 FCC Part 68, lightning surge type A 1500 800 10/160 µs 10/560 µs 200 100 10/160 µs 10/560 µs 0 0 FCC Part 68, lightning surge type B 1000 9/720 µs 25 5/320 µs 0 ESD contact discharge ESD air discharge 0 0 Table 3: Absolute Ratings (Tamb = 25°C) Symbol Parameter IPP Repetitive peak pulse current (see figure 2) IFS Fail-safe mode : maximum current (note 1) ITSM I2t Tstg Tj TL Non repetitive surge peak on-state current (sinusoidal) I2t value for fusing Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10 s. Note 1: in fail safe mode, the device acts as a short circuit 2/10 Value Unit 100 400 140 150 200 400 500 A 8/20 µs 5 kA t = 0.2 s t=1s t=2s t = 15 mn 24 15 12 4 A t = 16.6 ms t = 20 ms 20 21 A2s -55 to 150 150 °C 260 °C 10/1000 µs 8/20 µs 10/560 µs 5/310 µs 10/160 µs 1/20 µs 2/10 µs SMP100LC Table 4: Thermal Resistances Symbol Parameter Rth(j-a) Junction to ambient (with recommended footprint) Rth(j-l) Junction to leads Value 100 20 Unit °C/W °C/W Table 5: Electrical Characteristics (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VBO Breakover voltage IRM Leakage current IPP Peak pulse current IBO Breakover current IH Holding current VR Continuous reverse voltage IR Leakage current at VR C Capacitance IRM @ VRM Types max. IR @ VR max. max. note1 µA V µA Dynamic VBO Static VBO @ IBO max. note 2 max. note 3 V V V mA IH C C min. typ. typ. note 4 note 5 note 6 mA pF pF 50 (typ.) NA 75 SMP100LC-8 6 8 25 15 SMP100LC-25 22 25 40 35 NA 65 SMP100LC-35 32 35 55 55 NA 55 SMP100LC-65 55 65 85 85 45 90 SMP100LC-90 81 90 120 125 40 80 SMP100LC-120 108 120 155 160 35 75 140 185 190 30 65 SMP100LC-140 SMP100LC-160 2 120 800 150 160 205 200 30 65 SMP100LC-200 180 200 255 250 30 60 SMP100LC-230 207 230 295 285 30 60 SMP100LC-270 243 270 345 335 30 60 SMP100LC-320 290 320 400 390 25 50 SMP100LC-360 325 360 460 450 25 50 SMP100LC-400 360 400 540 530 20 45 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 144 5 IR measured at VR guarantee VBR min ≥ VR see functional test circuit 1 see test circuit 2 see functional holding current test circuit 3 VR = 50V bias, VRMS=1V, F=1MHz VR = 2V bias, VRMS=1V, F=1MHz 3/10 SMP100LC Figure 2: Pulse waveform %IPP Figure 3: Non repetitive surge peak on-state current versus overload duration ITSM(A) Repetitive peak pulse current 70 tr = rise time (µs) tp = pulse duration time (µs) 100 F=50Hz Tj initial = 25°C 60 50 40 50 30 20 10 0 tr t(s) t tp 0 1E-2 Figure 4: On-state voltage versus on-state current (typical values) 1E-1 1E+0 1E+1 1E+2 1E+3 Figure 5: Relative variation of holding current versus junction temperature IH[Tj] / IH[Tj=25°C] IT(A) 100 2.0 Tj initial = 25°C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 VT(V) Tj(°C) 0.0 10 0 1 2 3 4 5 6 7 -25 8 Figure 6: Relative variation of breakover voltage versus junction temperature 0 25 50 75 100 125 Figure 7: Relative variation of leakage current versus junction temperature (typical values) VBO[Tj] / VBO[Tj=25°C] IR[Tj] / IR[Tj=25°C] 1.08 2000 1000 1.06 1.04 100 1.02 1.00 10 0.98 Tj(°C) Tj(°C) 1 0.96 -25 4/10 0 25 50 75 100 125 25 50 75 100 125 SMP100LC Figure 8: Variation of thermal impedance junction to ambient versus pulse duration (Printed circuit board FR4, SCu=35µm, recommended pad layout) Figure 9: Relative variation of junction capacitance versus reverse voltage applied (typical values) C [VR] / C [VR=2V] Zth(j-a)/Rth(j-a) 100 1.4 F =1MHz VRMS = 1V Tj = 25°C 1.2 1.0 0.8 10 0.6 0.4 0.2 tp(s) 1 1E-3 VR(V) 0.0 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2 1 5 2 10 20 50 100 300 APPLICATION NOTE In wireline applications, analog or digital, both central office and subscriber sides have to be protected. This function is assumed by a combined series / parallel protection stage. Line Ex. Analog line card Protection stage Line Protection stage Ring relay Ex. ADSL line card or terminal In such a stage, parallel function is assumed by one or several Trisil, and is used to protect against short duration surge (lightning). During this kind of surges the Trisil limits the voltage across the device to be protected at its break over value and then fires. The fuse assumes the series function, and is used to protect the module against long duration or very high current mains disturbances (50/60Hz). It acts by safe circuits opening. Lightning surge and mains disturbance surges are defined by standards like GR1089, FCC part 68, ITU-T K20. Fuse TCP 1.25A Tip L Tip S Fuse TCP 1.25A SMP100LC-xxx T1 SMP100LC-xxx Gnd Gnd SMP100LC-xxx T2 Fuse TCP 1.25A Ring L Typical circuit for subscriber side Ring S Typical circuit for central office side 5/10 SMP100LC Following figure shows the test method of the board having Fuse and Trisil. I surge Surge Generator Line side Following curve shows the turn on of the Trisil during lightning surge. Device to be protected Test board V I surge (100A/div) Oscilloscope V (50V/div) Current probe Voltage probe These topologies, using SMP100LC from ST and TCP1.25A from Cooper Bussmann, have been functionally validated with a Trisil glued on the PCB. Following example was performed with SMP100LC-270 Trisil. For more information, see Application Note AN2064. Test conditions: 2/10µs + and -2.5 and 5kV 500A (10 pulses of each polarity), Tamb = 25°C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements Following curve shows Trisil action while the fuse remains operational. In case of high current power cross test, the fuse acts like a switch by opening the circuit. I surge (2A/div) V (100V/div) Test conditions: 600V 3A 1.1s (first level), Tamb = 25°C Test result: Fuse and Trisil OK after test in accordance with GR1089 requirements 6/10 I surge (10A/div) V (100V/div) Test conditions: 277V 25A (second level), Tamb = 25°C Test result: Fuse safety opened and Trisil OK after test in accordance with GR1089 requirements SMP100LC Figure 10: Test circuit 1 for Dynamic IBO and VBO parameters 100 V / µs, di /dt < 10 A / µs, Ipp = 100 A 2Ω 83 Ω 45 Ω 10 µF U 66 Ω 46 µH 0.36 nF 470 Ω KeyTek 'System 2' generator with PN246I module 1 kV / µs, di /dt < 10 A / µs, Ipp = 10 A 250 Ω 26 µH 60 µF U 47 Ω 46 µH 12 Ω KeyTek 'System 2' generator with PN246I module Figure 11: Test circuit 2 for IBO and VBO parameters K ton = 20ms R1 = 140Ω R2 = 240Ω 220V 50Hz DUT Vout VBO measurement 1/4 IBO measurement TEST PROCEDURE Pulse test duration (tp = 20ms): ● for Bidirectional devices = Switch K is closed ● for Unidirectional devices = Switch K is open VOUT selection: ● Device with VBO < 200V ➔ VOUT = 250 VRMS, R1 = 140Ω ● Device with VBO ≥ 200V ➔ VOUT = 480 VRMS, R2 = 240Ω 7/10 SMP100LC Figure 12: Test circuit 3 for dynamic IH parameter R VBAT = - 48 V Surge generator D.U.T This is a GO-NOGO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE 1/ Adjust the current level at the IH value by short circuiting the AK of the D.U.T. 2/ Fire the D.U.T. with a surge current ➔ IPP = 10A, 10/1000µs. 3/ The D.U.T. will come back off-state within 50ms maximum. Figure 13: Ordering Information Scheme SMP Trisil Surface Mount Repetitive Peak Pulse Current 100 = 100A Capacitance LC = Low Capacitance Voltage 65 = 65V 8/10 100 LC - xxx SMP100LC Figure 14: SMB Package Mechanical data E1 REF. D A1 A2 b c E E1 D L E A1 A2 C L b DIMENSIONS Millimeters Inches Min. Max. Min. Max. 1.90 2.45 0.075 0.096 0.05 0.20 0.002 0.008 1.95 2.20 0.077 0.087 0.15 0.41 0.006 0.016 5.10 5.60 0.201 0.220 4.05 4.60 0.159 0.181 3.30 3.95 0.130 0.156 0.75 1.60 0.030 0.063 Figure 15: Foot Print Dimensions (in millimeters) 2.3 1.52 2.75 1.52 Table 6: Ordering Information Part Number SMP100LC-8 SMP100LC-25 SMP100LC-35 SMP100LC-65 SMP100LC-90 SMP100LC-120 SMP100LC-140 SMP100LC-160 SMP100LC-200 SMP100LC-230 SMP100LC-270 SMP100LC-320 SMP100LC-360 SMP100LC-400 Marking PL8 L25 L35 L06 L09 L12 L14 L16 L20 L23 L27 L32 L36 L40 Package Weight Base qty Delivery mode SMB 0.11 g 2500 Tape & reel Date 09-Nov-2004 Revision 9 07-Dec-2004 10 20-Jun-2005 11 Description of Changes Absolute ratings values, table 3 on page 2, updated. SMP100LC-320, SMP100LC-360 and SMP100LC-400 addition. Telecom Circuit Protector added Table 7: Revision History 9/10 SMP100LC Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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