STD96N3LLH6 N-channel 30 V, 0.0037 Ω, 80 A, DPAK STripFET™ VI DeepGATE™ Power MOSFET Features Type VDSS RDS(on) max ID STD96N3LLH6 30 V 0.0042 Ω 80 A ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ High avalanche ruggedness ■ Low gate drive power losses 3 1 DPAK Application ■ Switching applications – Automotive Figure 1. Description Internal schematic diagram This product is an N-channel Power MOSFET that utilizes the 6th generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages. D (TAB or 2) G(1) S(3) AM01474v1 Table 1. Device summary Order codes Marking Package Packaging STD96N3LLH6 96N3LLH6 DPAK Tape and reel January 2011 Doc ID 18432 Rev 1 1/15 www.st.com 15 Contents STD96N3LLH6 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) .............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 .............................................. 8 Doc ID 18432 Rev 1 STD96N3LLH6 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 30 V ± 20 V Drain current (continuous) at TC = 25 °C 80 A Drain current (continuous) at TC = 100 °C 61 A Drain current (pulsed) 320 A Total dissipation at TC = 25 °C 70 W Derating factor 0.47 W/°C Single pulse avalanche energy 150 mJ -55 to 175 °C 175 °C Value Unit VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ID (1) ID IDM (2) PTOT EAS (3) Tstg Storage temperature Max. operating junction temperature Tj 1. Limited by wire bonding. 2. Pulse width limited by safe operating area. 3. Starting Tj = 25°C, IAV = 55 A, L = 0.1 mH Table 3. Symbol Thermal data Parameter Rthj-case Thermal resistance junction-case max 2.14 °C/W Rthj-amb Thermal resistance junction-ambient max 100 °C/W Thermal resistance junction-pcb max 35 °C/W Maximum lead temperature for soldering purpose 275 °C Rthj-pcb Tl (1) 1. When mounted on FR-4 board of 1 inch2, 2 oz Cu. Doc ID 18432 Rev 1 3/15 Electrical characteristics 2 STD96N3LLH6 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown Voltage ID = 250 µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 30 V VDS = 30 V, Tc = 125 °C IGSS Gate body leakage current (VDS = 0) VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source on resistance VGS = 10 V, ID = 40 A 0.0037 0.0042 RDS(on) Ω VGS = 5.5 V, ID = 40 A 0.0055 0.007 Ω Min Typ. Max. Unit - pF pF pF - nC nC nC V(BR)DSS Table 5. Symbol 30 V 1 Test conditions Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25 V, f=1 MHz, VGS = 0 - 2200 400 280 Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 15 V, ID = 80 A VGS = 4.5 V Figure 13 - 20 8.2 7.5 Pre Vth gate-to-source charge Post Vth gate-to-source charge VDD = 15 V, ID = 80 A Figure 18 - Gate input resistance f = 1 MHz gate bias Bias = 0 test signal level = 20 mV open drain - Qgs2 RG 1 10 µA µA ±100 nA 2.5 V Dynamic Parameter Qgs1 4/15 Static Doc ID 18432 Rev 1 3.4 nC - 6.2 1 nC - Ω STD96N3LLH6 Electrical characteristics Table 6. Symbol Switching on/off (inductive load) Parameter Test conditions Min. Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD = 15 V, ID = 40 A, RG = 4.7 Ω, VGS = 5 V Figure 12 - 19 91 - ns ns td(off) tf Turn-off delay time Fall time VDD = 15 V, ID = 40 A, RG = 4.7 Ω, VGS = 5 V Figure 12 - 24.5 23.4 - ns ns Min. Typ. Max. Unit - 80 320 A A 1.1 V Table 7. Symbol ISD ISDM (1) VSD(2) trr Qrr IRRM Source drain diode Parameter Test conditions Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 40 A, VGS = 0 - Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 80 A, di/dt = 100 A/µs, VDD = 24 V Figure 14 - 28.6 22.8 1.6 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 18432 Rev 1 5/15 Electrical characteristics STD96N3LLH6 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM03376v1 ID (A) 280dpc K δ=0.5 s ai re n) s a DS(o R n i max tio ra by e d Op ite Lim hi nt 100 0.2 0.1 100µs 10 0.05 -1 10 0.02 1ms Tj=175°C Tc=25°C 1 Sinlge pulse tp Single pulse -2 0.1 0.1 10 1 Figure 4. VDS(V) Output characteristics VGS=10V 7V 300 10 -5 10 -4 τ -2 -3 10 Figure 5. AM03379v1 ID (A) Zth=k Rthj-c δ=tp/τ 0.01 10ms -1 10 10 tp (s) 10 Transfer characteristics ID (A) AM03380v1 VDS=2V 300 6V 250 250 200 200 5V 150 150 4V 100 100 50 50 3V 0 0 Figure 6. 2 4 Normalized BVDSS vs temperature AM03381v1 BVDSS (norm) 0 0 VDS(V) Figure 7. 2 4 6 8 Static drain source on resistance AM03382v1 RDS(on) (mΩ) @250µA VGS(V) 7 VGS=10V 6 1.05 5 1.00 4 3 2 0.95 1 0.90 -55 -30 6/15 -5 20 45 70 95 120 145 TJ(°C) Doc ID 18432 Rev 1 0 0 10 20 30 40 ID(A) STD96N3LLH6 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM03378v1 VGS (V) VDD=15V 12 Capacitance variations AM03377v1 C (pF) ID=80A 10 Ciss 8 1000 6 Coss 4 Crss 2 100 0 0 10 20 30 40 Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) 5 50 Qg(nC) AM03383v1 @250µA 20 20 VDS(V) AM03384v1 RDS(on) (norm) 1.8 1.0 1.6 0.8 1.4 0.6 1.2 0.4 1.0 0.2 0.8 20 45 70 95 120 145 TJ(°C) 15 Figure 11. Normalized on resistance vs temperature 1.2 0 -55 -30 -5 10 VGS=10V ID=40A 0.6 -55 -30 -5 20 45 70 95 120 145 TJ(°C) Doc ID 18432 Rev 1 7/15 Test circuits 3 STD96N3LLH6 Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 µF 2200 RL µF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 µF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100µH S 3.3 µF B 25 Ω 1000 µF D VDD 2200 µF 3.3 µF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 16. Unclamped inductive waveform AM01471v1 Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/15 0 Doc ID 18432 Rev 1 10% AM01473v1 STD96N3LLH6 Test circuits Figure 18. Gate charge waveform Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Doc ID 18432 Rev 1 9/15 Package mechanical data 4 STD96N3LLH6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. DPAK (TO-252) mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 L1 2.80 L2 0.80 L4 0.60 1 R V2 10/15 Max. 0.20 0° 8° Doc ID 18432 Rev 1 STD96N3LLH6 Package mechanical data Figure 19. DPAK (TO-252) drawing 0068772_G Doc ID 18432 Rev 1 11/15 Packaging mechanical data 5 STD96N3LLH6 Packaging mechanical data Table 9. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 Figure 20. DPAK footprint(a) 6.7 1.8 3 1.6 2.3 6.7 2.3 1.6 a. All dimension are in millimeters 12/15 Doc ID 18432 Rev 1 AM08850v1 STD96N3LLH6 Packaging mechanical data Figure 21. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 22. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Doc ID 18432 Rev 1 13/15 Revision history 6 STD96N3LLH6 Revision history Table 10. 14/15 Document revision history Date Revision 27-Jan-2011 1 Changes First release. Doc ID 18432 Rev 1 STD96N3LLH6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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