Dual N-Channel JFET Switch CORPORATION U401 – U406 FEATURES • Minimum System Error and Calibration • Low Drift With Temperature From Low Power Supply Voltages • Operates • High Output Impedance PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 50V Gate Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Storage Temperature Range . . . . . . . . . . . . . -65oC to +200oC Operating Temperature Range . . . . . . . . . . . -55oC to +150oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC Power Dissipation (TA = 85oC) Derate above 25oC TO-71 One Side 300mW 2.6mW/ oC Both Sides 500mW 5mW/ oC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING INFORMATION S2 CJ2 G2 D2 G1 D1 S1 Part Package U401-6 XU401-6 Hermetic TO-71 Sorted Chips in Carriers Temperature Range -55oC to +150oC -55oC to +150oC U401 – U406 CORPORATION ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified) SYMBOL PARAMETER U401 MIN BVGSS Gate-Source Breakdown Voltage IGSS Gate Reverse Current (Note 2) VGS(off) Gate-Source Cutoff Voltage VGS(on) Gate-Source Voltage (on) IDSS Saturation Drain Current (Note 3) IG Operating Gate Current (Note 2) U402 MAX -50 MIN MIN -50 -25 -.5 MAX U403 -2.5 -50 -25 -.5 MAX U404 MIN -50 -25 -2.5 -.5 MAX -2.5 U405 MIN -50 -25 -.5 MAX -2.5 U406 MIN -50 -25 -.5 -2.5 -25 -.5 UNITS TEST CONDITIONS MAX V VDS = 0, IG = -1µA pA VDS = 0, V GS = -30V VDS = 15V, ID = 1nA -2.5 V -2.3 0.5 10.0 -2.3 0.5 -2.3 10.0 0.5 10.0 -2.3 0.5 10.0 -2.3 0.5 10.0 VDG = 15V, ID = 200µA -2.3 0.5 10.0 mA VDS = 10V, VGS = 0 VDG = 15V, ID = 200µA -15 -15 -15 -15 -15 -15 pA -10 -10 -10 -10 -10 -10 nA BVG1-G2 Gate-Gate Breakdown Voltage ±50 gfs Common-Source Forward Transconductance (Note 3) 2000 7000 2000 7000 ±50 ±50 2000 ±50 7000 2000 ±50 7000 2000 ±50 7000 2000 V 7000 gos Common-Source Output Conductance gfs Common-Source Forward Transconductance gos Common-Source Output Conductance 2.0 2.0 2.0 2.0 2.0 2.0 Ciss Common-Source Input Capacitance (Note 6) 8.0 8.0 8.0 8.0 8.0 8.0 Crss Common-Source Reverse Transfer Capacitance (Note 6) 3.0 3.0 3.0 3.0 3.0 3.0 en Equivalent Short-Circuit Input Noise Voltage 20 20 20 20 20 20 CMRR Common-Mode Rejection Ratio | VGS1 −VGS2 | Differential Gate-Source Voltage 5 10 10 15 20 | ∆VGS1 −VGS2 | ∆T Gate-Source Voltage Differential Drift (Note 4) 10 10 25 25 40 20 20 1000 2000 1000 2000 20 1000 2000 20 1000 2000 20 1000 2000 20 1000 TA = 125oC VDS = 0, V GS = 0, IG = ±1µA VDS = 10V, VGS = 0 f = 1kHz µS 2000 f = 1kHz VDG = 15V, ID = 200µA pF 95 95 95 NOTES: 1. Per transistor. 2. Approximately doubles for every 10oC increase in TA. 3. Pulse test duration = 300µs; duty cycle ≤3%. 4. Measured at end points TA, TB, TC. ∆VDD 5. CMRR = 20 log10 , ∆VDD = 10V. ∆ | V −V | GS GS 1 2 6. For design reference only, not 100% tested. 95 nV √ Hz f = 1MHz VDS = 15V, VGS = 0 f = 10Hz (Note 6) dB VDG = 10 to 20V, ID = 200µA (Note 5, 6) 40 mV VDG = 10V, ID = 200µA 80 µV/ oC 90 VDG = 10V, ID = 200µA TA = -55oC TB = +25oC TC = +125oC