TBB1002 Twin Build in Biasing Circuit MOS FET IC VHF/UHF RF Amplifier ADE-208-987F (Z) 7th. Edition Dec. 2000 Features • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Suitable for World Standard Tuner RF amplifier. Very useful for total tuner cost reduction. Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0 conditions. • Provide mini mold packages; CMPAK-6 Outline CMPAK-6 6 5 4 2 1 Notes: 1. 2. 3 1. Gate-1(1) 2. Source 3. Drain(1) 4. Drain(2) 5. Gate-2 6. Gate-1(2) Marking is “BM”. TBB1002 is individual type number of HITACHI TWIN BBFET. TBB1002 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage VDS 6 V Gate1 to source voltage VG1S +6 -0 V Gate2 to source voltage VG2S +6 -0 V Drain current ID 30 mA 250 mW *3 Channel power dissipation Pch Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Notes: 3. Value on the glass epoxy board (49mm × 38mm × 1mm). Electrical Characteristics (Ta = 25°C) The below specification are applicable for UHF unit (FET1) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS 6 — — V I D = 200µA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V(BR)G1SS +6 — — V I G1 = +10µA, VG2S = VDS = 0 Gate2 to source breakdown voltage V(BR)G2SS +6 — — V I G2 = +10µA, VG1S = VDS = 0 Gate1 to source cutoff current I G1SS — — +100 nA VG1S = +5V, V G2S = VDS = 0 Gate2 to source cutoff current I G2SS — — +100 nA VG2S = +5V, V G1S = VDS = 0 Gate1 to source cutoff voltage VG1S(off) 0.5 0.75 1.0 V VDS = 5V, VG2S = 4V, ID = 100µA Gate2 to source cutoff voltage VG2S(off) 0.5 0.75 1.0 V VDS = 5V, VG1S = 5V, ID = 100µA Drain current I D(op) 13 17 21 mA VDS = 5V, VG1 = 5V VG2S = 4V, RG = 100kΩ Forward transfer admittance |yfs| 21 26 31 mS VDS = 5V, VG1 = 5V, VG2S =4V RG = 100kΩ, f = 1kHz Input capacitance c iss 1.4 1.8 2.2 pF VDS = 5V, VG1 = 5V Output capacitance c oss 1.0 1.4 1.8 pF VG2S =4V, RG = 100kΩ Reverse transfer capacitance c rss — 0.02 0.04 pF f = 1MHz Power gain PG 16 21 — dB VDS = VG1 = 5V, VG2S = 4V RG = 100kΩ, f = 900MHz Zi=S11*, Zo=S22*(:PG) Noise figure NF — 1.7 2.5 dB Zi=S11opt (:NF) 2 TBB1002 Electrical Characteristics (Ta = 25°C) The below specification are applicable for VHF unit (FET2) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS 6 — — V I D = 200µA, VG1S = VG2S = 0 Gate1 to source breakdown voltage V(BR)G1SS +6 — — V I G1 = +10µA, VG2S = VDS = 0 Gate2 to source breakdown voltage V(BR)G2SS +6 — — V I G2 = +10µA, VG1S = VDS = 0 Gate1 to source cutoff current I G1SS — — +100 nA VG1S = +5V, V G2S = VDS = 0 Gate2 to source cutoff current I G2SS — — +100 nA VG2S = +5V, V G1S = VDS = 0 Gate1 to source cutoff voltage VG1S(off) 0.5 0.75 1.0 V VDS = 5V, VG2S = 4V, ID = 100µA Gate2 to source cutoff voltage VG2S(off) 0.5 0.75 1.0 V VDS = 5V, VG1S = 5V, ID = 100µA Drain current I D(op) 14 18 22 mA VDS = 5V, VG1 = 5V, VG2S = 4V, RG = 82kΩ Forward transfer admittance |yfs| 20 25 30 mS VDS = 5V, VG1 = 5V, VG2S =4V, RG = 82kΩ, f = 1kHz Input capacitance c iss 2.2 2.6 3.0 pF VDS = 5V, VG1 = 5V Output capacitance c oss 1.2 1.6 2.0 pF VG2S =4V, RG = 82kΩ Reverse transfer capacitance c rss — 0.03 0.05 pF f = 1MHz Power gain PG 22 27 — dB VDS = VG1 = 5V, VG2S = 4V Noise figure NF — 1.2 1.7 dB RG = 82kΩ, f = 200MHz 3 TBB1002 Test Circuits • DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) Measurment of FET1 Gate 2 VG2 Open Open RG A Gate 1 VG1 ID Drain VD Source Measurment of FET2 VG2 Gate 2 RG Drain Gate 1 A VD VG1 Open Open Source 4 ID TBB1002 • Equivalent Circuit No.1 No.6 Gate-1(1) Gate-1(2) BBFET-(1) BBFET-(2) No.2 No.5 Source Gate-2 No.3 No.4 Drain(1) Drain(2) • 200 MHz Power Gain, Noise Figure Test Circuit 1000p 1000p 47k VT VG2 VT 1000p 47k 1000p 47k TWINBBFET Output(50Ω) 1000p L2 Input(50Ω) L1 10p max 1000p 1000p 36p 1SV70 RG RFC 82k 1SV70 1000p V D = V G1 Unit : Resistance (Ω) Capacitance (F) L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns 5 Typical Output Characteristics (FET1) 25 200 100 0 50 100 150 Ambient Temperature Ω 68 k kΩ kΩ 0 15 10 kΩ 0 12 kΩ 0 5 1 10 0k 18 5 0 200 G= 20 R 300 V G2S = 4 V V G1 = VDS 82 I D (mA) 400 Maximum Channel Power Dissipation Curve Drain Current Channel Power Dissipation Pch* (mW) TBB1002 Ta (°C) 1 2 3 Drain to Source Voltage Ω 4 5 V DS (V) * Value on the glass epoxy board (49mm × 38mm × 1mm) 20 Forward Transfer Admittance |y fs | (mS) Drain Current I D (mA) 25 Drain Current vs. Gate1 Voltage (FET1) V DS = 5 V R G = 120 kΩ 4V 15 3V 10 2V 5 VG2S = 1 V 0 6 1 2 Gate1 Voltage 3 V G1 4 (V) 5 50 40 Forward Transfer Admittance vs. Gate1 Voltage (FET1) V DS = 5 V V G2S = 4 V 30 R G = 68 k Ω 100 k Ω 150 kΩ 20 10 0 1 2 Gate1 Voltage 3 4 V G1 (V) 5 TBB1002 Drain Current vs. Gate Resistance (FET1) 4 V DS = 5 V V G1 = 5 V V G2S = 4 V 25 Input Capacitance Ciss (pF) Drain Current I D (mA) 30 Input Capacitance vs. Gate2 to Source Voltage (FET1) 20 15 10 5 0 10 20 50 100 200 V DS = 5 V V G1 = 5 V R G = 100 kΩ f = 1 MHz 1 0 1 2 3 4 Gate Resistance R G (kΩ) Gate2 to Source Voltage V G2S (V) Typical Output Characteristics (FET2) Drain Current vs. Gate1 Voltage (FET2) 25 kΩ 82 kΩ 0 12 Ω 0k 15 10 5 Drain Current 10 0 kΩ 15 I D (mA) kΩ 56 G= 68 20 kΩ V G2S = 4 V V G1 = VDS R I D (mA) 2 0 500 1000 25 Drain Current 3 20 V DS = 5 V R G = 82 kΩ 4V 15 3V 10 2V 5 VG2S = 1 V 0 1 2 3 Drain to Source Voltage 4 5 V DS (V) 0 1 2 Gate1 Voltage 3 V G1 4 (V) 5 7 50 30 V DS = 5 V V G2S = 4 V 40 R G = 56 k Ω 30 82 k Ω 20 120 kΩ 10 0 1 2 3 Gate1 Voltage 4 20 15 10 5 V G1 (V) 20 50 100 200 500 1000 Gate Resistance R G (kΩ) Power Gain vs. Gate Resistance (FET2) 40 4 35 Power Gain PG (dB) Input Capacitance Ciss (pF) V DS = 5 V V G1 = 5 V V G2S = 4 V 25 0 10 5 Input Capacitance vs. Gate2 to Source Voltage (FET2) 3 2 V DS = 5 V V G1 = 5 V R G = 82 kΩ f = 1 MHz 1 0 0 1 30 25 20 15 2 3 Gate2 to Source Voltage V G2S (V) 8 Drain Current vs. Gate Resistance (FET2) Forward Transfer Admittance vs. Gate1 Voltage (FET2) Drain Current I D (mA) Forward Transfer Admittance |y fs | (mS) TBB1002 4 10 10 V DS = 5 V V G1 = 5 V V G2S = 4 V f = 200 MHz 20 50 100 200 500 1000 Gate Resistance R G (kΩ) TBB1002 Noise Figure vs. Gate Resistance (FET2) Gain Reduction vs. Gate2 to Source Voltage (FET2) 0 3 V DS = 5 V V G1 = 5 V V G2S = 4 V f = 200 MHz Gain Reduction GR (dB) Noise Figure NF (dB) 4 2 1 0 10 10 20 30 40 50 20 50 100 200 500 1000 Gate Resistance R G (kΩ) V DS = V G1 = 5 V R G = 82 kΩ 4 3 2 1 0 Gate2 to Source Voltage V G2S (V) 9 TBB1002 Package Dimensions As of January, 2001 (0.65) + 0.1 0.15 – 0.05 0 to 0.1 0.9 ± 0.1 + 0.1 – 0.05 (0.2) 6-0.2 (0.65) 2.1 ± 0.3 2.0 ± 0.2 1.3 ± 0.2 (0.425) 1.25 ± 0.1 (0.425) Unit: mm Hitachi Code JEDEC EIAJ Mass (reference value) 10 CMPAK-6 — Conforms 0.006 g TBB1002 Cautions 1. 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