TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 300-mA 40-V LOW-DROPOUT REGULATOR WITH 25-µA QUIESCENT CURRENT Check for Samples: TPS7A6033-Q1, TPS7A6050-Q1 FEATURES 1 • • • • • • • • • Low Dropout Voltage – 300mV at IOUT = 150mA 4-V to 40-V Wide Input Voltage Range With up to 45-V Transients 300-mA Maximum Output Current Ultra Low Quiescent Current – IQUIESCENT = 25 µA (Typ) at Light Loads – ISLEEP < 2µA when EN = Low 3.3-V and 5-V Fixed Output Voltage Low-ESR Ceramic Output Stability Capacitor Integrated Power-On Reset – Programmable Delay – Open-Drain Reset Output Integrated Fault Protection – Short-Circuit/Over-Current Protection – Thermal Shutdown Low Input Voltage Tracking Thermally Enhanced Power Package – 5-pin TO-263 (KTT /D2PAK) – 5-pin TO-252 (KVU /DPAK) APPLICATIONS • • • • Qualified for Automotive Applications Infotainment Systems with Sleep Mode Body Control Modules Always ON Battery Applications – Gateway Applications – Remote Keyless Entry Systems – Immobilizers DESCRIPTION The TPS7A60xx/TPS7A61xx is a series of low dropout linear voltage regulators designed for low power consumption and quiescent current less than 25 µA in light load applications. These devices feature an integrated over current protection and are designed to achieve stable operation even with lowESR ceramic capacitors. Power-On Reset delay is implemented during device start up to indicate that the output voltage is stable and in regulation. The Power-On Reset delay is fixed (250 µs typical), and can also be programmed by an external capacitor. Low voltage tracking feature allows for a smaller input capacitor and can possibly eliminate the need of using a boost converter during cold crank conditions. Because of these features, these devices are well suited in power supplies for various automotive applications. TYPICAL REGULATOR STABILITY 10 VIN = 14V COUT = 10µF, 47µF TA = 27°C VOUT = 5V, 3.3V ESR of COUT (Ω) • 1 Stable Operation Over Entire Region 0.1 0.01 0.01 0.1 1 10 100 300 IOUT (mA) Figure 1. ESR vs Load Current for TPS7A60/1xx 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com TYPICAL APPLICATION SCHEMATIC TPS7A61xx TPS7A60xx VIN VIN VOUT VOUT VIN VIN VOUT V OUT COUT CIN COUT CIN RDELAY VEN RRST EN RRST CDLY GND nRST GND RESET Figure 2. Programmable Reset Delay Option nRST RESET Figure 3. Enable Option ORDERING INFORMATION (1) KEY FEATURE OUTPUT VOLTAGE 5 pin KTT 5V Programable Reset Delay (1) (2) 2 TOP-SIDE MARKING Reel of 500 TPS7A6050QKTTRQ1 7A6050Q1 Tube of 70 TPS7A6050QKVUQ1 5 pin KVU 7A6050Q1 Reel of 2500 TPS7A6050QKVURQ1 Product Preview 5 pin KTT Reel of 500 TPS7A6033QKTTRQ1 7A6033Q1 5 pin KVU Reel of 2500 TPS7A6033QKVURQ1 7A6033Q1 5V 5 pin KVU Reel of 2500 TPS7A6150QKVURQ1 Product Preview 3.3V 5 pin KVU Reel of 2500 TPS7A6133QKVURQ1 7A6133Q1 3.3V Enable ORDERABLE PART NUMBER (2) PACKAGE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) NO. DESCRIPTION VALUE UNIT 1.1 VIN, VEN Unregulated inputs (2) (3) 45 V 1.2 VOUT Regulated output 7 V 1.3 nRST Open drain reset output (2) 7 V 1.4 1.5 1.6 1.7 RDELAY θJP Output to charge an external cpacitor 7 V Thermal impedance junction to exposed pad KTT (D2PAK) package 1.3 °C/W Thermal impedance junction to exposed pad KVU (DPAK) package 1.1 °C/W 30.2 °C/W 29.3 °C/W 34.4 °C/W 38.6 °C/W Thermal impedance junction to ambient KTT (D2PAK) package θJA Thermal impedance junction to ambient KTT (D2PAK) package θJA (6) ESD Electrostatic discharge TOP Operating ambient temperature 1.10 TS Storage temperature range (5) (6) (5) Thermal impedance junction to ambient KVU (DPAK) package (5) 1.9 (2) (3) (4) (4) Thermal impedance junction to ambient KVU (DPAK) package (4) 1.8 (1) (2) 2 kV 125 °C -65 to +150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Absolute negative voltage on these pins not to go below –0.3V. Absolute maximum voltage for duration less than 480ms. The thermal data is based on JEDEC standard high K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure needs to be incorporated. The thermal data is based on JEDEC standard low K profile – JESD 51-3. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure needs to be incorporated. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. DISSIPATION RATINGS NO. JEDEC STANDARD PACKAGE TA < 25°C POWER RATING (W) DERATING FACTOR ABOVE TA = 25°C (°C/W) TA = 85°C POWER RATING (W) 2.1 JEDEC Standard PCB low K, JESD 51-3 5 pin KTT 3.63 34.4 1.89 5 pin KVU 3.24 38.6 1.68 5 pin KTT 4.14 30.2 2.15 5 pin KVU 4.27 29.3 2.22 2.2 2.3 JEDEC Standard PCB high K, JESD 51-5 2.4 RECOMMENDED OPERATING CONDITIONS NO. DESCRIPTION (1) MIN MAX UNIT 3.1 VIN, VEN Unregulated input voltage 4 40 V 3.2 nRST, RDELAY (2) Low voltage input/output 0 5.25 V 3.3 TJ Operating junction temperature range -40 150 °C TYP MAX UNIT (1) (2) Applicable for TPS7A61xx only. Applicable for TPS7A60xx only. ELECTRICAL CHARACTERISTICS VIN = 14V, TJ = -40ºC to 150ºC (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN 4. Input Voltage (VIN pin) 4.1 VIN Fixed 5V output, IOUT = 1mA Input voltage Fixed 3.3V output, IOUT = 1mA Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 5.3 40 4 40 Submit Documentation Feedback V 3 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 14V, TJ = -40ºC to 150ºC (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 25 40 µA 3 µA (1) 4.2 IQUIESCENT Quiescent current VIN = 8.2V to 18V, VEN = 5V, IOUT = 0.01mA to 0.75mA (1) 4.3 ISLEEP (1) Sleep/shutdown current VIN = 8.2V to 18V, VEN < 0.8V, IOUT = 0mA (no load), TA = 125°C 4.4 VIN-UVLO Under voltage lock out voltage Ramp VIN down until output is turned OFF 3.16 V 4.5 VIN(POWERUP) Power up voltage Ramp VIN up until output is turned ON 3.45 V 5. Enable Input (EN pin) 5.1 VIL (1) Logic input low level 5.2 VIH (1) Logic input high level 0 0.8 V 2.5 40 V -2 2 % VIN = 6V to 28V, IOUT = 10mA, VOUT = 5V 15 mV VIN = 6V to 28V, IOUT = 10mA, VOUT = 3.3V 20 mV IOUT = 10mA to 300mA, VIN= 14V, VOUT = 5V 25 mV IOUT = 10mA to 300mA,VIN = 14V, VOUT = 3.3V 35 mV 500 mV IOUT = 150mA 300 mV 6. Regulated Output Voltage (VOUT pin) 6.1 VOUT Regulated output voltage 6.2 ∆VLINE-REG Line regulation 6.3 Load regulation 6.4 VDROPOUT (2) Dropout voltage (VIN – VOUT) IOUT = 250mA 6.5 RSW (3) Switch resistance VIN to VOUT resistance 6.6 IOUT Output current VOUT in regulation 6.7 ICL Output current limit VOUT = 0V (VOUT pin is shorted to ground) 6.8 (1) (2) (3) 4 ∆VLOAD-REG Fixed VOUT value (3.3V or 5V as applicable), IOUT = 10mA to 300mA, VIN= VOUT + 1V to 16V PSRR (3) Power supply ripple rejection 2 Ω 0 300 mA 350 1000 mA VIN-RIPPLE = 0.5 Vpp, IOUT = 300mA, frequency = 100 Hz, VOUT = 5V and VOUT = 3.3V 60 VIN-RIPPLE = 0.5 Vpp, IOUT = 300mA, frequency = 150 kHz, VOUT = 5V and VOUT = 3.3V 30 dB Applicable for TPS7A61xx only. This test is done with VOUT in regulation and VIN – VOUT parameter is measured when VOUT (3.3V or 5.0V) drops by 100mV at specified loads. Specified by design – not tested Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) VIN = 14V, TJ = -40ºC to 150ºC (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 7. Reset (nRST pin) 7.1 VOL Reset pulled low IOL = 5mA 7.2 IOH Leakage current Reset pulled to VOUT through 5kΩ resistor 7.3 7.4 VTH(POR) UVTHRES Power-On Reset threshold VOUT power up above internally set tolerance, VOUT = 5V 4.5 V 1 µA 4.77 V VOUT power up above internally set tolerance, VOUT = 3.3V 3.07 VOUT falling below internally set tolerance, VOUT = 5V Reset threshold 4.65 0.4 4.5 4.65 4.77 V VOUT falling below internally set tolerance, VOUT = 3.3V 3.07 CDLY = 100pF 300 µs CDLY = 100nF 300 ms 7.5 tPOR (4) Power-On Reset delay 7.6 tPOR-PRESET Internally preset Power-On CDLY not connected in TPS7A60xx/ not available in Reset delay TPS7A61xx, VOUT = 5V and VOUT = 3.3V 250 µs 7.7 tDEGLITCH Reset deglitch time 5.5 µs 8. Reset Delay (RDELAY pin) 8.1 VTH(RDELAY) (5) Threshold to release nRST high 8.2 IDLY (5) Delay capacitor charging current 8.3 IOL (5) Delay capacitor discharging current Voltage at RDELAY pin is ramped up 0.75 Voltage at RDELAY pin = 1V 3 3.3 V 1 1.25 µA 5 mA 9. Operating Temperature Range 9.1 TJ Operating junction temperature 9.2 TSHUTDOWN Thermal shutdown trip point 9.3 THYST Thermal shutdown hysteresis (4) (5) -40 150 ºC 165 ºC 10 ºC Design Information – not tested; specified by characterization Applicable for TPS7A60xx only. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 5 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com DEVICE INFORMATION KTT PACKAGE (TOP VIEW) 1 2 3 4 KVU PACKAGE (TOP VIEW) 1 5 2 3 4 5 GND VIN nRST VIN GND RDELAY/ VOUT ENABLE nRST RDELAY/ VOUT ENABLE TERMINAL FUNCTIONS NO. NAME TYPE DESCRIPTION I Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor is connected between VIN pin and GND pin to dampen input line transients. 1 VIN 2 nRST O Reset pin: This is an output pin with an external pull up resistor connected to VOUT pin. 3 GND I/O Ground pin: This is signal ground pin of the IC. RDELAY O Reset delay timer pin (for TPS7A60xx only): This pin is used to program the reset delay timer using an external capacitor (CDLY) to ground. EN I Enable pin (for TPS7A61xx only): This is a high voltage tolerant input pin with an internal pull down. A high input to this pin activates the device and turns the regulator ON. This input can be connected to VIN terminal for self bias applications. If this pin is not connected, the device will stay disabled. VOUT O Regulated output voltage pin: This is a regulated voltage output (VOUT = 3.3V or 5V, as applicable) pin with a limitation on maximum output current. In order to achieve stable operation and prevent oscillation, an external output capacitor (COUT) with low ESR is connected between this pin and GND pin. 4 5 6 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 FUNCTIONAL BLOCK DIAGRAM VIN Band Gap VRef1 Temp . Sensor/ Thermal Shutdown VIN CIN UVLO Comp . with internal reference Q1 VRef1 Regulator Error Control Amp. Logic Control VOUT VOUT RDELAY CDLY Over Current Detection Charge Pump COUT RRST Voltage Supervisor with Reset Delay Q2 Oscillator RESET nRST GND Figure 4. TPS7A60xx Functional Block Diagram VIN Band Gap VRef1 VIN CIN Temp . Sensor / Thermal Shutdown UVLO Comp . with internal reference Q1 VRef1 Logic Control Regulator Error Control Amp. VOUT VEN VOUT EN Over Current Detection Charge Pump Oscillator COUT RRST Voltage Supervisor with Reset Delay Q2 RESET nRST GND Figure 5. TPS7A61xx Functional Block Diagram Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 7 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS ESR vs LOAD CURRENT 10 VIN = 14V COUT = 1µF TA = 27°C VOUT = 5V VIN = 14V COUT = 1µF TA = 27°C VOUT = 3.3V ESR of COUT (Ω) ESR of COUT (Ω) 10 ESR vs LOAD CURRENT 1 Stable Operation 0.1 1 Stable Operation 0.1 Unstable Operation 0.06 0.06 0.03 0.01 0.01 Unstable Operation 0.1 1 IOUT (mA) 10 30 100 300 0.03 0.01 0.01 QUIESCENT CURRENT vs LOAD CURRENT 80 55 IQUIESCENT (µA) I QUIESCENT (µA) 50 40 30 20 8 Submit Documentation Feedback 100 1000 IOUT = 250mA 30 10 10 300 35 25 1 IOUT (mA) 100 40 20 0.1 30 VOUT =5V, 3.3V 45 0.01 10 VIN =14V 50 60 0 0.001 1 IOUT (mA) QUIESCENT CURRENT vs AMBIENT AIR TEMPERATURE VIN = 14V TA = 25°C VOUT = 5V, 3.3V 70 0.1 15 IOUT = 1mA -50 0 50 T A (°C) 100 150 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) DROP OUT VOLTAGE (1) vs LOAD CURRENT QUIESCENT CURRENT vs INPUT VOLTAGE 0.4 700 VOUT = 5V, 3.3V TA= 25°C 0.3 500 400 300 IOUT = 100mA T A = 125°C 0.25 T A = 25°C 0.2 T A = -40°C 0.15 200 0.1 No Load 100 0 V OUT = 5V 0.35 VDROP OUT (V) I QUIESCENT (µA) 600 0.05 0 4 14 24 V IN (V) 34 0 40 50 OUTPUT VOLTAGE vs AMBIENT AIR TEMPERATURE 5.1 IOUT = 1mA 250 300 IOUT = 100mA TA = 25°C 5 5.04 4 5.02 VOUT (V) VOUT (V) 200 6 5.06 5 4.98 3 2 4.96 4.94 1 4.92 4.9 -50 (1) 150 IOUT (mA) OUTPUT VOLTAGE vs INPUT VOLTAGE VIN = 14V 5.08 100 0 50 TA (°C) 100 150 0 2 3 4 5 6 7 V IN (V) Drop out voltage is measured when the output voltage drops by 100mV from the regulated output voltage level. (For example, drop out voltage for TPS7A6050 is measured when the output voltage drops down to 4.9V from 5V.) Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 9 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT CURRENT vs INPUT VOLTAGE 0.12 750 ILOAD = 100mA VOUT = 5V, 3.3V 0.1 0.08 650 TA= 125°C TA = 25°C 0.06 600 TA = -40°C 0.04 550 500 0.02 450 -50 0 0 VIN (V) 50 TA (°C) LOAD REGULATION vs AMBIENT AIR TEMPERATURE LINE REGULATION vs AMBIENT AIR TEMPERATURE 10 20 30 12 40 50 10.5 10 9.5 9 1.5 1 0.5 8 -50 0 50 T A (°C) 100 0 -50 150 PSRR AT HEAVY LOAD CURRENT 120 50 T A (°C) 120 100 150 60 40 VIN = 14V IOUT = 1mA TA = 25°C COUT = 10µF VOUT = 5V, 3.3V 100 PSRR (dB) 80 0 PSRR AT LIGHT LOAD CURRENT VIN = 14V IOUT = 250mA TA = 25°C COUT = 10µF VOUT = 5V, 3.3V 100 PSRR (dB) 150 2 8.5 80 60 40 20 0 100 IOUT = 10mA VOUT = 5V, 3.3V VIN step from 8V to 28V 2.5 Line Regulation (mV) 11 0 3 VIN = 14V VOUT = 5V, 3.3V IOUT step from 10mA to 300mA 11.5 Load Regulation (mV) VIN = 14V VOUT = 5V, 3.3V 700 ICL (mA) IOUT (A) OUTPUT CURRENT LIMIT vs AMBIENT AIR TEMPERATURE 20 10 100 10k 1k Frequency (Hz) 100k 1M 0 10 100 10k 1k Frequency (Hz) 100k 1M Note: Graphs shown in 'Typical Characteristics' section for unreleased devices are for preview only. 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 DETAILED DESCRIPTION TPS7A60/1xx is a series of monolithic low dropout linear voltage regulators with integrated reset functionality. These voltage regulators are designed for low power consumption and quiescent current less than 25µA in light load applications. Because of an integrated reset delay (also called Power-On Reset delay), these devices are well suited in power supplies for microprocessors/ microcontrollers. These devices are available in two fixed output voltage (3.3V and 5V) versions as follows: • Programmable reset delay version (TPS7A60xx) • Enable version (TPS7A61xx) nRST is asserted high and CDLY is discharged through an internal load. This allows CDLY to charge from approximately 0V during the next power cycle. If no external capacitor is connected, the delay time is preset internally. This is shown in Figure 6. In TPS7A60xx devices, if CDLY capacitor is not connected to RDELAY pin, reset delay time is set internally. This is shown in Figure 7. VIN(POWERUP) VIN The following section describes the features of TPS7A60/1xx voltage regulators in detail. Reset Delay and Reset Output VOUT Reset delay is implemented when the device starts up to indicate that output voltage is stable and in regulation, and also when the output recovers from a negative voltage spike due to a load step or a dip in the input voltage for a specified duration. Reset delay timer is initialized when the voltage at output (VOUT) exceeds 93% of the regulated output voltage (3.3V or 5V, as applicable). The reset output (nRST) is asserted high after Power-On Reset delay (tPOR) has elapsed. If the regulated output voltage falls below 93% of the set level, nRST is asserted low after a short de-glitch time of approximately 5.5µs (typical). For TPS7A60xx devices, reset delay time can be programmed by connecting an external capacitor (CDLY) to RDELAY pin. The delay time is given by Equation 1: tPOR = VTH(RDELAY) RDELAY Programmable Reset Delay nRST Figure 6. Power Up and Reset Delay Function with CDLY Capacitor connected to RDELAY Pin for TPS7A60xx VIN(POWERUP) CDLY ´ 3 1´ 10 VTH(POR) = 93% of VOUT -6 (1) Where, tPOR = reset delay time in seconds CDLY = reset delay capacitor value in farads, 100 pF to 100 nF VIN VTH(POR) = 93% of VOUT VOUT In TPS7A61xx devices, there is no RDELAY pin and reset delay time is preset internally (250µs typical). VTH(RDELAY) During power up, the regulator incorporates a protection scheme to limit the current through pass element and output capacitor. When the input voltage exceeds a certain threshold (VIN(POWERUP)) level, the output voltage begins to ramp as shown in Figure 6 and Figure 7. When the output voltage reaches power on reset threshold (VTH(POR)) level, a constant output current charges an external capacitor (CDLY) to an internal threshold (VTH(RDELAY)) voltage level. Then, Internal Reset Delay 250µs (typ) nRST Figure 7. Power Up and Reset Delay Function with CDLY Capacitor not connected/available in TPS7A60xx/TPS7A61xx respectively Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 11 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com In case of negative transients in the input voltage (VIN), the reset signal will be asserted low only if the output (VOUT) drops and stays below the reset threshold level (VTH(POR)) for more than deglitch time (tDEGLITCH). This is shown in Figure 8. While nRST is low, if the input voltage resumes to the nominal operating voltage, normal power up sequence will be followed. nRST will be asserted high, only if the output voltage exceeds the reset threshold voltage (VTH(POR)) and the reset delay time (tPOR) has elapsed. This is shown in the shaded region of Figure 8. VIN t < tDEGLITCH t > tDEGLITCH VTH(POR) UVTHRES VOUT VTH(RDELAY) RDELAY tPOR tDEGLITCH tPOR tDEGLITCH nRST Figure 8. Conditions for Activation of Reset Charge Pump Operation ON Hysteresis OFF 7.8 lower input voltages and turns off at higher input voltages. The charge pump switching thresholds are hysteretic. Figure 9 and Figure 10 shows typical switching thresholds for the charge pump at light (IOUT < ~2mA) and heavy (IOUT > ~2mA) loads respectively. Charge Pump State Charge Pump State These devices have an internal charge pump which turns on or off depending on the input voltage and the output current. The charge pump switching circuitry shall not cause conducted emissions to exceed required thresholds on the input voltage line. For a given output current, the charge pump stays on at ON Hysteresis OFF 9.2 7.9 Figure 9. Charge Pump Operation at Light Loads 12 Submit Documentation Feedback 9.6 VIN (V) VIN (V) Figure 10. Charge Pump Operation at Heavy Loads Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 Low Power Mode At light loads and high input voltages (VIN>~8V such that charge pump is off) the device operates in Low Power Mode and the quiescent current consumption is reduced to 25µA (typical) as shown in Table 1. Table 1. Typical Quiescent Current Consumption IOUT Charge Pump ON Charge Pump OFF IOUT < ~2mA (Light load) 250 µA 25 µA (Low Power Mode) IOUT > ~2mA (Heavy load) 280 µA 70 µA Under Voltage Shutdown protects them from excessive power dissipation. For example, during a short circuit condition on the output; current through the pass element is limited to ICL to protect the device from excessive power dissipation. Thermal Shutdown These devices incorporate a thermal shutdown (TSD) circuit as a protection from overheating. For continuous normal operation, the junction temperature should not exceed TSD trip point. If the junction temperature exceeds TSD trip point, the output is turned off. When the junction temperature falls below TSD trip point, the output is turned on again. This is shown in Figure 11. These devices have an integrated under voltage lock out (UVLO) circuit to shutdown the output if the input voltage (VIN) falls below an internally fixed UVLO threshold level (VIN-UVLO). This ensures that the regulator is not latched into an unknown state during low input voltage conditions. The regulator will power up when the input voltage exceeds VIN(POWERUP) level. Low Voltage Tracking At low input voltages the regulator drops out of regulation, the output voltage tracks input minus a voltage based on the load current (IOUT) and switch resistance (RSW). This allows for a smaller input capacitor and can possibly eliminate the need of using a boost convertor during cold crank conditions. Integrated Fault Protection These devices feature an integrated fault protection to make them ideal for use in automotive applications. In order to keep them in safe area of operation during certain fault conditions, internal current limit protection and current limit fold back are used to limit the maximum output current. This Figure 11. Thermal Cycling Waveform for TPS7A6050 (VIN = 24 V, IOUT = 300 mA, VOUT = 5 V) Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 13 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION Typical application circuits for TPS7A60xx and TPS7A61xx are shown in Figure 12 and Figure 13 respectively. Depending upon an end application, different values of external components may be used. A larger output capacitor may be required during fast load steps in order to prevent reset from occurring. A low ESR ceramic capacitor with dielectric of type X5R or X7R is recommended. Additionally, a bypass capacitor can be connected at the output to decouple high frequency noise as per the end application. VIN VOUT VOUT 1µF to 10µF 0.1µF 1kΩ to 5kΩ RDELAY 100pF to 100nF For device under operation at a given ambient air temperature (TA), the junction temperature (TJ) can be calculated using Equation 3. TJ = TA + (θJA × PD) (3) Where, θJA = junction to ambient air thermal impedance ΔT = TJ – TA = (θJA × PD) 10µF to 22µF 0.1µF term The rise in junction temperature due to power dissipation can be calculated using Equation 4. TPS7A60xx VIN As IQUIESCENT << IOUT, therefore, the IQUIESCENT × VIN in Equation 2 can be ignored. (4) For a given maximum junction temperature (TJ-Max), the maximum ambient air temperature (TA-Max) at which the device can operate can be calculated using Equation 5. TA-Max = TJ-Max – (θJA × PD) (5) Example GND nRST RESET Figure 12. Typical Application Schematic for TPS7A60xx If IOUT = 100mA, VOUT = 5V, VIN = 14V, IQUIESCENT = 250µA and θJA= 30˚C/W, the continuous power dissipated in the device is 0.9W. The rise in junction temperature due to power dissipation is 27˚C. For a maximum junction temperature of 150˚C, maximum ambient air temperature at which the device can operate is 123˚C. TPS7A61xx VIN VIN VOUT VOUT 1µF to 10µF 10µF to 22µF 0.1µF VEN 1kΩ to 5kΩ EN GND 0.1µF nRST For adequate heat dissipation, it is recommended to solder the power pad (exposed heat sink) to thermal land pad on the PCB. Doing this provides a heat conduction path from die to the PCB and reduces overall package thermal resistance. Power derating curves for TPS7A60/1xx series of devices in KTT(D2PAK) and KVU(DPAK) packages are shown in Figure 14. RESET 4 3.5 Figure 13. Typical Application Schematic for TPS7A61xx Power dissipated in the device can be calculated using Equation 2. Where, PD = continuous power dissipation IOUT = output current VIN = input voltage VOUT = output voltage IQUIESCENT = quiescent current 14 Submit Documentation Feedback (2) Power Dissipated (W) Power Dissipation and Thermal Considerations PD = IOUT × (VIN - VOUT)) + IQUIESCENT × VIN JESD 51-5 (KTT) 3 JESD 51-5 (KVU) 2.5 JESD 51-3 (KVU) 2 JESD 51-3 (KTT) 1.5 1 0.5 0 0 25 50 75 100 125 150 Ambient Air Temperature (°C) Figure 14. Power Derating Curves Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62G – MARCH 2010 – REVISED MARCH 2012 For optimum thermal performance, it is recommended to use a high K PCB with thermal vias between ground plane and solder pad/ thermal land pad. This is shown in Figure 15 (a) and (b). Further, heat spreading capabilities of a PCB can be considerably improved by using a thicker ground plane and a thermal land pad with a larger surface area. Keeping other factors constant, surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 16 shows variation of θJA with surface area of the thermal land pad (soldered to the exposed pad) for KTT and KVU packages. 55 50 q JA (°C/W) Exposed Tab Thermal Via Thermal Land Pad 45 KVU (DPAK) (JESD 51-3) 40 PCB KTT (D2PAK) (JESD 51-3) Ground Plane (a) Before soldering 35 30 0 200 400 600 800 1000 Thermal Pad Area (sq. mm) Figure 16. θJA vs Thermal Pad Area (b) After soldering Figure 15. Using Multilayer PCB and Thermal Vias For Adequate Heat Dissipation Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 Submit Documentation Feedback 15 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 SLVSA62G – MARCH 2010 – REVISED MARCH 2012 www.ti.com REVISION HISTORY Changes from Revision F (01-DEC-2011) to Revision G • 16 Page Added the following text to regulated output voltage section 6.1: to 300mA, VIN= VOUT + 1V to 16V .................................. 4 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TPS7A6033-Q1 TPS7A6050-Q1 PACKAGE OPTION ADDENDUM www.ti.com 20-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS7A6033QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TPS7A6033QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TPS7A6050QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TPS7A6050QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TPS7A6133QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TPS7A6150QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Apr-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ DDPAK/ TO-263 KTT 5 500 330.0 24.4 TPS7A6033QKVURQ1 PFM KVU 5 2500 330.0 TPS7A6050QKTTRQ1 DDPAK/ TO-263 KTT 5 500 330.0 TPS7A6050QKVURQ1 PFM KVU 5 2500 TPS7A6133QKVURQ1 PFM KVU 5 2500 TPS7A6150QKVURQ1 PFM KVU 5 2500 TPS7A6033QKTTRQ1 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.6 15.8 4.9 16.0 24.0 Q2 16.4 6.9 10.5 2.7 8.0 16.0 Q2 24.4 10.6 15.8 4.9 16.0 24.0 Q2 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A6033QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0 TPS7A6033QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 TPS7A6050QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0 TPS7A6050QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 TPS7A6133QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 TPS7A6150QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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