NEC UPC8101GR

PRELIMINARY DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC8126K
900 MHz BAND DIRECT QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The µPC8126K is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This IC integrates a pre-mixer for local signals plus a quadrature modulator operating from
889 MHz to 960 MHz. The chip which has been conventionally packaged in 20-pin SSOP is packaged in 28-pin QFN
and therefore is suitable for higher density mounting. In addition, the IC has power save function and can operate
2.7 to 3.6 V supply voltage. Consequently the µPC8126K can contribute to make RF blocks smaller size, higher
performance and lower power consumption.
FEATURES
• Directly modulate in 889 MHz to 960 MHz
• Built-in pre-mixer for local signals
• External IF filter can be applied between modulator output and pre-mixer input terminal.
• Current consumption ICC = 35 mA TYP. @ VCC = 3.0 V
• Equipped with power save function.
• 28-pin QFN suitable for higher density mounting.
APPLICATIONS
• Digital cellular phones: PDC800M
ORDERING INFORMATION
Part Number
µPC8126K-E1
Package
28-pin plastic QFN (5.1 × 5.5 × 0.95 mm)
Supplying Form
Embossed tape 12 mm wide.
QTY 2.5 kp/reel.
Pins 1 through 10 are in pull-out direction.
Remark To order evaluation samples, please contact your local NEC sales office .
(Part number for sample order: µPC8126K)
Caution Electro-static sensitive device
The information in this document is subject to change without notice.
Document No. P13488EJ1V0DS00 (1st edition)
Date Published February 1999 N CP(K)
Printed in Japan
©
1999
µPC8126K
N. C.
23
GND
24
N. C.
IF-LOin
VPS2
GND
N.C.
MODout
VCC3
N. C.
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
22
21
20
19
18
17
16
15
14
GND
13
Q
12
Qb
11
Ib
10
I
9
GND
LO Pre-Mix
RF-LOin
25
÷2
N. C.
1
2
2
3
4
5
6
7
8
N. C.
LO
Buffer
VPS1
28
Phase
Shifter
VCC2
GND
LO×2
N. C.
27
LOin
MIXout
N. C.
26
LOinb
VCC1
I/Q-Mix
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
QUADRATURE MODULATOR SERIES PRODUCT
Part Number
Functions
ICC
(mA)
fLO1in
(MHz)
fMODout Up-Converter
(MHz) fRFout (MHz)
µPC8101GR
150 MHz Quad.Mod
15/@2.7 V 100 to 300 50 to 150
µPC8104GR
RF Up-Converter + IF
Quad.Mod
28/@3.0 V
100 to 400
µPC8105GR
400 MHz Quad.Mod
16/@3.0 V
100 to 400
External
µPC8110GR
1 GHz Direct Quad.Mod
24/@3.0 V
800 to 1 000
Direct
µPC8125GR
RF Up-Converter + IF
Quad.Mod + AGC
36/@3.0 V
220 to 270
1 800 to 2 000
µPC8126GR
900 MHz Direct Quad.Mod 35/@3.0 V
with Offset-Mixer
915 to 960
915 to 960
(LO pre-mixer)
889 to 960
889 to 960
µPC8126K
µPC8129GR
×2LO IF Quad. Mod+RF
Up-Converter
Phase
Shifter
Package
Application
20-pin
CT-2 etc.
SSOP (225 mil)
900 to 1 900 Doubler
Digital Comm.
+ F/F
External
F/F
16-pin
SSOP (225 mil)
20-pin
PDC800 MHz, etc.
SSOP (225 mil)
PHS
PDC800 MHz
28-pin QFN
28/@3.0 V 200 to 800 100 to 400 800 to 1 900
F/F
20-pin
GSM,
SSOP (225 mil) DCS1800, etc.
µPC8139GR-7JH Transceiver IC
(1.9 GHz Indirect Quad.
Mod + RX-IF + IF VCO)
TX: 32.5
RX: 4.8
/@3.0 V
220 to 270
1 800 to 2 000
CR
30-pin
PHS
TSSOP (225 mil)
µPC8158K
28/@3.0 V
100 to 300
800 to 1 500
RF Up-Converter + IF
Quad.Mod + AGC
28-pin QFN
PDC800 M/1.5 G
Remark For outline of the quadrature modulator series, please refer to the application note Usage of µPC8101,
8104, 8105, 8125, 8129 (Document No. P13251E) and so on.
Preliminary Data Sheet P13488EJ1V0DS00
3
µPC8126K
APPLICATION EXAMPLE
[PDC800 MHz]
SUB ANT
LNA
1st MIX
2nd MIX
SW
TO DEMOD
RSSI
MAIN ANT
RSSI OUT
1st LO
SW
2nd LO
PLL1 PLL2
SW
I
0°
φ
(÷2)
PA
AGC
×2
Filter
90°
Q
µ PC8126 K
This block diagram presents the IC’s location example applied in the system. The system block construction
herein is an example.
4
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Test Conditions
Rating
Unit
Supply Voltage
VCC
TA = +25 °C
4.0
V
Power Save Control Voltage
VPS
TA = +25 °C
4.0
V
Power Dissipation
PD
TA = +85 °C
430
mW
Operating Ambient Temperature
TA
–40 to +85
°C
Storage Temperature
Tstg
–55 to +150
°C
Note
Note Mounted on a 50 × 50 × 1.6 mm double sided copper clad epoxy glass PWB.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Supply Voltage
VCC
2.7
3.0
3.6
V
Operating Ambient Temperature
TA
–25
+25
+75
°C
Pre-Mix. RF Input Frequency
fRFin
689
–
1 200
MHz
Pre-Mix. RF Input Power
PRFin
–13
–11
–9
dBm
120
135
270
MHz
–14
–12
–10
dBm
fIFin = 200 MHz
889
–
898
MHz
fIFin = 135 MHz
915
–
960
MHz
Pre-Mix. IF Input Frequency
fIFin
Pre-Mix. IF Input Power
PIFin
Pre-Mix. Output Frequency
(Modulator Output Frequency,
Modulator LO Input Frequency)
fMIXout
(fMODout, fLOin)
P (fIF × 7) ≤ –65 dBc
Modulator LO Input Power
PLOin
–21.5
–18.5
–15.5
dBm
I/Q Input Frequency
fI/Qin
DC
–
10
MHz
I/Q Input Amplitude
VI/Qin
Single ended Input
–
–
500
mVP-P
Differential Input
–
–
250
Preliminary Data Sheet P13488EJ1V0DS00
5
µPC8126K
ELECTRICAL CHARACTERISTICS
(TA = +25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS1, VPS2 ≥ 2.2 V unless otherwise specified)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
No Input Signals
24
35
44
mA
VPS ≤ 0.5 V (Low),
No Input Signals
–
0
15
µA
fIFin = 135 MHz, PIFin = –12 dBm
fRFin = 813 MHz, PRFin = –11 dBm
fMODout = 948 MHz + fI/Q
fI/Qin = 2.625 kHz
VI/Qin = 500 mVP-P (Single ended)
I/Q (DC) = Ib/Qb (DC) = VCC/2
Data Rate: 42 kbps,
RNYQ: α = 0.5
MOD Pattern: All Zero
–12
–9
–6
dBm
–
–35
–30
dBc
–
–40
–30
dBc
–
–45
–30
dBc
–
–
–65
dBc
MODULATOR + PRE-MIXER TOTAL (TEST CIRCUIT 1 unless otherwise specified)
Total Circuit Current
ICC (TOTAL)
Total Circuit Current at Sleep Mode
ICC (PS) TOTAL
Modulator Output Power
PMODout
Local Oscillator Leakage
LOL
Note
ImR
Image Rejection
I/Q 3rd Order Intermodulation
P (fIF × 7)
fIF-LO × 7 Harmonics
Power Save
Response Time
IM3 (I/Q)
Rise Time
TPS (RISE)
VPS: Low to High, TEST CIRCUIT 2
–
3
5
µs
Fall Time
TPS (FALL)
VPS: High to Low, TEST CIRCUIT 2
–
3
5
µs
EVM
fIFin = 135 MHz, PIFin = –12 dBm
fRFin = 813 MHz, PRFin = –11 dBm
fMODout = 948 MHz + fI/Q
fI/Qin = 2.625 kHz
VI/Qin = 500 mVP-P (Single ended)
I/Q (DC) = Ib/Qb (DC) = VCC/2
Data Rate: 42 kbps,
RNYQ: α = 0.5
MOD Pattern: PN9 (Pseudorandom pattern)
–
1.6
3.5
%rms
–
–65
–60
dBc
Error Vector Magnitude
Adjacent Channel Power
ACP
(∆f = ±50 kHz)
Port Current-7 pin
IPS (7 pin)
No Input Signals
–
–
620
µA
Port Current-17 pin
IPS (17 pin)
No Input Signals
–
–
400
µA
Note fLOL = fIFin + fRFin
6
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
STANDARD CHARACTERISTICS FOR REFERENCE
(TA = +25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS1, VPS2 ≥ 2.2 V unless otherwise specified)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
No Input Signals
–
27.5
34
mA
ICC (PS) (MOD)
VPS ≤ 0.5 V (Low),
No Input Signals
–
0
10
µA
Input Impedance I and Q Port
ZI/Qin
fI/Q = DC to 10 MHz
90
180
–
kΩ
Modulator Output Port VSWR
VSWR (MOD)
fMODout = 948 MHz
–
1.5:1
–
–
ICC (MIX)
No Input Signals
–
7.5
10
mA
VPS ≤ 0.5 V (Low),
No Input Signals
–
0
5
µA
fRFin = 813 MHz, PRFin = –11 dBm
fIFin = 135 MHz, PIFin = –12 dBm
fMIXout = 948 MHz
–5
–3
–1
dB
–17
–15
–13
dBm
MODULATOR (TEST CIRCUIT 3)
Modulator Circuit Current
Modulator Circuit Current at Sleep
Mode
ICC (MOD)
PRE-MIXER (TEST CIRCUIT 4)
Pre-Mixer Circuit Current
Pre-Mixer Circuit Current at Sleep
Mode
ICC (PS) (MIX)
Pre-Mixer Conversion Gain
CG (MIX)
Pre-Mixer Output Power
Pout (MIX)
Preliminary Data Sheet P13488EJ1V0DS00
7
µPC8126K
PIN EXPLANATIONS
Pin
No.
Symbol
Supply
Voltage
(V)
Pin
Voltage (V)
@3 V
2
LOinb
–
2.6
Bypass of LO input for modulator.
This pin should be externally
grounded through around 33 pF
capacitor.
4
LOin
–
2.6
LO input for the phase shifter.
Connect around 300 Ω between pin
4 and 5 to match to 50 Ω by LC.
6
VCC2
2.7 to 3.6
–
7
VPS1
(Modulator)
VPS
–
Description
0 to 0.5
0
–
7
State
ON (Active Mode)
OFF (Sleep Mode)
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
10
I
VCC/2
–
Input for I signal.
This input impedance is 180 kΩ.
In case of that I/Q input signals are
single ended, amplitude of the signal
is 500 mVP-P max.
Note
11
Ib
VCC/2
–
Input for I signal.
This input impedance is 180 kΩ.
In case of that I/Q input signals are
single ended, VCC/2 biased DC
signal should be input.
In case of that I/Q input signals are
differential, amplitude of the signal is
250 m VP-P max.
Note
–––––––––––––
10
Note Relations between amplitude and VCC/2 bias of input signal are following.
8
2
–––––––––––––
Power save control pin for the
modulator can control On/Sleep
state with bias as follows.
2.2 to 3.6
GND
(Modulator)
4
Supply voltage pin for the phase
shifter and IQ Mixer. An internal
regulator helps keep the device
stable against temperature or VCC
variation.
VPS (V)
9
Equivalent Circuit
Preliminary Data Sheet P13488EJ1V0DS00
11
µPC8126K
Pin
No.
Symbol
Supply
Voltage
(V)
Pin
Voltage (V)
@3 V
12
Qb
VCC/2
–
Description
Input for Q signal.
This input impedance is 180 kΩ.
In case of that I/Q input signals are
single ended, VCC/2 biased DC
signal should be input.
In case of that I/Q input signals are
differential, amplitude of the signal is
250 mVP-P max.
Note
Equivalent Circuit
12
13
13
Q
VCC/2
–
Input for Q signal.
This input impedance is 180 kΩ.
In case of that I/Q input signals are
single ended, amplitude of the signal
is 500 mVP-P max.
Note
14
GND
(Modulator)
0
–
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
–––––––––––––
Supply voltage pin for the output
buffer amplifier of modulator.
An internal regulator helps keep the
device stable against temperature or
VCC variation.
–––––––––––––
16
17
VCC3
MODout
2.7 to 3.6
–
–
1.6
Output pin from the modulator.
This is emitter follower output.
So this output impedance is low.
17
19
20
GND
(Modulator)
VPS2
(Pre-Mix)
0
VPS
–
–
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
Power save control pin can control
the On/Sleep state with bias as
follows.
VPS (V)
–––––––––––––
20
State
2.2 to 3.6
ON (Active Mode)
0 to 0.5
OFF (Sleep Mode)
Note Relations between amplitude and VCC/2 bias of input signal are following.
Preliminary Data Sheet P13488EJ1V0DS00
9
µPC8126K
Pin
No.
Symbol
Supply
Voltage
(V)
Pin
Voltage (V)
@3 V
21
IF-LOin
–
1.3
Description
Equivalent Circuit
IF input pin for the Pre-Mixer.
This pin is biased internally.
Capacitor should be connected in
series, and grounded through 51 Ω.
21
24
25
26
27
28
1, 3,
5, 8,
15,
18,
22, 23
10
GND
(Pre-Mix)
RF-LOin
0
–
VCC1
(Pre-Mix)
2.7 to 3.6
Pre-Mixout
2.7 to 3.6
GND
(Modulator)
N.C.
0
–
–
2.3
–
–
–
–
Ground pin for Pre-Mixer.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
RF input pin for the Pre-Mixer.
This pin is biased internally.
Capacitor should be connected in
series, and grounded through 51 Ω.
Supply voltage pin for the Pre-Mixer.
An internal regulator helps keep the
device stable against temperature or
VCC variation.
–––––––––––––
25
–––––––––––––
Output from the Pre-Mixer. This pin
is designed as open collector. Due
to the high impedance output, this
pin should be externally equipped
with LC matching circuit to next
stage.
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
27
–––––––––––––
Non connection pins.
–––––––––––––
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
RELATION BETWEEN I/Q PIN INPUT DC VOLTAGE AND AMPLITUDE
I/Q input signal (mVP-P)
Supply Voltage (V)
VCC
I/Q DC Voltage (V)
VCC/2 = I = Ib = Q = Qb
2.7 to 3.6
1.35 to 1.8
Single ended input
I=Q
Differential input
I = Ib = Q = Qb
≤ 500
≤ 250
EXPLANATION OF INTERNAL FUNCTION
Block
90° PHASE
SHIFTER
Function/Operation
Input signal from LO is send to digital circuit of
T-type flip-flop through frequency doubler.
Output signal from T-type F/F is changed to
same frequency as LO input and that have
quadrature phase shift, 0°, 90 °, 180°, 270°.
These circuits have function of self phase
correction to make correctly quadrature
signals.
BUFFER AMP.
Buffer amplifiers for each phase signals to
send to each mixers.
MIXER
Each signals from buffer amp. are quadrature
modulated with two double-balanced mixers.
High accurate phase and amplitude inputs are
realized to good performance for image
rejection.
ADDER
Block Diagram
from LOin
×2
÷2F/F
I
Ib
Qb
Q
Output signals from each mixers are added
with adder and send to final amplifier.
to MODout
Preliminary Data Sheet P13488EJ1V0DS00
11
µPC8126K
TEST CIRCUIT 1
Pre-mixer + Quadrature modulator (except Power save response time)
Spectrum Analyzer
Signal Generator
Voltage
Source
Signal Generator
VCC3 (MOD)
VPS2 (Pre Mix)
BPF
100 pF
MODout
Voltage
Source
IFin
1 000 pF
33 pF
RFin
0.22 µF
51 Ω
1 000 pF
VCC1 (Pre Mix)
100 pF
22 21 20 19 18 17 16 15
51 Ω
23
14
24
13
1 000 pF
33 pF
25
0.22É F
Mixout
7 pF
1 pF 18 nH
I/Q Mixer
15 nH
27
2.5 pF
2
7 pF
3
4
6.8 nH
Iin
9
I/Q Singnal
Generator
8
VPS1 (MOD)
1 000 pF
33 pF
2 pF
10 nH
Voltage
Source
0.22 µF
Filter
12
7
300 Ω
33 pF
6.8 nH
5
6
100 pF
Ib
10
I/Q Mixer
28
Qb
12
11
Frequency
Doubler
1
5.6 nH
TFF
PreMixer
26
Qin
18 nH
VCC2 (MOD)
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
TEST CIRCUIT 2
Pre-mixer + Quadrature modulator (for Power save response time)
Spectrum Analyzer
Voltage
Source
Signal Generator
Signal Generator
VCC3 (MOD)
VPS2 (Pre Mix)
BPF
100 pF
MODout
Voltage
Source
IFin
1 000 pF
33 pF
51 Ω
RFin
VCC1 (Pre Mix)
0.22 µ F
1 000 pF
100 pF
I/Q Singnal
Generator
22 21 20 19 18 17 16 15
51 Ω
23
14
24
13
1 000 pF
33 pF
0.22 µ F
25
Mixout
7 pF
1 pF 18 nH
I/Q Mixer
26
27
2.5 pF
2
7 pF
3
4
5
6
100 pF
300 Ω
33 pF
6.8 nH
1 000 pF
Ib
Iin
10
I/Q Mixer
28
Qb
12
11
Frequency
Doubler
1
5.6 nH
TFF
PreMixer
15 nH
Qin
7
9
Palse Pattern
Generator
8
VPS1 (MOD)
33 pF
Voltage
Source
0.22 µF
6.8 nH
Filter
2 pF
10 nH
18 nH
VCC2 (MOD)
Preliminary Data Sheet P13488EJ1V0DS00
13
µPC8126K
TEST CIRCUIT 3
Quadrature modulator block
Spectrum Analyzer
or Network Analyzer
Voltage
Source
VCC3 (MOD)
100 pF
MODout
1 000 pF
33 pF
22
21
20
19
18
0.22 µF
17
16
15
23
14
24
13
25
12
26
11
27
10
28
9
1
2
3
300 Ω
33 pF
33 pF
4
5
6
100 pF
7
1 000 pF
8
Qin
Qb
Ib
Iin
Voltage Source
Pulse Pattern Generator
VPS1 (MOD)
6.8 nH
Voltage
Source
0.22 µ F
LOinb
2 pF
VCC2 (MOD)
Signal Generator
LOin
In this case, pin 20 to 27 should be opened or grounded.
14
Preliminary Data Sheet P13488EJ1V0DS00
I/Q Signal
Generator
µPC8126K
TEST CIRCUIT 4
Pre-mixer block
Signal Generator
Signal Generator
Voltage
Source
BPF
Voltage
Source
IFin
51 Ω
VCC1 (Pre Mix)
RFin
100 pF
0.22 µF
Mixout
VCC3 (MOD)
1 000 pF
VPS2 (Pre Mix)
22
1 000 pF
MODout
51 Ω
21
20
19
18
17
16
15
23
14
24
13
25
12
26
11
27
10
28
9
33 pF
1 pF 18 nH
15 nH
Spectrum Analyzer
1
2
LOinb
3
4
5
6
7
Qin
Qb
Ib
Iin
8
VPS1 (MOD)
LOin VCC2 (MOD)
Preliminary Data Sheet P13488EJ1V0DS00
15
µPC8126K
PACKAGE DIMENSIONS
0.22
0.5
0.125
0.95 ± 0.1
28 pin
1 pin
0.22
(4.7)
(5.1 ± 0.1)
5.1 ± 0.1
2 × 0.5 = 1
1.2
2 × 0.5 = 1
4 – 0.5
0.5
4 – 0.5
28 pin plastic QFN (UNIT: mm)
0.5
7 × 0.5 = 3.5
(5.1)
0.5
(4.1)
(5.5 ± 0.1)
(0.22)
0.3
0.5
5.5 ± 0.1
(0.22)
0.5
(4.5)
Bottom View
16
Preliminary Data Sheet P13488EJ1V0DS00
0.5
µPC8126K
NOTE ON CORRECT USE
(1) Observe precautions for handling because of electrostatic sensitive devices.
(2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired operation).
(3) Keep the track length between the ground pins as short as possible.
(4) Connect a bypass capacitor (example 1 000 pF) to the VCC pin.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered under the following recommended condition.
For soldering methods and
conditions other than those recommended below, contact your NEC sales representative.
Soldering Method
Soldering Conditions
Recommended Condition
Symbol
Infrared Reflow
Package peak temperature: 235°C or below
Time: 30 seconds or less (at 210°C)
Note
Count: 2, Exposure limit : None
IR35-00-2
Partial Heating
Pin temperature: 300°C
Time: 3 seconds or less (per side of device)
Note
Exposure limit : None
–
Note After opening the dry pack, keep it in a place below 25°C and 65% RH for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
For details of recommended soldering conditions for surface mounting, refer to information document
SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
Preliminary Data Sheet P13488EJ1V0DS00
17
µPC8126K
[MEMO]
18
Preliminary Data Sheet P13488EJ1V0DS00
µPC8126K
[MEMO]
Preliminary Data Sheet P13488EJ1V0DS00
19
µPC8126K
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5