NEC UPD75108FGF

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75108F,75112F,75116F
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75116F offers high-speed operation (tCY = 1.91 µ s) at a low supply voltage (VDD = 2.7 V) which is not possible
with the µPD75116.
It has the same functions as, and is pin compatible with, the µPD75116, allowing low voltage sets to be developed
by making efficient use of previously developed and used software resources. Note, however, that the operating
voltage range is different from that of the µPD75116.
A version of the µPD75116F with on-chip PROM, the µPD75P116*, is also available for evaluation during system
development.
* There are some differences in electrical specifications between the µPD75116F and the µPD75P116.
Functions are described in detail in the following User’s Manual, which should be read when carrying out design
work.
µPD75116 User’s Manual : IEM-922
FEATURES
• µPD75116 low voltage high-speed operation product
• Instruction execution time
Ta = –40 to +50 °C
VDD = 2.7 to 5.0 V
1.91 µs , 15.3 µs (operation at 4.19 MHz)
2 µs, 4 µs, 32 µs (operation at 2 MHz)
1.91 µs , 15.3 µs (operation at 4.19 MHz)
VDD = 2.8 to 5.0 V
VDD = 4.5 to 5.0 V
Ta = –40 to +60 °C
2 µs, 4 µs, 32 µs (operation at 2 MHz)
0.95 µs, 1.91 µs, 15.3 µs (operation at 4.19 MHz)
• 43 systematically arranged instructions
• 8-bit data transfer, compare, operation and increment/decrement instructions
• GETI instruction allowing any 2-byte or 3-byte instruction to be implemented in 1 byte
• Wide range of input/output ports : 58 ports
• 3 on-chip 8-bit timer channels : synchronous/asynchronous (start/stop)
• 8-bit serial interface on chip
• Programmable threshold port : 4-bit resolution × 4 channels
"Unless there are any particular functional differences, the µPD75116F is described in this document as a representative
product."
The information in this document is subject to change without notice.
Document No. IC-2810B
(O.D.No. IC-8224B)
Date Published April 1994P
Printed in Japan
The mark ★ shows major revised points.
© NEC Corporation 1991
µPD75108F,75112F,75116F
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
µPD75108FGF-×××-3BE
µPD75112FGF-×××-3BE
µPD75116FGF-×××-3BE
64-pin plastic QFP (14 × 12 mm)
64-pin plastic QFP (14 × 12 mm)
64-pin plastic QFP (14 × 20 mm)
Standard
Standard
Standard
Remarks
×××: ROM code number
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
APPLICATIONS
Cordless telephone subsets, portable radio equipment, pager, etc.
2
µPD75108F,75112F,75116F
OVERVIEW OF FUNCTIONS
Item
Contents
Basic instructions
43
Instruction cycle
0.95 µs, 1.91 µs, 15.3 µs (VDD = 4.5 to 5.0 V, 4.19 MHz operation)
2 µs, 4 µs, 32 µs (VDD = 2.7 to 5.0 V, 2 MHz operation)
3-stage switching capability
Minimum instruction
execution time
0.95 µs (operating at 4.5 to 5.0 V)
1.91 µs (operating at 2.7 V )
8064 × 8 bits (µPD75108F)
On-chip memory
ROM
12160 × 8 bits (µPD75112F)
16256 × 8 bits (µPD75116F)
RAM
512 × 4 bits
General register
4-bits × 8 × 4 banks (memory mapping)
Accumulator
3 accumulators for different manipulated data lengths
• 1-bit accumulator (CY), 4–bit acculumalor (A), 8-bit accumulator (XA)
Input/output port
Total 58
• CMOS input pins
: 10
• CMOS input/output pins (LED direct drive capability)
: 32
• Middle-high voltage N-ch open-drain input/output pins : 12
(LED direct drive capability, a pull-up resistor can be incorporated bit-wise.)
• Comparator input pins (4-bit precision)
: 4
Timer/counter
• 8-bit timer/event counter × 2
• 8-bit basic interval timer (watchdog timer applicable)
8-bit serial interface
• 2 transfer modes
• Serial transmission/reception modes
• Serial reception mode
• LSB top/MSB top switchable
Vector interrupt
External : 3 Internal : 4
Test input
External : 2
Standby
• STOP/HALT mode
Instruction set
•
•
•
•
Others
• Bit manipulation memory (bit sequential buffer) on chip
Package
• 64-pin plastic QFP (14 × 20 mm)
Various bit manipulation instructions (set, reset, test, Boolean operation)
8-bit data transfer, comparison, operation, increment/decrement instructions
1-byte relative branch instruction
GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte
3
µPD75108F,75112F,75116F
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) .....................................................................................................
6
2.
BLOCK DIAGRAM ..................................................................................................................................
7
3.
PIN FUNCTIONS ....................................................................................................................................
8
3.1
3.2
3.3
3.4
PORT PINS .....................................................................................................................................................
OTHER PINS ...................................................................................................................................................
PIN INPUT/OUTPUT CIRCUITS ...................................................................................................................
RECOMMENDED CONNECTION OF UNUSED PINS .................................................................................
8
9
10
11
3.5
PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ...............................................................
12
4.
MEMORY CONFIGURATION ................................................................................................................ 13
5.
PERIPHERAL HARDWARE FUNCTIONS .............................................................................................. 18
5.1
DIGITAL INPUT/OUTPUT PORTS ................................................................................................................
18
5.2
5.3
5.4
5.5
CLOCK GENERATOR .....................................................................................................................................
CLOCK OUTPUT CIRCUIT .............................................................................................................................
BASIC INTERVAL TIMER ..............................................................................................................................
TIMER/EVENT COUNTER .............................................................................................................................
19
20
21
21
5.6
5.7
5.8
SERIAL INTERFACE .......................................................................................................................................
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ............................................................
BIT SEQUENTIAL BUFFER ...........................................................................................................................
23
25
26
6.
INTERRUPT FUNCTION ........................................................................................................................ 27
7.
STANDBY FUNCTION ........................................................................................................................... 29
8.
RESET FUNCTION ................................................................................................................................. 30
9.
INSTRUCTION SET ................................................................................................................................ 32
10. APPLICATION EXAMPLE ...................................................................................................................... 41
10.1 CORDLESS TELEPHONE (SUBSET) ............................................................................................................
10.2 DISPLAY PAGER ............................................................................................................................................
41
42
11. MASK OPTION SELECTION .................................................................................................................. 43
12. ELECTRICAL SPECIFICATIONS ............................................................................................................ 44
12.1 WHEN Ta = –40 to +50 °C, VDD = 2.7 to 5.0 V ...........................................................................................
12.2 WHEN Ta = –40 to +60 °C, VDD = 2.8 to 5.0 V ...........................................................................................
4
45
55
µPD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE) ......................................................................................... 65
14.
PACKAGE INFORMATION .....................................................................................................................................
71
15. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 73
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD751×× SERIES PRODUCTS ....................... 74
APPENDIX B. DEVELOPMENT TOOLS ...................................................................................................... 76
APPENDIX C. RELATED DOCUMENTS ..................................................................................................... 77
5
µPD75108,75112F,75116F
1. PIN CONFIGURATION (TOP VIEW)
P130
P143
P142
P141
NC
P140
VDD
P33
P32
P31
P30
P43
P42
64-Pin Plastic QFP (14 × 20 mm)
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
P131
P40
2
50
P132
P53
3
49
P133
P52
4
48
P120
P51
5
47
P50
6
46
P121
P122
RESET
7
45
P123
X2
8
X1
P63
9
P62
11
P61
12
P60
13
P73
14
P72
15
P71
P70
µPD75116FGF-×××-3BE
µPD75112FGF-×××-3BE
µPD75116FGF-×××-3BE
P41
10
44
P00/INT4
43
P01/SCK
42
P02/SO
41
P03/SI
40
P20/PTO0
39
P21/PTO1
38
P22/PCL
37
P23
16
36
T11
17
35
T10
P83
18
34
P82
19
33
PTH00
PTH01
PTH02
PTH03
P10/INT0
P11/INT1
P12/INT2
P13/INT3
VSS
P90
P91
P92
P93
P81
P80
20 21 22 23 24 25 26 27 28 29 30 31 32
★ Pin Name
P00-P03
: Port 0
SCK
: Serial Clock
P10-P13
P20-P23
: Port 1
: Port 2
SO
SI
: Serial Output
: Serial Input
P30-P33
: Port 3
PTO0, PTO1
: Programmable Timer Output
P40-P43
P50-P53
: Port 4
: Port 5
PCL
PTH00-PTH03
: Programmable Clock
: Programmable Treshold Input
P60-P63
: Port 6
INT0, INT1, INT4 : External Vectored Interrupt Input
P70-P73
P80-P83
: Port 7
: Port 8
INT2, INT3
TI0, TI1
P90-P93
: Port 9
P120-P123 : Port 12
P130-P133 : Port 13
P140-P143 : Port 14
6
: External Test Input
: Timer Input
X1, X2
: Clock Oscillation
RESET
NC
: Reset
: No Connection
VDD
: Positive Power Supply
VSS
: Ground
2.
INTBT
BIT SEQ.
BUFFER
(16)
SP(8)
PROGRAM*
COUNTER
ALU
TIMER/EVENT
COUNTER
#0
TI0
PTO0/P20
TIMER/EVENT
COUNTER
#1
INTT1
SI/P03
SO/P02
SCK/P01
4
P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
PORT 4
4
P40-P43
PORT 5
4
P50-P53
PORT 6
4
P60-P63
PORT 7
4
P70-P73
PORT 8
4
P80-P83
PORT 9
4
P90-P93
PORT 12
4
P120-P123
PORT 13
4
P130-P133
PORT 14
4
P140-P143
BANK
INTT0
TI1
PTO1/P21
PORT 0
CY
BLOCK DIAGRAM
BASIC
INTERVAL
TIMER
ROM
PROGRAM
GENERAL REG.
MEMORY
8064 × 8 BITS
(µPD75108F)
SERIAL
INTERFACE
12160 × 8 BITS
INTSIO
(µPD75112F)
16256 × 8 BITS
DECODE
AND
CONTROL
RAM
DATA
MEMORY
512 × 4 BITS
(µPD75116F)
INT0/P10
INTERRUPT
CONTROL
fXX / 2
PTH00-PTH03
4
PROGRAMMABLE
THRESHOLD
PORT #0
CLOCK
OUTPUT
CONTROL
PCL/P22
CLOCK
DIVIDER
N
CLOCK
GENERATOR
X1
STAND BY
CONTROL
CPU CLOCK Φ
X2
VDD
*
VSS RESET
The µPD75108F program counter is composed of 13 bits and the µPD75112F/75116F program counter is composed of 14 bits
7
µPD75108F,75112F,75116F
INT1/P11
INT2/P12
INT3/P13
INT4/P00
µPD75108F,75112F,75116F
3. PIN FUNCTIONS
3.1
PORT PINS
Pin Name
P00
P01
Input/Output
Input
Input/output
DualFunction Pin
Function
8-bit I/O
INT4
P03
Input/output
Input
SCK
F
Input
SO
E
SI
B
×
INT0
P10
INT1
P11
Input
P12
INT2
P13
INT3
P20 *3
PTO0
4-bit input port (PORT 1).
Input
B
4-bit input/output port (PORT 2).
Input
E
PTO1
P21 *3
Input/output
P22 *3
PCL
P23 *3
—
×
P30 to P33 *3
Input/output
—
Programmable 4-bit input/output port (PORT 3).
Input/output can be specified bit-wise.
Input
E
P40 to P43 *3
Input/output
—
4-bit input/output port (PORT 4).
Input
E
P50 to P53 *3
Input/output
—
4-bit input/output port (PORT 5).
Input
E
P60 to P63 *3
Input/output
—
Programmable 4-bit input/output port (PORT 6).
Input/output can be specified bit-wise.
Input
E
P70 to P73 *3
Input/output
—
4-bit input/output port (PORT 7).
Input
E
P80 to P83 *3
Input/output
—
4-bit input/output port (PORT 8).
Input
E
P90 to P93 *3
Input/output
—
4-bit input/output port (PORT 9).
Input
E
—
N-ch open-drain 4-bit input/output port (PORT
12).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
Input *2
M
—
N-ch open-drain 4-bit input/output port (PORT
13).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
Input *2
M
—
N-ch open-drain 4-bit input/output port (PORT
14).
On-chip pull-up resistor can be specified bit-wise
(mask option).
Open-drain: +10 V withstand voltage
Input *2
M
P120 to P123 *3
P130 to P133 *3
P140 to P143 *3
* 1.
2.
3.
8
I/OCircuit
Type *1
B
4-bit input port (PORT 0).
P02
After Reset
Input/output
Input/output
Input/output
● : Schmitt trigger input
Open-drain … high impedance
On-chip pull-up resistor … high level
Direct LED drive capability
—
µPD75108F,75112F,75116F
3.2
OTHER PINS
Pin Name
Input/Output
DualFunction Pin
PTH00 to PTH03
Input
—
Variable threshold voltage 4-bit analog input port.
N
Input
—
External event pulse input to timer/event counter. Or edge
detection vectored interrupt input or 1-bit input is also
possible.
B
TI0
TI1
After Reset
I/O Circuit
Type *1
P20
PTO0
Input/output
Timer/event counter output
Input
E
P21
PTO1
SCK
Input/output
P01
Serial clock input/output
Input
F
SO
Input/output
P02
Serial data output
Input
E
SI
Input
P03
Serial data input
Input
B
INT4
Input
P00
Edge detection vector interrupt input (detection of both
rising and falling edges)
Input
B
Edge detection vector interrupt input (detection edge selectable)
Input
B
Edge detection testable input (rising edge detection)
Input
B
Clock output
Input
E
P10
INT0
Input
P11
INT1
P12
INT2
Input
P13
INT3
PCL
Input/output
X1, X2
* 1.
2.
Function
P22
—
System clock oscillation crystal/ceramic connection pin.
When an external clock is used, the clock is input to X1 and
the inverted clock is input to X2.
RESET
Input
—
System reset input (low-level active).
NC*2
—
—
No Connection
VDD
—
Positive power supply
VSS
—
GND potential
B
● : Schmitt trigger input
When sharing a print board with µPD75P116, NC pin should be connected to VDD.
9
µPD75108F,75112F,75116F
3.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the µPD75116F are shown in abbreviated form.
Fig. 3-1 Pin Input/Output Circuit List
Type F
Type A
VDD
data
IN/OUT
Type D
P-ch
output
disable
IN
Type B
N-ch
This is an input/output circuit made up of a Type D
push-pull output and Type B Schmitt-triggered input.
CMOS standard input buffer
Type B
VDD
Type M
Pull-Up Resistor
(Mask Option)
N-ch
(+6 V
Withstand
Voltage)
data
IN
output
disable
Middle-High Voltage Input Buffer
(+6 V Withstand Voltage)
Schmitt-trigger input with hysteresis characteristic
Type D
IN/OUT
Type N
Comparator
VDD
data
P-ch
+
OUT
–
output
disable
N-ch
VREF (Threshold Voltage)
Push-pull output that can be made highimpedance output (P-ch and N-ch OFF)
Type E
data
IN/OUT
Type D
output
disable
Type A
This is an input/output circuit made up of a
Type D push-pull output and Type A input buffer.
10
µPD75108F,75112F,75116F
3.4
RECOMMENDED CONNECTION OF UNUSED PINS
Pin
Recommended Connection
PTH00 to PTH03
TI0
Connect to VSS or VDD.
TI1
P00
Connect to VSS.
P01 to P03
Connect to VSS or VDD.
P10 to P13
Connect to VSS.
P20 to P23
P30 to P33
P40 to P43
P50 to P53
Input
: Connect to VSS or VDD.
P60 to P63
P70 to P73
Output : Leave open.
P80 to P83
P90 to P93
P120 to P123
P130 to P133
P140 to P143
NC
*
Leave open *
If a printed board is used with the µPD75P116, NC pin should be connected to VDD directly.
11
µPD75108F,75112F,75116F
3.5 PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN
In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test
mode for testing internal µPD75116F operation (for IC testing).
The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if noise
exceeding V DD is applied during normal operation, the test mode may be entered, making it impossible for normal
operation to continue.
If, for example, inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from
these pins, and the pin voltage exceeds VDD, misoperation may result.
Wiring should therefore be carried out so that interwiring noise is suppressed as far as possible. If it is completely
impossible to suppress noise, noise prevention measures should be taken using an external component as shown
below.
●
Diode with small VF (0.3 V or less) connected
between P00/INT4 or RESET and VDD
●
Capacitor connected between
P00/INT4 or RESET and VDD
VDD
Diode with
small VF
12
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
µPD75108F,75112F,75116F
4. MEMORY CONFIGURATION
• Program memory (ROM)
:
8064 × 8 bits (0000H to 1F7FH) : µPD75108F
12160 × 8 bits (0000H to 2F7FH) : µPD75112F
16256 × 8 bits (0000H to 3F7FH) : µPD75116F
• 0000H to 0001H
: Vector table in which a program start address after reset is written.
• 0002H to 000BH : Vector table in which program start addresses after interruption are written.
• 0020H to 007FH : Table area referred by GETI instruction
• Data memory
• Data area : 512 × 4 bits (000H to 1FFH)
• Peripheral hardware area : 128 × 4 bits (F80H to FFFH)
13
µPD75108F,75112F,75116F
Fig. 4-1 Program Memory Map (µ PD75108F)
Address
7
0000H
6
MBE RBE
0
5
0
Internal Reset Start Address (High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
0004H
0006H
0008H
000AH
MBE RBE
MBE RBE
MBE RBE
MBE RBE
MBE RBE
0
0
0
0
0
INTBT/INT4 Start Address
(High-Order 5 Bits)
INTBT/INT4 Start Address
(Low-Order 8 Bits)
INT0/INT1 Start Address
(High-Order 5 Bits)
INT0/INT1 Start Address
(Low-Order 8 Bits)
INTSIO Start Address
(High-Order 5 Bits)
INTSIO Start Address
(Low-Order 8 Bits)
INTT0 Start Address
(High-Order 5 Bits)
INTT0 Start Address
(Low-Order 8 Bits)
INTT1 Start Address
(High-Order 5 Bits)
INTT1 Start Address
(Low-Order 8 Bits)
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL ! addr
Instruction
Subroutine
Entry Address
BR ! addr
Instruction
Branch Address
BR $ addr
Instruction Relative
Branch Address
–15 to –1,
+2 to +16
0020H
GETI Instruction Reference Table
007FH
0080H
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
07FFH
0800H
0FFFH
1000H
BRCB !caddr
Instruction
Branch Address
1F7FH
Remarks
14
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
µPD75108F,75112F,75116F
Fig. 4-2 Program Memory Map (µ PD75112F)
Address
7
0000H
6
MBE
RBE
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
0004H
0006H
0008H
000AH
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
INTBT/INT4 Start Address
(High-Order 6 Bits)
INTBT/INT4 Start Address
(Low-Order 8 Bits)
INT0/INT1 Start Address
(High-Order 6 Bits)
INT0/INT1 Start Address
(Low-Order 8 Bits)
INTSIO Start Address
(High-Order 6 Bits)
INTSIO Start Address
(Low-Order 8 Bits)
INTT0 Start Address
(High-Order 6 Bits)
INTT0 Start Address
(Low-Order 8 Bits)
INTT1 Start Address
(High-Order 6 Bits)
INTT1 Start Address
(Low-Order 8 Bits)
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL ! addr
Instruction
Subroutine
Entry Address
BR ! addr
Instruction
Branch Address
BR $ addr
Instruction Relative
Branch Address
–15 to –1,
+2 to +16
0020H
GETI Instruction Reference Table
007FH
0080H
07FFH
0800H
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
0FFFH
1000H
BRCB !caddr
Instruction
Branch Address
1FFFH
2000H
BRCB !caddr
Instruction
Branch Address
2F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
15
µPD75108F,75112F,75116F
Fig. 4-3 Program Memory Map (µ PD75116F)
Address
7
0000H
6
MBE
RBE
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H
0004H
0006H
0008H
000AH
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
INTBT/INT4 Start Address
(High-Order 6 Bits)
INTBT/INT4 Start Address
(Low-Order 8 Bits)
INT0/INT1 Start Address
(High-Order 6 Bits)
INT0/INT1 Start Address
(Low-Order 8 Bits)
INTSIO Start Address
(High-Order 6 Bits)
INTSIO Start Address
(Low-Order 8 Bits)
INTT0 Start Address
(High-Order 6 Bits)
INTT0 Start Address
(Low-Order 8 Bits)
INTT1 Start Address
(High-Order 6 Bits)
INTT1 Start Address
(Low-Order 8 Bits)
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL ! addr
Instruction
Subroutine
Entry Address
BR ! addr
Instruction
Branch Address
BR $ addr
Instruction Relative
Branch Address
–15 to –1,
+2 to +16
0020H
GETI Instruction Reference Table
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
Branch Destination
Address and Subroutine
Entry Address by GETI
Instruction
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
3F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order
8 bits have been changed by the BR PCDE or BR PCXA instruction.
16
µPD75108F,75112F,75116F
Fig. 4-4 Data Memory Map
Data Memory
General
Register Area
Memory Bank
000H
(32 × 4)
01FH
Bank 0
Data Area
Static RAM
(512 × 4)
Stack Area
256 × 4
0FFH
100H
256 × 4
Bank 1
1FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
Bank 15
FFFH
17
µPD75108F,75112F,75116F
5. PERIPHERAL HARDWARE FUNCTIONS
5.1
DIGITAL INPUT/OUTPUT PORTS
There are the following three digital input/output ports.
• CMOS input (PORT0, PORT1)
:
8
• CMOS input/output (PORT2 to PORT9)
: 32
• N-ch open-drain input/output (PORT12 to PORT14) : 12
Total
: 52
Table 5-1 List of Input/Output Pin Manipulation Commands
Port Name
Function
PORT 0
4-bit input
Operation/Features
Regardless of the operating mode of the shared
pin, reading or test is always possible.
Remarks
These pins are shared with SI,
SO, SCK, INT0 to INT4.
PORT 1
PORT 3
Can be set in the input or output bit-wise.
PORT 6
PORT 2
PORT 4
4-bit input/output *
PORT 5
PORT 7
Can be set in the input or output mode as a 4bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are
paired and data input/output is possible as an
8-bit unit.
Port 2, PT00, PT01, and PCL share
the same pins.
PORT 8
PORT 9
PORT12
4-bit input/output *
PORT13
(N-ch open-drain +10
V withstand voltage)
PORT14
*
18
Can drive a LED directly.
Can be set to input or output mode as a 4-bit
unit. Ports 12 and 13 are paired and data input/
output is possible as an 8-bit unit.
On-chip pull-up resistor specifiable bit-wise by mask option.
µPD75108,75112F,75116F
5.2
CLOCK GENERATOR
(1) Clock generator configuration
This is the circuit which generates various kinds of clock supplied to the CPU and peripheral hardware to control
the CPU operating mode.
This circuit can also change the instruction execution time.
• 0.95 µs/1.91 µs/15.3 µs (4.19 MHz operation)
Fig. 5-1 Clock Generator Block Diagram
• Basic Interval Timer (BT)
• Clock Output Circuit
• Timer/Event Counter
• Serial Interface
X1
1/8 to 1/4096
System Clock
Oscillation
Circuit
fXX or fX
Frequency Divider
1/2 1/16
X2
Frequency
Divider
Selector
Oscillation
Stop
1/4
Φ
• CPU
• Clock Output Circuit
PCC
Internal Bus
PCC0
PCC1
4
HALT *
HALT F/F
PCC2
S
PCC3
STOP *
R
PCC2,
PCC3
Clear
Q
STOP F/F
Q
Wait Release Signal from BT
S
RESET Signal
R
Remarks
Standby Release Signal from
Interrupt Control Circuit
1.
2.
fXX = Crystal/ceramic oscillator frequency
fX = External clock frequency
3.
Φ = CPU Clock
4.
* indicates instruction execution
5.
PCC : Processor clock control register
6.
One Φ clock cycle (t CY) is one machine cycle. See "AC
CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for tCY.
19
µPD75108F,75112F,75116F
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses
to remote control outputs or peripheral LSI’s.
• Clock output (PCL) : Φ , 524 kHz, 262 kHz (4.19 MHz operation)
Fig. 5-2 Configuration of Clock Output Circuit
From Clock
Generator
Φ
Output Buffer
fXX/2
3
Selector
P22/PCL
fXX/2
4
PORT2.2
CLOM3
0
CLOM1 CLOM0 CLOM
P22
Output Latch
4
Internal Bus
20
Bit 2 of PMGB
Bit Specified
in Port 2
Input/Output
Mode
µPD75108,75112F,75116F
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
• It operates as an interval timer which generates reference time interrupts.
• It can be applied as a watchdog timer which detects when a program is out of control.
• Selects and counts wait times when the standby mode is released.
• It reads count contents.
Fig. 5-3 Basic Interval Timer Configuration
From Clock
Generator
fXX/2
fXX/2
Clear
5
7
fXX/2
Set
Basic Interval Timer
(8-Bit Frequency Divider)
MPX
fXX/2
Clear
9
BT
12
BT Interrupt
Request Flag
IRQBT
Vector
Interrupt
Request
Signal
3
BTM3
*SET1
BTM2
BTM1
BTM0
Wait Release
Signal during
Standby Release
BTM
8
4
Internal Bus
Remarks
* indicates instruction execution.
5.5 TIMER/EVENT COUNTER
The µPD75116F incorporates two internal timer/event counter channels.
Timer/event counter channel 0 and channel 1 differ only in selectable count pulse (CP) and clock supply function
to serial interface and are the same in other configurations and functions.
The functions of the timer/event counter are as follows.
• Operates as a programmable interval timer.
• Outputs square waves in the desired frequency to the PTOn pin.
• Operates as an event counter.
• Use of TIn pin as an external interrupt input pin.
• Divides the TIn pin input into N divisions and outputs it to the PTOn pin (frequency divider operation).
• Supplies a serial shift clock to the serial interface circuit. (channel 0 only)
• Count status read function.
21
22
Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
Internal Bus
SET1
8
*1
8
8
TMn
TMODn
Modulo Register (8)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TOFn
8
TIn
TOn
PORT2.n
Bit 2 of PGMB
Port 2
P2n
Input/
Output
Output
Latch
Mode
To Serial
Interface*3
Match
TOUT
F/F
Comparator (8)
8
Input Buffer
TOEn
TO
Enable
Flag
P2n/PTOn
TO
Selector
Output
Buffer
Tn
TIn
*2
From Clock
Generator
Edge
Detector
Count Register (8)
MPX
CP
INTTn
(IRQTn Set Signal)
Clear
TMn1
Timer Operation Start
RESET
3. The serial interface signal is output only from timer/event counter channel 0.
IRQTn
Clear Signal
µPD75108F,75112F,75116F
* 1. SET1 : Instruction execution.
2. For details, see Fig. 5-1.
TMn0
µPD75108,75112F,75116F
5.6
SERIAL INTERFACE
The µPD75116F incorporates the clocked 8-bit serial interface. There are the following two modes of serial
interface.
• 3-wire serial I/O mode (MSB-first/LSB-first switchable)
• Operation stop mode
In the 3-wire serial I/O mode, the µPD75116F can be connected with the 75X series, 78K series and various kinds
of I/O devices.
23
24
Fig. 5-5 Serial Interface Block Diagram
Internal Bus
8
8
8
SIO0
P03/SI
SET1 *
SIO7
SIO
SIOM
Shift Registor (8)
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
P02/SO
Serial Clock
Counter (3)
INTSIO
IRQSIO
Set Signal
Overflow
Clear
IRQSIO
Clear Signal
Serial Start
P01/SCK
Q
Φ
S
fxx/2
4
fxx/2
10
MPX
TOF0
(from Timer Channel 0)
* SET1 : instruction execution
µPD75108F,75112F,75116F
R
µPD75108,75112F,75116F
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
The µPD75116F is provided with 4-bit analog input pins (PTH00 to PTH03) for which the threshold voltage can
be changed. These pins have a configuration as shown in Fig. 5-6.
0.5
15.5
The threshold voltage (VREF) can be selected in 16 ways (VDD × ——— — VDD × ———) and analog signals can be
16
16
directly input.
This port can also be used as a digital signal input port by selecting VDD × 7.5/16 as VREF.
Fig. 5-6 Programmable Threshold Port Block Diagram
Input Buffer
PTH00
+
+
PTH01
-
+
PTH02
-
Internal Bus
Programmable Threshold
Port Input Latch (4)
-
+
PTH03
-
Operation
Stopped
PTH0
VDD
PTHM7
1
2R
PTHM6
R
PTHM5
R
MPX
VREF
PTHM4
8
PTHM3
PTHM2
1
2R
4
PTHM1
PTHM0
PTHM
25
µPD75108F,75112F,75116F
5.8
BIT SEQUENTIAL BUFFER ······ 16 BITS
Bit manipulation of the bit sequential buffer is the bit manipulation special data memory. Since, in particular,
the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient
when processing data comprising a large number of bits bit-wise.
Fig. 5-7 Bit Sequential Buffer Format
Address
Bit
FC3H
3
Symbol
L Register L = F
2
1
FC2H
0
3
BSB3
2
1
FC1H
0
3
BSB2
L=CL=B
2
1
FC0H
0
3
BSB1
L=8L=7
2
L=4 L=3
INCS L
26
0
BSB0
DECS L
Remarks
1
In pmem. @L addressing, the specified bit moves according to the L register.
L=0
µPD75108F,75112F,75116F
6. INTERRUPT FUNCTION
The µPD75116F has 7 interrupt sources. Multiple interrupts with priority is are also possible.
Two test sources are also provided. The test sources are edge detection testable inputs.
Table 6-1 Interrupt Sources
Interrupt Source
INTBT (standard time interval signal from
basic interval timer)
INT4
(both rising edge and falling edge
detection)
INT0
(rising edge and falling edge
detection selection)
INT1
INTSIO (serial data transfer end signal)
Interrupt Order*1
Vector Interrupt Request
Signal
(Vector Table Address)
1
VRQ1
(0002H)
2
VRQ2
(0004H)
Internal
3
VRQ3
(0006H)
Internal/External
Internal
External
External
External
INTT0
(match signal from timer/event
counter# 0 or TI0 input edge detection)
Internal/external
4
VRQ4
(0008H)
INTT1
(match signal from timer/event
counter# 1 or TI1 input edge detection)
Internal/external
5
VRQ5
(000AH)
INT2*2 (rising edge detection)
External
INT3*2 (rising edge detection)
*
Testable input signal
(Set IRQ2 and IRQ3)
1. The interrupt order is the priority order when multiple interrupt requests are generated simultaneously.
2. INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt
sources, but do not generate vector interrupts.
The µPD75116F interrupt control circuit has the following functions:
• Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IE×××)
and interrupt master enable flag (IME).
• Arbitrary setting of interrupt start address.
• Multiple interruption function by which priority can be specified using the interrupt priority selection register
(IPS).
• Interrupt request flag (IRQ×××) test function (interrupt generation confirmation by software possible).
• Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
27
28
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus
2
2
IM1
IM0
INT
BT
INT4
/P00
INT0
/P10
INT1
/P11
INT3
/P13
Edge
Detection
Circuit
Edge
Detection
Circuit
Interrupt Enable Flag (IE XXX )
IPS
IST
Decoder
IRQBT
IRQ4
IRQ0
IRQ1
INTSIO
IRQSIO
INTT0
IRQT0
INTT1
IRQT1
Edge
Detection
Circuit
Edge
Detection
Circuit
(IME)
2
Priority Control
Circuit
Vector
Table
Address
Generator
IRQ2
IRQ3
Interrupt
Request
Flag
Standby Release
Signal
µPD75108F,75112F,75116F
INT2
/P12
Edge
Detection
Circuit
4
9
µPD75108F,75112F,75116F
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the µPD75116F has two standby modes (STOP mode
and HALT mode).
Table 7-1 Standby Mode Setting and Operation Status
STOP Mode
Operation Status
Setting instruction
HALT Mode
STOP instruction
HALT instruction
Clock generator circuit
System clock oscillation stopped
Only CPU clock Φ stopped
Basic interval timer
Operation stopped
Operable
(IRQBT set at reference time intervals)
Serial interface
Operation possible only when the
external SCK input and TO0 output
(when timer/event counter 0 is external
TI0 input) are selected as a serial clock
Operation possible if a clock other than Φ
is specified as a serial clock
Timer/event counter
Operable only when TIn pin input
specified as count clock
Operation possible
Clock output circuit
Operation stopped
Except CPU clock Φ, output possible.
External interrupt
Operation of INT0 to INT4 possible
CPU
Operation stopped
Release signal
Operation stopped
Interrupt request signal from operable hardware enabled by interrupt enable flag, or
RESET input
29
µPD75108F,75112F,75116F
8. RESET FUNCTION
The reset operation timing is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
Wait
(Approx. 31.3 ms: 4.19 MHz)
RESET Input
Operating Mode or Standby
Mode
HALT Mode
Internal Reset Operation
The state of hardware after reset operation is as shown in Table 8-1.
30
Operating Mode
µPD75108F,75112F,75116F
Table 8-1 Status of Each Hardware after Resetting
RESET Input in Standby
Mode
Hardware
µPD75108F
Low-order 5 bits of program
memory address 0000H are set
in PC12 to PC8 and the contents
of address 0001H are set in PC7
to PC0.
µPD75112F
µPD75116F
Low-order 6 bits of program
memory address 0000H are set
in PC13 to PC8 and the contents
of address 0001H are set in PC7
to PC0.
Program counter (PC)
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Sets program memory address
0000H bit 6 and bit 7 to RBE and
MBE, respectively.
Same as left
Bank enable flag (MBE, RBE)
Undefined
Stack pointer (SP)
Undefined
Held*
Undefined
General register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank selection register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
0
0
Data memory (RAM)
Basic interval
timer
Counter (BT)
Mode register (BTM)
0
0
FFH
FFH
0
0
TOEn, TOFn
0, 0
0, 0
Shift register (SIO)
Held
Undefined
Mode register (SIOM)
0
0
Processor clock control register (PCC)
0
0
0
0
Reset (0)
Reset (0)
Interrupt enable flag (IE×××)
0
0
Priority selection register (IPS)
0
0
Counter (Tn)
Timer/event
counter
(n = 0, 1)
Serial interface
Clock generator,
clock output
circuit
Modulo register (TMODn)
Mode register (TMn)
Clock output mode register (CLOM)
Interrupt request flag (IRQ×××)
Interrupt
Digital port
INT0, 1 mode registers (IM0, IM1)
0, 0
0, 0
Output buffer
OFF
OFF
Output latch
Clear (0)
Clear (0)
0
0
PTH00 to 03 input latch
Undefined
Undefined
Mode register (PTHM)
0
0
0
0
I/O mode register (PMGA, B, C)
Analog port
Bit sequential buffer (BSB0 to BSB3)
*
Same as left
Held
Carry flag (CY)
PSW
RESET Input during
Operation
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
31
µPD75108F,75112F,75116F
9.
INSTRUCTION SET
(1) Operand identifier and description
The operand is described in the operand field of each instruction in accordance with the description for the
operand identifier of the instruction. (For details, refer to RA75X Assembler Package User’s Manual Language
Volume (EEU-730).) When there are multiple elements in the description, one of the elements is selected. Upper
case letters and symbols (+,–) are keywords and are described unchanged.
Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (For details, refer
to µPD75116 User’s Manual (IEM-922).) However, there are restrictions on the labels for which fmem and pmem
can be used.
Identifier
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp'
rp'1
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL-, DE, DL
rpa1
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
8-bit immediate data or label*
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
*
32
Description
µPD75108F
0000H to 1F7FH immediate data or label
µPD75112F
0000H to 2F7FH immediate data or label
µPD75116F
0000H to 3F7FH immediate data or lebel
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
IE×××
RBn
MBn
PORT 0 to PORT 9, PORT12 to PORT14
IEBT, IESIO, IET0, IET1, IE0 to IE4
RB0 to RB3
MB0, MB1, MB15
In the case of the 8-bit data processing, an even address only can be described for mem.
µPD75108F,75112F,75116F
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register
C
D
E
H
:
:
:
:
C register
D register
E register
H register
L
X
XA
BC
:
:
:
:
L register
X register
Register pair (XA); 8-bit accumulator
Register pair (BC)
DE
HL
XA'
BC'
:
:
:
:
Register pair (DE)
Register pair (HL)
Extension register pair (XA')
Extension register pair (BC')
DE'
HL'
PC
SP
:
:
:
:
Extension register pair (DE')
Extension register pair (HL')
Program counter
Stack pointer
CY
PSW
MBE
RBE
:
:
:
:
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
PORTn
IME
IPS
IE×××
:
:
:
:
Portn (n = 0 to 9, 12 to 14)
Interrupt master enable flag
Interrupt priority selection register
Interrupt enable flag
RBS
MBS
PCC
.
:
:
:
:
Register bank selection register
Memory bank selection register
Processor clock control register
Address, bit delimiter
(××)
××H
: Contents addressed by ××
: Hexadecimal data
33
µPD75108F,75112F,75116F
(3) Description of addressing area field symbols
*1
MB = MBE • MBS (MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
µPD75108F : addr = 0000H to 1F7FH
µPD75112F : addr = 0000H to 2F7FH
µPD75116F : addr = 0000H to 3F7FH
*7
addr = (Current PC) –15 to
(Current PC) + 16
*8
µPD75108F : caddr =
=
µPD75112F : caddr =
=
=
µPD75116F : caddr =
=
=
=
0000H
1000H
0000H
1000H
2000H
0000H
1000H
2000H
3000H
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
Remarks
to
to
to
to
to
to
to
to
to
0FFFH
1F7FH
0FFFH
1FFFH
2F7FH
0FFFH
1FFFH
2FFFH
3F7FH
(PC12 = 0) or
(PC12 = 1)
(PC13, PC12 =
(PC13, PC12 =
(PC13, PC12 =
(PC13, PC12 =
(PC13, PC12 =
(PC13, PC12 =
(PC13, PC12 =
Data memory
addressing
00B)
01B)
10B)
00B)
01B)
10B)
11B)
or
or
Program memory
addressing
or
or
or
1.
2.
MB indicates the accessible memory bank.
For *2, MB = 0 without regard to MBE and MBS.
3.
4.
For *4 and *5, MB = 15 without regard to MBE and MBS.
*6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The value
of S changes as follows:
• No skip ....................................................................................................................................................................... S = 0
• When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1
• When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instructions) ........................... S = 2
Note
One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= tCY) of the CPU clockΦ. Three times can be selected by PCC setting.
34
µPD75108F,75112F,75116F
Instruction Group
Mnemonic
MOV
Transfer
XCH
Operands
Bytes Machine
Cycles
Operation
Addressing
Area
Skip
Condition
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
Stack A
HL, #n8
2
2
HL ← n8
Stack B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @HL+
1
2+S
A ← (HL), then L ← L + 1
*1
L=0
A, @HL-
1
2+S
A ← (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp'
2
2
XA ← rp'
reg1, A
2
2
reg1 ← A
rp'1, XA
2
2
rp'1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @HL+
1
2+S
A ↔ (HL), then L ← L + 1
*1
L=0
A, @HL-
1
2+S
A ↔ (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A,reg1
1
1
A ↔ reg1
XA, rp'
2
2
XA ↔ rp'
XA, @PCDE
1
3
Stack A
• µPD75108F
XA ← (PC12-8 + DE)ROM
• µPD75112F, 75116F
XA ← (PC13-8 + DE)ROM
Table Reference
MOVT
XA, @PCXA
1
3
• µPD75108F
XA ← (PC12-8 + XA)ROM
• µPD75112F, 75116F
XA ← (PC13-8 + XA)ROM
35
µPD75108F,75112F,75116F
Instruction
Group
Mnemonic
Operands
CY, fmem.bit
CY, pmem.@L
Bit
transfer
MOV1
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
ADDS
ADDC
SUBS
Operations
SUBC
AND
OR
Bytes Machine
Cycles
2
2
2
2
2
2
Addressing
Area
2
CY ← (fmem.bit)
*4
2
CY ← (pmem7 – 2 + L3 – 2.bit(L1–0))
*5
2
CY ← (H + mem3 – 0.bit)
*1
2
(fmem.bit) ← CY
*4
2
(pmem7 – 2 + L3 – 2.bit(L1–0)) ← CY
*5
2
(H + mem3 – 0.bit) ← CY
*1
Skip
Condition
A, #n4
1
1+S
A ← A + n4
XA, #n8
2
2+S
XA ← XA + n8
A, @HL
1
1+S
A ← A + (HL)
XA, rp'
2
2+S
XA ← XA + rp'
carry
rp'1, XA
2
2+S
rp'1 ← rp'1 + XA
carry
A, @HL
1
1
A, CY ← A + (HL) + CY
*1
carry
carry
carry
*1
XA, rp'
2
2
XA, CY ← XA + rp' + CY
rp'1, XA
2
2
rp'1, CY ← rp'1 + XA + CY
A, @HL
1
1+S
A ← A – (HL)
XA, rp'
2
2+S
XA ← XA – rp'
borrow
rp'1, XA
2
2+S
rp'1 ← rp'1 – XA
borrow
A, @HL
1
1
A, CY ← A – (HL) – CY
XA, rp'
2
2
XA, CY ← XA – rp' – CY
rp'1, XA
2
2
rp'1, CY ← rp'1 – XA – CY
A, #n4
2
2
A ← A ∧ n4
A, @HL
1
1
A ← A ∧ (HL)
XA, rp'
2
2
XA ← XA ∧ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∧ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
XOR
36
Operation
*1
*1
*1
*1
*1
borrow
µPD75108F,75112F,75116F
Instruction
Group
Mnemonic
Operands
Bytes Machine
Cycles
Operation
Addressing
Area
Skip Condition
A
1
1
CY ← A 0, A3 ← CY, An–1 ← An
A
2
2
A←A
reg
1
1+S
reg ← reg + 1
reg = 0
rp1
1
1+S
rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg – 1
reg = FH
rp'
2
2+S
rp' ←rp' – 1
rp' = FFH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, rp'
2
2+S
Skip if XA = rp'
XA = rp'
SET1
CY
1
1
CY ← 1
Carry flag CLR1
manipulation
SKT
CY
1
1
CY ← 0
CY
1
1+S
NOT1
CY
1
1
CY ← CY
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 0
*5
(pmem.@L) = 0
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L 3–2.bit (L1–0))
= 1 and clear
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit)
= 1 and clear
*1
(@H + mem.bit) = 1
Accumulator RORC
manipulation
NOT
INCS
Increment
/decrement
DECS
Comparison SKE
SET1
CLR1
Memory bit
manipulation SKT
CY = 1
Skip if CY = 1
SKF
SKTCLR
37
µPD75108F,75112F,75116F
Instruction
Group
Mnemonic
Operands
CY, fmem.bit
AND1
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
Memory bit
manipulation
OR1
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
XOR1
CY, pmem.@L
CY, @H + mem.bit
addr
Bytes Machine
Cycles
2
2
2
2
2
2
2
2
2
—
3
CY ← CY ∧ (fmem.bit)
*4
2
CY ← CY ∧ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∧ (H + mem3–0.bit)
*1
2
CY ← CY ∨ (fmem.bit)
*4
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∨ (H + mem3–0.bit)
*1
2
CY ← CY ∨ (fmem.bit)
*4
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
2
CY ← CY ∨ (H + mem3–0.bit)
*1
—
3
Branch
$addr
BRCB
!caddr
PCDE
1
2
2
2
2
3
BR
PCXA
2
Skip
Addressing
Condition
Area
2
BR
!addr
Operation
3
• µPD75108F
PC12–0 ← addr
(The assembler selects the optimum instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
• µPD75112F, 75116F
PC13–0 ← addr
(The assembler selects the optimum instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
• µPD75108F
PC12-0 ← addr
• µPD75112F, 75116F
PC13-0 ← addr
• µPD75108F
PC12-0 ← addr
• µPD75112F, 75116F
PC13-0 ← addr
*6
*6
*7
• µPD75108F
PC12-0 ← PC 12 + caddr 11-0
• µPD75112F, 75116F
PC13-0 ← PC13, PC12 + caddr11-0
*8
• µPD75108F
PC12-0 ← PC 12-8 + DE
• µPD75112F, 75116F
PC13-0 ← PC 13-8 + DE
• µPD75108F
PC12-0 ← PC 12-8 + XA
• µPD75112F, 75116F
PC13-0 ← PC 13-8 + XA
• µPD75108F
(SP-4) (SP-1) (SP-2) ← PC11-0
(SP-3) ← MBE, RBE, 0, PC12
Subroutine
stack control
38
CALL
!addr
3
3
PC12-0 ← addr, SP ← SP–4
• µPD75112F, 75116F
(SP-4) (SP-1) (SP-2) ← PC11-0
(SP-3) ← MBE, RBE, PC13, PC12
PC13-0 ← addr, SP ← SP–4
*6
µPD75108F,75112F,75116F
Instruction
Group
Mnemonic
CALLF
Operands Bytes Machine
Cycles
!faddr
2
1
RET
2
3
Subroutine
stack control
1
RETS
RETI
3+S
• µPD75112F, 75116F
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13, PC12
PC13–0 ← 000, faddr, SP ← SP – 4
• µPD75112F, 75116F
MBE, RBE, PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
• µPD75108F
MBE, RBE, ×, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4, then skip unconditionally
• µPD75112F, 75116F
MBE, RBE, PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4, then skip unconditionally
1
1
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp
1
1
rp ← (SP + 1) (SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
2
IME (IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME (IPS.3) ← 0
2
2
IE××× ← 0
IE×××
DI
IE×××
Unconditional
• µPD75108F
MBE, RBE, ×, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
PSW ← (SP + 4) (SP + 5 ), SP ← SP + 6
rp
EI
*9
• µPD75108F
MBE, RBE, ×, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
3
POP
Addressing
Skip Condition
Area
• µPD75108F
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, 0, PC12
PC12–0 ← 00, faddr, SP ← SP – 4
1
PUSH
Interrupt
control
Operation
• µPD75112F, 75116F
MBE, RBE, PC13, PC12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
PSW ← (SP + 4) (SP + 5 ), SP ← SP + 6
39
µPD75108F,75112F,75116F
Instruction
Group
Mnemonic
Bytes Machine
Cycles
Operation
A, PORTn
2
2
A← PORTn
XA, PORTn
2
2
XA ← PORTn + 1, PORTn (n = 4, 6, 8, 12)
PORTn, A
2
2
PORTn ← A
PORTn, XA
2
2
PORTn + 1, PORTn ← XA (n = 4, 6, 8, 12)
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n
MBn
2
2
MBS ← n (n = 0, 1, 15)
IN
*1
Input/output
*1
OUT
CPU control
Operands
SELL
Addressing
Skip Condition
Area
(n = 0 to 9, 12 to 14)
(n = 2 to 9, 12 to 14)
(n = 0 to 3)
• µPD75108F
TBR Instruction
PC12–0 ← (taddr)4–0 ← (taddr + 1)
---------------------------------------------------------TCALL Instruction
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
Special
*2
GETI
taddr
1
3
(SP – 3) ← MBE, RBE, 0, PC12
PC12–0 ← (taddr)4–0 ← (taddr + 1)
SP ← SP – 4
---------------------------------------------------------Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
• µPD75112F, 75116F
TBR Instruction
PC13–0 ← (taddr)5–0 ← (taddr + 1)
---------------------------------------------------------TCALL Instruction
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, 0, PC13, PC12
PC13–0 ← (taddr)5–0 ← (taddr + 1)
SP ← SP – 4
---------------------------------------------------------Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
*
40
*10
-----------------------Conforms to
referenced
instruction.
----------------------Conforms to
referenced
instruction.
1. When executing the IN/OUT instruction, <MBE = 0> or <MBE = 1, MBS = 15> must be set.
2. The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction.
IDC
µPD6130
µPD6131
µPD2840
µPD2841
Compression
MSK
Modem
Extension
MPX
Transmitter/
Receiver
Prescaler
Speaker
VCO
Speaker
Amp
PLL
TCXO
MPX
10. APPLICATION EXAMPLE
Amp
10.1 CORDLESS TELEPHONE (SUBSET)
Power Amp
Prescaler
LED Display
VCO
µPD75116F
PLL
Key Matrix
SIO
Radio Wave
Detection
Extra-Area
Detection
LCD
Controller/
Driver
µPD7228
LED
Display
Console
ID ROM
Detection
Filter
Mixer
2SC4226
1SS281
3SK177
Amp
2SC2757
2SC4182
Legend
41
IDC
:
Immediate Deviation Controller,
ID ROM
:
ID (Identification) Code ROM, LCD
:
Liquid Crystal Display,
LED
:
Light Emitting Diode,
MPX
:
Multiplexer,
MSK
:
Minimum Shift Keying,
PLL
:
Phase Locked Loop,
SIO
:
Serial Data Input/Output,
TCXO
:
Temperature Compensation Crystal Oscillator,
VCO
:
Voltage Control Oscillator
µPD75108F,75112F,75116F
µPD6252
µPD75108F,75112F,75116F
10.2 DISPLAY PAGER
µ PD75116F
Filter
INT
RAM
µ PD446
Code ROM
Switch
Piezoelectric
Buzzer
High-Current
Output
TO
LED Display
Comparator
Input
Battery Check
SIO
LCD Controller/Driver
µ PD7228/7229
42
LCD Display
µPD75108F,75112F,75116F
11. MASK OPTION SELECTION
The µPD75116F has the following mask option to select whether or not a pull-up resistor is incorporated.
Pin
Mask Option
P120 to P123
P130 to P133
Pull-up resistor can be incorporated bit-wise.
P140 to P143
43
µPD75108F,75112F,75116F
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
Supply voltage
SYMBOL
TEST CONDITIONS
RATING
UNIT
–0.3 to +5.5
V
–0.3 to VDD +0.3
V
–0.3 to VDD +0.3
V
–0.3 to +11
V
–0.3 to VDD +0.3
V
One pin
–15
mA
All pins
–30
mA
Peak value
30
mA
Effective value
15
mA
100
mA
60
mA
100
mA
60
mA
VDD
VI1
Except ports 12, 13 and 14
Input voltage
Internal pull-up resistor
VI2*1
Ports 12 to 14
Open–drain
Output voltage
VO
Output current
high
IOH
One pin
Output current low
IOL*2
Total of ports 0, 2 to 4, 12 to
14
Peak value
Effective value
Peak value
Total of ports 5 to 9
Effective value
*
Operating
temperature
Topt
–40 to +60
°C
Storage
temperature
Tstg
–65 to +150
°C
1. When a voltage exceeding 10V is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor)
should be 50KΩ or more.
2. Effective value should be calculated: [Effective value] = [Peak value] × √duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily.
The absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions which ensure that the absolute
maximum ratings are not exceeded.
44
µPD75108F,75112F,75116F
12.1 WHEN Ta = –40 to +50 °C, VDD = 2.7 to 5.0 V
OPERATING VOLTAGE (Ta = –40 to +50 °C)
PARAMETER
*
TEST CONDITIONS
MIN.
MAX.
UNIT
CPU*1
*2
5.0
V
Programmable threshold port
(comparator input)
4.5
5.0
V
Other hardware*1
2.7
5.0
V
1. Except system clock oscillation circuit, programmable threshold port.
2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = –40 to +50 °C, VDD = 2.7 to 5.0 V)
RESONATOR
RECOMMENDED
CONSTANT
X1
X2
PARAMETER
Oscillator
frequency (f XX)*1
VDD = Oscillation
voltage range
Oscillation
stabilization time*2
After VDD reaches
MIN. of oscillation
voltage range
Ceramic
resonator
C1
C2
X1
Oscillator
frequency (f XX)*1
X2
Crystal
resonator
C1
X1
C2
X2
External
clock
µPD74HCU04
*
TEST
CONDITIONS
Oscillation
stabilization time*2
MIN.
TYP.
2.0
2.0
VDD = 4.5 to 5.0 V
4.19
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
X1 input
frequency (f X)*1
2.0
5.0*3
MHz
X1 input
high-/low-level width
(t XH, tXL)
100
250
ns
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC
CHARACTERISTICS for instruction execution time.
2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of
oscillation voltage range or the STOP mode is released.
3. When the oscillator frequency is 4.19 MHz < fXX ≤ 5.0 MHz, PCC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 µs and the rated MIN. value
of 0.95 µs is not observed.
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure
enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect
to a ground pattern carrying a high current.
• A signal should be not taken from the oscillator.
45
★
µPD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
RECOMMENDED CERAMIC RESONATOR (Ta = –40 to +50 °C)
EXTERNAL CAPACITANCE [pF]
MANUFACTURER
Murata Mfg.
Kyocera
PRODUCT NAME
OSCILLATION VOLTAGE RANGE [V]
C1
C2
MIN.
MAX.
CSA 2.00MG
30
30
2.7
5.0
CSA 4.19MG
30
30
3.0
5.0
CSA 4.19MGU
30
30
2.7
5.0
CST 4.19T
––
––
3.0
5.0
KBR–2.0MS
100
100
3.0
5.0
KBR–4.0MS
33
33
3.0
5.0
KBR–4.19MS
33
33
3.0
5.0
KBR–4.9152M
33
33
3.0
5.0
RECOMMENDED CRYSTAL RESONATOR (Ta = –20 to +50 °C)
EXTERNAL CAPACITANCE [pF]
MANUFACTURER
Kinseki
46
PRODUCT NAME
HC-49/U
OSCILLATION VOLTAGE RANGE [V]
C1
C2
MIN.
MAX.
22
22
2.7
5.0
µPD75108F,75112F,75116F
DC CHARACTERISTICS (Ta = –40 to +50 °C, VDD = 2.7 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MAX.
UNIT
Other than below
0.7 V DD
VDD
V
VIH2
Ports 0,1,TI0, 1, RESET
0.8 V DD
VDD
V
Internal pull-up resistor
0.7 V DD
VDD
V
VIH3
Ports 12 and 14
Open–drain
0.7 V DD
12
V
VDD – 0.5
VDD
V
VIH4
X1, X2
VIL1
Other than below
0
0.3 VDD
V
VIL2
Ports 0,1,TI0, 1, RESET
0
0.2 VDD
V
VIL3
X1, X2
0
0.4
V
VDD = 4.5 to 5.0 V, IOH = –1 mA
Output voltage high
TYP.
VIH1
Input voltage high
Input voltage low
MIN.
VDD – 1.0
V
VDD – 0.5
V
VOH
IOH = –100 µA
Ports 0, 2 to 9, IOL = 15 mA
0.35
2.0
V
Ports 12 to 14, IOL = 10 mA
0.35
2.0
V
VDD = 4.5 to 5.0 V, IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
Other than below
3
µA
X1, X2
20
µA
Ports 12 to 14 (open-drain)
20
µA
Except X1, X2
–3
µA
–20
µA
VDD = 4.5 to 5.0 V
Output voltage low
VOL
ILIH1
Input leakage
current high
VIN = VDD
ILIH2
ILIH3
Input leakage
current low
VIV = 10 V
ILIL1
VIN = 0 V
X1, X2
ILIL2
ILOH1
VOUT = VDD
Other than below
3
µA
ILOH2
VOUT = 10 V
Ports 12 to 14 (open-drain)
20
µA
Output leakage
current low
ILOL
VOUT = 0 V
–3
µA
Internal pull-up
resistor
(mask option)
70
kΩ
RL
Ports 12 to 14
80
kΩ
3
9
mA
0.55
1.5
mA
600
1800
µA
200
600
µA
0.1
10
µA
Output leakage
current high
VDD = 4.5 to 5.0 V
15
40
10
VDD = 4.5 to 5.0 V*2
IDD1
Supply current*1
IDD2
IDD3
*
4.19 MHz
VDD = 3 V ±10 %*3
Crystal oscillation
C1 = C2 = 22 pF
VDD = 4.5 to 5.0 V
HALT
mode
VDD = 3 V ±10 %
STOP mode, VDD = 3 V ±10 %
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3. When the PCC register is set to 0000 for operation in the low-speed mode.
47
µPD75108F,75112F,75116F
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
Input/output
capacitance
SYMBOL
TEST CONDITIONS
MIN.
TYP.
CIN
COUT
f = 1 MHz
MAX.
UNIT
15
pF
15
pF
15
pF
MAX.
UNIT
±100
mV
Unmeasured pins returned to 0 V
CIO
COMPARATOR CHARACTERISTICS (Ta = –40 to +50 °C, VDD = 4.5 to 5.0 V)
PARAMETER
SYMBOL
Compare accuracy
VACOMP
Threshold voltage
VTH
0
VDD
V
PTH input voltage
VIPTH
0
VDD
V
Comparator circuit
current consumption
48
TEST CONDITIONS
PTHM7 set to "1"
MIN.
TYP.
1
mA
µPD75108F,75112F,75116F
AC CHARACTERISTICS (Ta = –40 to +50 °C, VDD = 2.7 to 5.0 V)
PARAMETER
SYMBOL
CPU clock cycle time*
(Minimum instruction
execution time = 1
machine cycle)
tCY
TI0, TI1 input
frequency
fTI
TI0, TI1 input high/
low-level width
TEST CONDITIONS
MIN.
VDD = 4.5 to 5.0 V
VDD = 4.5 to 5.0 V
tTIH,
TYP.
MAX.
UNIT
0.95
32
µs
1.91
32
µs
0
1
MHz
0
275
kHz
0.48
µs
1.8
µs
Input
0.8
µs
Output
0.95
µs
Input
3.2
µs
Output
3.8
µs
Input
0.4
µs
tKCY/2 – 50
ns
1.6
µs
tKCY/2 – 150
ns
VDD = 4.5 to 5.0 V
tTIL
V DD = 4.5 to 5.0 V
SCK cycle time
tKCY
VDD = 4.5 to 5.0 V
SCK high/low-level
width
tKH,
Output
tKL
Input
Output
SI setup time
(to SCK↑)
tSIK
100
ns
SI hold time
(from SCK↑)
tKSI
400
ns
SO output delay
time from SCK↓
tKSO
INT0 to INT4
High/low-level width
tINTH,
tINTL
5
µs
RESET low-level
width
tRSL
5
µs
VDD = 4.5 to 5.0 V
300
ns
1000
ns
49
µPD75108F,75112F,75116F
*
The CPU clock Φ cycle time is determined by the
oscillation frequency of the connected resonator
and the setting of the processor clock control
tCY vs. VDD
40
32
7
register (PCC). The graph on the right shows the
characteristic for cycle time tCY supply current VDD
during system clock operation.
6
5
Operating
Guarantee
Range
4
tCY [µ s]
3
2
1
0.5
0
1
2
3
4
VDD [V]
50
5
6
µPD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
0.7 VDD
0.7 VDD
Test Points
0.3 VDD
0.3 VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V
0.4 V
X1 Input
TI0,TI1 Input Timing
1/fTI
tTIL
TI0, TI1
tTIH
0.8 VDD
0.2 VDD
51
µPD75108F,75112F,75116F
Serial Transfer Timing
tKCY
tKH
tKL
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
Input Data
SI
0.8 VDD
0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
0.8 VDD
INT0–INT4
0.2 VDD
RESET Input Timing
tRSL
RESET
52
0.2 VDD
µPD75108F,75112F,75116F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +50 °C)
PARAMETER
SYMBOL
Data retention supply voltage
VDDDR
Data retention supply current*1
IDDDR
Release signal set time
tSREL
Oscillation stabilization time*2
tWAIT
TEST CONDITIONS
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.1
UNIT
5.0
V
10
µA
µs
0
Release by RESET
217/f XX
ms
*3
ms
Release by interrupt request
*
MAX.
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting (see table below).
WAIT TIME
BTM3
BTM2
BTM1
BTM0
—
0
0
0
220/fXX (approx. 250 ms)
—
0
1
1
217/fXX (approx. 31.3 ms)
—
1
0
1
215/fXX (approx. 7.82 ms)
—
1
1
1
213/fXX (approx. 1.95 ms)
(Figures in parentheses are for operation at fXX = 4.19 MHz)
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
53
µPD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
54
µPD75108F,75112F,75116F
12.2 WHEN Ta = –40 to +60 °C, VDD = 2.8 to 5.0 V
OPERATING VOLTAGE (Ta = –40 to +60 °C)
PARAMETER
*
TEST CONDITIONS
MIN.
MAX.
UNIT
CPU*1
*2
5.0
V
Programmable threshold port
(comparator input)
4.5
5.0
V
Other hardware*1
2.8
5.0
V
1. Except system clock oscillation circuit, programmable threshold port.
2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 2.8 to 5.0 V)
RESONATOR
RECOMMENDED
CONSTANT
X1
X2
PARAMETER
Oscillator
frequency (f XX)*1
VDD = Oscillation
voltage range
Oscillation
stabilization time*2
After VDD reaches
MIN. of oscillation
voltage range
Ceramic
resonator
C1
C2
X1
Oscillator
frequency (f XX)*1
X2
Crystal
resonator
C1
X1
C2
X2
External
clock
µPD74HCU04
*
TEST
CONDITIONS
Oscillation
stabilization time*2
MIN.
TYP.
2.0
2.0
VDD = 4.5 to 5.0 V
4.19
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
X1 input
frequency (f X)*1
2.0
5.0*3
MHz
X1 input
high-/low-level width
(t XH, tXL)
100
250
ns
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC
CHARACTERISTICS for instruction execution time.
2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of
oscillation voltage range, or the STOP mode is released.
3. When the oscillator frequency is 4.19 MHz < fXX ≤ 5.0 MHz, PCC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 µs and the rated MIN. value
of 0.95 µs is not observed.
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure
enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect
to a ground pattern carrying a high current.
• A signal should be not taken from the oscillator.
55
★
µPD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
RECOMMENDED CERAMIC RESONATOR (Ta = –40 to +60 °C)
EXTERNAL CAPACITANCE [pF]
MANUFACTURER
Murata Mfg.
Kyocera
PRODUCT NAME
OSCILLATION VOLTAGE RANGE [V]
C1
C2
MIN.
MAX.
CSA 2.00MG
30
30
2.7
5.0
CSA 4.19MG
30
30
3.0
5.0
CSA 4.19MGU
30
30
2.7
5.0
CST 4.19T
––
––
3.0
5.0
KBR–2.0MS
100
100
3.0
5.0
KBR–4.0MS
33
33
3.0
5.0
KBR–4.19MS
33
33
3.0
5.0
KBR–4.9152M
33
33
3.0
5.0
RECOMMENDED CRYSTAL RESONATOR (Ta = –20 to +60 °C)
EXTERNAL CAPACITANCE [pF]
MANUFACTURER
Kinseki
56
PRODUCT NAME
HC-49/U
OSCILLATION VOLTAGE RANGE [V]
C1
C2
MIN.
MAX.
22
22
2.7
5.0
µPD75108F,75112F,75116F
DC CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 2.8 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MAX.
UNIT
Other than below
0.7 VDD
VDD
V
VIH2
Ports 0,1,TI0, 1, RESET
0.8 VDD
VDD
V
Internal pull-up resistor
0.7 VDD
VDD
V
VIH3
Ports 12 to 14
Open–drain
0.7 VDD
10
V
VDD – 0.5
VDD
V
VIH4
X1, X2
VIL1
Other than below
0
0.3 VDD
V
VIL2
Ports 0,1,TI0, 1, RESET
0
0.2 VDD
V
VIL3
X1, X2
0
0.4
V
VDD = 4.5 to 5.0 V, IOH = –1 mA
Output voltage high
TYP.
VIH1
Input voltage high
Input voltage low
MIN.
VDD – 1.0
V
VDD – 0.5
V
VOH
IOH = –100 µA
Ports 0, 2 to 9, IOL = 15 mA
0.35
2.0
V
Ports 12 to 14, IOL = 10 mA
0.35
2.0
V
VDD = 4.5 to 5.0 V, IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
Other than below
3
µA
X1, X2
20
µA
Ports 12 to 14 (open-drain)
20
µA
Except X1, X2
–3
µA
X1, X2
–20
µA
VDD = 4.5 to 5.0 V
Output voltage low
VOL
ILIH1
Input leakage
current high
VIN = VDD
ILIH2
ILIH3
Input leakage
current low
VIV = 10 V
ILIL1
VIN = 0 V
ILIL2
ILOH1
VOUT = VDD
Other than below
3
µA
ILOH2
VOUT = 10 V
Ports 12 to 14 (open-drain)
20
µA
Output leakage
current low
ILOL
VOUT = 0 V
–3
µA
Internal pull-up
resistor
(mask option)
70
kΩ
RL
Ports 12 to 14
80
kΩ
3
9
mA
4.19 MHz
VDD = 2.8 to 3.3 V*3
Crystal oscillation
C1 = C2 = 22 pF
VDD = 4.5 to 5.0 V
HALT
mode
VDD = 2.8 to 3.3 V
0.55
1.5
mA
600
1800
µA
200
600
µA
STOP mode, VDD = 2.8 to 3.3 V
0.1
10
µA
Output leakage
current high
VDD = 4.5 to 5.0 V
15
40
10
VDD = 4.5 to 5.0 V*2
IDD1
Supply current*1
IDD2
IDD3
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3. When the PCC register is set to 0000 for operation in the low-speed mode.
57
µPD75108F,75112F,75116F
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
Input/output
capacitance
SYMBOL
TEST CONDITIONS
MIN.
TYP.
CIN
COUT
f = 1 MHz
MAX.
UNIT
15
pF
15
pF
15
pF
MAX.
UNIT
±100
mV
Unmeasured pins returned to 0 V
CIO
COMPARATOR CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 4.5 to 5.0 V)
PARAMETER
SYMBOL
Compare accuracy
VACOMP
Threshold voltage
VTH
0
VDD
V
PTH input voltage
VIPTH
0
VDD
V
Comparator circuit
current consumption
58
TEST CONDITIONS
PTHM7 set to "1"
MIN.
TYP.
1
mA
µPD75108F,75112F,75116F
AC CHARACTERISTICS (Ta = –40 to +60 °C, VDD = 2.8 to 5.0 V)
PARAMETER
SYMBOL
CPU clock cycle time*
(Minimum instruction
execution time = 1
machine cycle)
tCY
TI0, TI1 input
frequency
fTI
TI0, TI1 input high/
low-level width
TEST CONDITIONS
MIN.
VDD = 4.5 to 5.0 V
VDD = 4.5 to 5.0 V
tTIH,
TYP.
MAX.
UNIT
0.95
32
µs
1.91
32
µs
0
1
MHz
0
275
kHz
0.48
µs
1.8
µs
Input
0.8
µs
Output
0.95
µs
Input
3.2
µs
Output
3.8
µs
Input
0.4
µs
tKCY/2 – 50
ns
1.6
µs
tKCY/2 – 150
ns
VDD = 4.5 to 5.0 V
tTIL
V DD = 4.5 to 5.0 V
SCK cycle time
tKCY
VDD = 4.5 to 5.0 V
SCK high/low-level
width
tKH,
Output
tKL
Input
Output
SI setup time
(to SCK↑)
tSIK
100
ns
SI hold time
(from SCK↑)
tKSI
400
ns
SO output delay
time from SCK↓
tKSO
INT0 to INT4
High/low-level width
tINTH,
tINTL
5
µs
RESET low-level
width
tRSL
5
µs
VDD = 4.5 to 5.0 V
300
ns
1000
ns
59
µPD75108F,75112F,75116F
*
The CPU clock Φ cycle time is determined by the
oscillation frequency of the connected resonator
and the setting of the processor clock control
register (PCC). The graph on the right shows the
tCY vs. VDD
40
32
7
6
characteristic for cycle time tCY supply current VDD
during system clock operation.
5
Operating
Guarantee
Range
4
tCY [µ s]
3
2
1
0.5
0
1
2
3
4
VDD [V]
60
5
6
µPD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
0.7 VDD
Test Points
0.3 VDD
0.7 VDD
0.3 VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V
0.4 V
X1 Input
TI0, TI1 Input Timing
1/fTI
tTIL
TI0, TI1
tTIH
0.8 VDD
0.2 VDD
61
µPD75108F,75112F,75116F
Serial Transfer Timing
tKCY
tKH
tKL
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
Input Data
SI
0.8 VDD
0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
0.8 VDD
INT0–INT4
0.2 VDD
RESET Input Timing
tRSL
RESET
62
0.2 VDD
µPD75108F,75112F,75116F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +60 °C)
PARAMETER
SYMBOL
Data retention supply voltage
VDDDR
Data retention supply current*1
IDDDR
Release signal set time
tSREL
Oscillation stabilization time*2
tWAIT
TEST CONDITIONS
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.1
UNIT
5.0
V
10
µA
µs
0
Release by RESET
217/f XX
ms
*3
ms
Release by interrupt request
*
MAX.
1. Excluding current flowing in the internal pull-up resistors and comparator circuit.
2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting (see table below).
WAIT TIME
BTM3
BTM2
BTM1
BTM0
—
0
0
0
220/fXX (approx. 250 ms)
—
0
1
1
217/fXX (approx. 31.3 ms)
—
1
0
1
215/fXX (approx. 7.82 ms)
—
1
1
1
213/fXX (approx. 1.95 ms)
(Figures in parentheses are for operation at fXX = 4.19 MHz)
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
63
µPD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
64
µPD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE)
IDD vs. VDD (Crystal Oscillator : 4.19 MHz)
(Ta = 25 °C)
High-Speed Mode
Medium-Speed Mode
1000
Low-Speed Mode
Supply Current IDD [µA]
HALT Mode
X1
100
X2
Crystal
4.19 MHz
22pF
22pF
10
0
1
2
3
4
5
6
Supply Voltage VDD [V]
65
µPD75108F,75112F,75116F
IDD vs. fXX Characteristic Examples (Crystal Oscillation)
(VDD = 5.0 V, Ta = 25 °C)
3.0
Values in parentheses indicate PCC set values.
X1
Supply Current IDD [mA]
2.5
X2
C1
High-Speed Mode [0011]
C2
2.0
Medium-Speed Mode
[0010]
1.5
Low-Speed Mode [0000]
1.0
HALT Mode [0100]
0.5
0
0
1
2
3
4
5
fXX [MHz]
IDD vs. fXX Characteristic Examples (Ceramic Oscillation)
(VDD = 5.0 V, Ta = 25 °C)
3.0
Values in parentheses indicate PCC set values.
High-Speed Mode [0011]
X1
X2
Supply Current IDD [mA]
2.5
C1
C2
2.0
Medium-Speed Mode
[0010]
1.5
Low-Speed Mode [0000]
1.0
HALT Mode [0100]
0.5
0
0
1
2
3
4
fXX [MHz]
66
5
µPD75108F,75112F,75116F
IDD vs. fX Characteristic Examples (External Clock)
(VDD = 5.0 V, Ta = 25 °C)
3.0
Values in parentheses indicate PCC set values.
X1
Supply Current IDD [mA]
2.5
X2
µPD74HCU04
High-Speed Mode [0011]
2.0
Medium-Speed Mode
[0010]
1.5
Low-Speed Mode [0000]
1.0
0.5
HALT Mode [0100]
0
0
1
2
3
4
5
fX [MHz]
67
µPD75108F,75112F,75116F
fTI vs. VDD Characteristic
TIn Input Frequency fTI [kHz]
(Ta = –40 to +50 °C)
1000
500
Operating
Guarantee
Range
100
50
0
0
1
2
3
4
5
6
7
VDD [V]
fTI vs. VDD Characteristic
TIn Input Frequency fTI [kHz]
(Ta = –40 to +60 °C)
1000
500
Operating
Guarantee
Range
100
50
0
0
1
2
3
4
VDD [V]
68
5
6
7
µPD75108F,75112F,75116F
VOL vs. IOL (Ports 0, 2 to 9) Characteristic Examples
VDD = 5 V
30
Ports 0, 2 to 9 Output Current Low IOL [mA]
VDD = 4 V
VDD = 3 V
20
10
0
0
1
2
3
4
VOL [V]
VOL vs. IOL (Ports 12 to 14) Characteristic Examples
VDD = 5 V
30
Ports 12 to 14 Output Current Low IOL [mA]
VDD = 4 V
20
VDD = 3 V
10
0
0
1
2
3
4
VOL [V]
69
µPD75108F,75112F,75116F
VOH vs. IOH (Ports 0, 2 to 9) Characteristic Examples
VDD = 5 V
-15
Ports 0, 2 to 9 Output Current High IOH [mA]
VDD = 4 V
-10
VDD = 3 V
-5
0
0
1
2
3
VDD – VOH [V]
Remarks
70
Characteristic curves not marked "Guarantee Range" indicate reference values.
4
µPD75108F,75112F,75116F
14. PACKAGE INFORMATION
64
PINPlastic
PLASTIC
QFP
(14×20)
64-Pin
QFP (14
× 20)
A
B
33
32
64
1
20
19
detail of lead end
F
Q
5°±5°
D
C
S
51
52
G
H
I M
J
M
P
K
N
L
P64GF-100-3B8,3BE,3BR-1
NOTE
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.40 ± 0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.8 ± 0.2
0.071–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
Q
0.1 ± 0.1
S
3.0 MAX.
+0.008
0.106
0.004 ± 0.004
0.119 MAX.
71
µPD75108F,75112F,75116F
64-Pin Ceramic QFP for ES (Reference Diagram)
14.2
64
52
51
19
20
33
32
18.0
1
0.4
0.15
2.25
1.0
20
12.0
Caution
1.
Note that the metal cap is
connected to pin 26, and is
at the VSS (GND) level.
2.
Note that the leads on the
underside are formed at an
angle.
3.
Cutting of the lead tips is
not process-controlled, and
therefore there is no stan-
Bottom
View
dard lead length.
72
µPD75108F,75112F,75116F
15. RECOMMENDED SOLDERING CONDITIONS
The µPD75116F should be soldered and mounted under the conditions recommended in the table below.
For details of recommended conditions, refer to the information document "Semiconductor Device Mount
Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 15-1 Surface Mount Type Soldering Conditions
µPD75108FGF-×××-3BE : 64-Pin Plastic QFP (14 × 20 mm)
µPD75112FGF-×××-3BE : 64-Pin Plastic QFP (14 × 20 mm)
µPD75116FGF-×××-3BE : 64-Pin Plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature : 230 °C, Duration : 30 sec. max. (at 210 °C or
avove), Number of times : once
IR30-00-1
VPS
Package peak temperature : 215 °C, Duration : 40 sec. max. (at 200 °C or
above), Number of times : once
VP15-00-1
Wave soldering
Solder bath temperature : 260 °C max., Duration : 10 sec. max., Number of
times : once, Preheating temperature : 120 °C max. (package surface
temperature)
WS60-00-1
Pin part heating
Pin part temperature : 300 °C max., Duration : 3 sec. max. (per device side)
Pin part heating
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Notice
A version of this product with improved recommended soldering conditions is
available. For details (improvements such as infrared reflow peak temperature
extension (235 °C), number of times: twice, relaxation of time limit, etc.), contact
NEC sales personnel.
73
µPD75108F,75112F,75116F
★
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD751×× SERIES PRODUCTS
Product Name
Item
ROM (byte)
RAM (× 4 bits)
µPD75104/106/108/112/116
µPD75104A/108A
µPD75108F/112F/116F
4K/6K/8K/12K/16K
(Mask ROM)
4K/8K
(Mask ROM)
8K/12K/16K
(Mask ROM)
320/320/512/512/512
320/512
512
Instruction set
75X High-End
Total
58
CMOS input
10
10 (Pull-up resistor mask option : 4) 10
CMOS
input/output
32 (LED direct drive capability)
32 (Pull-up resistor mask option : 24,
32 (LED direct drive capability)
LED direct drive capability)
I/O N-ch open-drain
port input/output
12 (LED direct drive capability)
+12 V
Withstand voltage
Pull-up resistor
+10 V
Can be incorporated by mask option
4 (4-bit precision)
Analog input
Power-on reset circuit
On-chip (Mask option)
None
Power-on flag
Operating voltage
Operating temperature
range
Minimum instruction
execution time
Package *2
*
2.7 to 6.0 V
2.7 to 5.0 V (Ta = –40 to +50 °C)
2.8 to 5.0 V
–40 to +85 °C
–40 to +60 °C
0.95 µs (operating at 4.5 to 6.0 V)
3.8 µs (operating at 2.7 V)
0.95 µs (operating at 4.5 to 5.0 V)
1.91 µs (operating at 2.7V)
• 64-pin plastic shrink DIP
• 64-pin plastic QFP(GF-3BE)
• 64-pin plastic QFP (G-1B)
: µPD75104/106/108 only
• 64-pin plastic QFP(GF-3BE)
1. 75X High-End can also be used by means of the 16K-byte mode/24K-byte mode switching function.
2. The following five types of plastic QFP are available.
• G-1B ........ 14 × 20 × 2.05 mm, 1.0 mm pitch
• GC-AB8 ... 14 × 14 × 2.55 mm, 0.8 mm pitch
• GF-3BE .... 14 × 20 × 2.7 mm, 1.0 mm pitch
• G-22 ........ 14 × 14 × 1.5 mm, 0.8 mm pitch
• GK-7ET ... 12 × 12 × 1.45 mm, 0.65 mm pitch
3. Under development.
74
• 64-pin plastic QFP(GC-AB8)
• 64-pin plastic QFP (G-22)
: µPD75108A only
µPD75108F,75112F,75116F
µPD75116H/117H
µPD75P108B
µPD75P116
µPD75P117H
16K/24K
(Mask ROM)
8K
(One-time PROM)
24K
(One-time PROM)
768
512
768
75X High-End/Extended
High-End
75X High-End
75X Extended
High-End*1
58
10
32 (LED direct drive
capability : 8)
32 (LED direct drive capability)
32 (LED direct drive
capability : 8)
12
12 (LED direct drive capability)
12
+6 V
+12 V
+6 V
Can be incorporated by
mask option
None
4 (4-bit precision)
None
1.8 to 5.0 V
–40 to +60 °C
0.95 µs (operating at 2.7 V)
1.91 µs (operating at 1.8 V)
None
5 V ±10 %
2.7 to 6.0 V
–40 to +85 °C
0.95 µs (operating at 4.5 to 6.0 V)
3.8 µs (operating at 2.7 V)
• 64-pin plastic QFP (GC-AB8) • 64-pin plastic shrink DIP
• 64-pin plastic QFP (GK-7ET) • 64-pin plastic QFP (GF-3BE)
• 64-pin ceramic shrink DIP
with window
0.95 µs
(operating at 4.75 to 5.5 V)
1.8 to 5.0 V
–40 to +60 °C
0.95 µs (operating at 2.7 V)
1.91 µs (operating at 1.8 V)
• 64-pin plastic shrink DIP
• 64-pin plastic QFP (GC-AB8)
• 64-pin plastic QFP (GF-3BE) • 64-pin plastic QFP
(GK-7ET)*3
75
µPD75108F,75112F,75116F
★
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD75116F.
Hardware
IE-75000-R*1
IE-75001-R
75X series in-circuit emulator
IE-75000-R-EM*2
Emulation board for the IE-75000-R or IE-75001-R
EP-75108GF-R
Emulation probe for the µPD75116FGF. A 64-pin conversion socket (EV-9200G-64) is also
provided.
EV-9200G-64
PG-1500
PROM programmer
PA-75P116GF
PROM programmer adapter for the µPD75P116GF, connected to the PG-1500.
IE Control Program
Software
PG-1500 Controller
RA75X Relocatable
Host machines
• PC-9800 series (MS-DOS™ Ver. 3.30 to Ver. 5.00A*3)
• IBM PC/AT™ (PC-DOS™ Ver.3.1)
Assembler
*
1. Maintenance product
2. Not incorporated in the IE-75001-R.
3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software.
Remarks
76
Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.
µPD75108F,75112F,75116F
★
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User’s Manual
IEM–1260
Instruction Application Table
Application Note
Not Available
(I)
Introductory Volume
IEM–1139
(II)
Remote Control Reception
Volume
IEM–1281
(III) Barcode Reader Volume
IEM–1265
(IV) MSK Transmission/Reception
IC Control Volume
IEM–1278
75X Series Selection Guide
IF–1027
Development Tools Documents
Document Name
Document Number
IE-75000-R/IE-75001-R User’s Manual
EEU–1455
IE-75000-R-EM User’s Manual
EEU–1294
EP-75108GF-R User’s Manual
EEU–1318
PG-1500 User’s Manual
EEU–1335
Hardware
Operation Volume
EEU–1346
Language Volume
EEU–1343
RA75X Assembler Package User’s Manual
Software
PG-1500 Controller User’s Manual
EEU–1291
Other Documents
Document Name
Document Number
Package Manual
IEI–1213
Surface Mount Technology Manual
IEI–1207
Quality grade on NEC Semiconductor Devices
IEI–1209
NEC Semiconductor Device Reliability & Quality Control
Not Available
Electrostatic Discharge (ESD) Test
Not Available
Semiconductor Devices Quality Guide Guarantee Guide
Microcomputer Related Products Guide Other Manufacturers Volume
Note
MEI–1202
Not Available
The information in these related documents is subject to change without notice. For design purpose, etc.,
be sure to use the latest ones.
77
µPD75108F,75112F,75116F
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.