DATA SHEET MOS INTEGRATED CIRCUIT µPD754202, 754202(A) 4-BIT SINGLE-CHIP MICROCONTROLLERS The µPD754202 is a member of the 75XL Series of 4-bit single-chip microcontrollers that enable data processing equivalent to that of an 8-bit microcontroller. It features expanded CPU functions compared to the 75X Series and enables high-speed, low-voltage operation at 1.8 V, making it suitable for battery-driven applications. The µPD754202(A) is a higher-reliability product compared to the µ PD754202. Detailed function descriptions, etc., are provided in the following user’s manual. Be sure to read it when designing. µPD754202 User’s Manual: U11132E FEATURES • • • Key return reset function for keyless entry Low-voltage operation: VDD = 1.8 to 6.0 V On-chip memory • Program memory (ROM): 2048 × 8 bits • Data memory (RAM) • : 128 × 4 bits Variable instruction execution time useful for high-speed operation and power save • 0.95, 1.91, 3.81, 15.3 µs (at 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (at 6.0-MHz operation) • Compact package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)) APPLICATIONS Automotive electronics such as keyless entry units The µPD754202 and µPD754202(A) have different quality grades. Unless otherwise specified, descriptions in this data sheet apply to the µPD754202. The information in this document is subject to change without notice. Document No. U12181EJ1V0DS00 (1st edition) Date Published May 1997 N Printed in Japan © 1997 µPD754202, 754202(A) ORDERING INFORMATION Part Number Package Quality Grade µPD754202GS-×××-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) Standard µPD754202GS-×××-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Standard µPD754202GS(A)-×××-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) Special µPD754202GS(A)-×××-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Special Remark ××× indicates the ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Differences between µPD754202 and µPD754202(A) Part Number µPD754202 µPD754202(A) Item Quality grade 2 Standard Special µPD754202, 754202(A) FUNCTION LIST Parameter Function Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (system clock: at 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (system clock: at 6.0-MHz operation) On-chip memory ROM 2048 × 8 bits RAM 128 × 4 bits General-purpose register • 4-bit manipulation: 8 × 4 banks • 8-bit manipulation: 4 × 4 banks I/O port CMOS input 4 Mask option-specifiable on-chip pull-up resistor CMOS input/output 9 Software-specifiable on-chip pull-up resistor connection Total 13 Timer 4 channels • 8-bit timer counter: 3 channels (Usable as 16-bit timer counter) • Basic interval timer/watchdog timer: 1 channel Bit sequential buffer (BSB) 16 bits Vectored interrupt External: 1, Internal: 4 Test input External: 1 (key return reset function provided) System clock oscillation circuit Ceramic/crystal oscillation circuit Standby function STOP/HALT mode Operating ambient temperature T A = –40 to +85 ˚C Supply voltage VDD = 1.8 to 6.0 V Package • 20-pin plastic SOP (300 mil, 1.27-mm pitch) • 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) 3 µPD754202, 754202(A) CONTENTS 1. PIN CONFIGURATION (Top View) .................................................................................................... 6 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION .................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Non-port Pins .............................................................................................................................. 9 Pin Input/Output Circuits ......................................................................................................... 10 Recommended Connection of Unused Pins .......................................................................... 11 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 12 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 12 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 13 5. MEMORY CONFIGURATION ............................................................................................................14 6. PERIPHERAL HARDWARE FUNCTION ......................................................................................... 17 6.1 Digital I/O Port ........................................................................................................................... 17 6.2 Clock Generator ........................................................................................................................17 6.3 Basic Interval Timer/Watchdog Timer ..................................................................................... 19 6.4 Timer Counter ........................................................................................................................... 20 6.5 Bit Sequential Buffer ................................................................................................................24 7. INTERRUPT FUNCTION AND TEST FUNCTION ........................................................................... 25 8. STANDBY FUNCTION .......................................................................................................................27 9. RESET FUNCTION ............................................................................................................................28 9.1 Configuration and Operation Status of Reset Function ........................................................ 28 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 32 10. MASK OPTION ..................................................................................................................................34 11. INSTRUCTION SETS ......................................................................................................................... 35 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44 13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................ 53 14. PACKAGE DRAWINGS ......................................................................................................................55 15. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 57 4 µPD754202, 754202(A) APPENDIX A. µPD754202, 75F4264 FUNCTION LIST ..................................................................... 58 APPENDIX B. DEVELOPMENT TOOLS ..............................................................................................59 APPENDIX C. RELATED DOCUMENTS ..............................................................................................62 5 µPD754202, 754202(A) 1. PIN CONFIGURATION (Top View) • 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754202GS-×××-BA5 µPD754202GS(A)-×××-BA5 • 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) µPD754202GS-×××-GJG µPD754202GS(A)-×××-GJG RESET 1 20 KRREN X1 2 19 P80 X2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62 9 12 P72/KR6 P63 10 11 P73/KR7 IC: Internally Connected (Connect directly to VDD) Pin Identification IC INT0 KR4 to KR7 KRREN P30 to P33 P60 to P63 P70 to P73 P80 PTO0 to PTO2 RESET VDD VSS X1, X2 6 : : : : : : : : : : : : : Internally Connected External Vectored Interrupt Key Return 4 to 7 Key Return Reset Enable Port 3 Port 6 Port 7 Port 8 Programmable Timer Output 0 to 2 Reset Positive Power Supply Ground System Clock (Ceramic/Crystal) µPD754202, 754202(A) 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/WATCHDOG TIMER PORT3 4 P30-P33 PORT6 4 P60-P63 PORT7 4 P70-P73 PORT8 1 P80 SP (8) INTBT RESET CY ALU 8-BIT TIMER COUNTER#0 PTO0/P30 INTT0 TOUT SBS PROGRAM COUNTER INTT1 8-BIT TIMER COUNTER#1 PTO1/P31 8-BIT TIMER COUNTER#2 PTO2/P32 BANK GENERAL REG. CASCADED 16-BIT TIMER COUNTER PROGRAM MEMORY (ROM) 2048×8 BITS DATA MEMORY (RAM) 128×4 BITS INTT2 INT0/P61 INTERRUPT CONTROL KRREN KR4/P70KR7/P73 BIT SEQ. BUFFER (16) DECODE AND CONTROL 4 CPU CLOCK Φ fX/2N CLOCK SYSTEM CLOCK STAND BY CONTROL DIVIDER GENERATOR X1 X2 IC V DD VSS RESET 7 µPD754202, 754202(A) 3. PIN FUNCTION 3.1 Port Pins Pin Name Input/Output Alternate Function Input/Output PTO0 8-bit I/O After Reset I/O Circuit TypeNote – Input E-B – Input F -A 4-bit input port (PORT7). On-chip pull-up resistor can be specified bit-wise (mask option). – Input B -A 1-bit input/output port (PORT8). On-chip pull-up resistor can be specified by software. – Input F -A Function P31 PTO1 P32 PTO2 P33 – Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units. – Programmable 4-bit input/output port (PORT6). P30 P60 Input/Output P61 INT0 P62 – P63 – P70 Input KR4 P71 KR5 P72 KR6 P73 KR7 P80 Input/Output – This port can be specified input/output bit-wise. On-chip pull-up resistor can be specified by software in 4-bit units. Noise eliminator can be selected on P61/ INT0. Note Circled characters indicate Schmitt trigger input. 8 µPD754202, 754202(A) 3.2 Non-port Pins Pin Name PTO0 Input/Output Alternate Function Output P30 PTO1 P31 PTO2 P32 After Reset I/O Circuit TypeNote Input E-B Input F -A Falling edge detection testable input Input B -A Input B – – – B -A Function Timer counter output INT0 Input P61 Edge detection vectored interrupt input (detected edge is selectable) Noise eliminator selectable Noise eliminator/ asynchronous selectable KR4 to KR7 Input P70 to P73 KRREN Input – Key return reset enable. When KRREN = high level in STOP mode, reset signal is generated at falling edge of KRn. X1 Input – X2 – System clock oscillation crystal/ceramic connection pin. If using an external clock, input to X1 and reverse input to X2. RESET Input – System reset input (low-level active). Pull-up resistor can be incorporated on-chip (mask option). IC – – Internally connected. Connect directly to VDD. – – V DD – – Positive power supply – – V SS – – Ground potential – – Note Circled characters indicate Schmitt trigger input. 9 µPD754202, 754202(A) 3.3 Pin Input/Output Circuits The µPD754202 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch CMOS standard input buffer N-ch output disable Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt trigger input with hysteresis characteristics P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-A VDD P.U.R. VDD P.U.R. enable P.U.R. (Mask Option) P-ch data IN output disable P.U.R. : Pull-Up Resistor IN/OUT Type D Type B P.U.R. : Pull-Up Resistor 10 µPD754202, 754202(A) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin Recommended Connecting Method P30/PTO0 Input state : Independently connect to VSS or VDD via a resistor. P31/PTO1 Output state: Leave open. P32/PTO2 P33 P60 P61/INT0 P62 P63 P70/KR4 Connect to VDD. P71/KR5 P72/KR6 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. IC Connect directly to VDD. 11 µPD754202, 754202(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The µPD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS). • Mk I mode : Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. • Mk II mode: Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Number of stack bytes Mk II mode 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles for subroutine instructions Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. The number of stack bytes (usable area) during execution of subroutine call instructions increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALL !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. 12 µPD754202, 754202(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Because SBS.3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS.3 to “0” to select the Mk II mode. 13 µPD754202, 754202(A) 5. • MEMORY CONFIGURATION Program Memory (ROM): 2048 × 8 bits (0000H-07FFH) • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. • Addresses 0002H to 000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt service can start from any address. • Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. • Data Memory (RAM) • Data area: 128 words × 4 bits (000H-07FH) • Peripheral hardware area: 128 words × 4 bits (F80H-FFFH) 14 µPD754202, 754202(A) Figure 5-1. Program Memory Map Address 7 6 0000H MBE RBE 5 4 0 0 0 3 0 0001H Internal reset start address (high-order 3 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE 0 0 0 INTBT start address INTBT start address 0003H 0004H MBE RBE 0 0 0 INT0 start address INT0 start address 0005H (high-order 3 bits) (low-order 8 bits) CALLF !faddr instruction entry address (high-order 3 bits) (low-order 8 bits) 0006H 0007H 0008H 0009H 000AH MBE RBE 0 0 0 000BH INTT0 start address 000CH MBE RBE 000DH INTT0 start address 0 0 0 (high-order 3 bits) (low-order 8 bits) Branch address of BR !addr BRCB !caddr BR BCDE BR BCXA BRA !addr1Note CALL !addr CALLA !addr1Note instructions INTT1/INTT2 start address (high-order 3 bits) INTT1/INTT2 start address (low-order 8 bits) GETI branch/call address BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H 07FFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be made to an address with only the low-order 8 bits of the PC changed by means of a BR PCDE or BR PCXA instruction. 15 µPD754202, 754202(A) Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (128 × 4) Memory bank (32 × 4) Stack area 128 × 4 0 (96 × 4) 07FH 080H 0FFH Not incorporated F80H 128 × 4 Peripheral hardware area FFFH 16 15 µPD754202, 754202(A) 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port The following two types of I/O ports are provided. • CMOS Input (PORT7) : 4 • CMOS Input/Output (PORT3, 6, 8) : 9 Total 13 Table 6-1. Types and Features of Digital Ports Port Name PORT3 Function 4-bit I/O Operation and Features Can be set to input or output mode bit-wise. PORT6 Remarks Also used for PTO0 to PTO2 pins. Also used for INT0 pin. PORT7 4-bit input PORT8 1-bit I/O 4-bit input only port On-chip pull-up resistor can be specified by mask option bit-wise. Can be set to input or output mode bit-wise. Also used for KR4 to KR7 pins. – 6.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed as follows. • 0.95, 1.91, 3.81, 15.3 µs (system clock operating at 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (system clock operating at 6.0 MHz) 17 µPD754202, 754202(A) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · INT0 noise eliminator X1 X2 System clock oscillator 1/1 to 1/4096 fX Divider Oscillation stops Selector 1/2 1/41/16 Divider Internal bus 1/4 Φ · CPU · INT0 noise eliminator PCC PCC0 PCC1 HALT F/F 4 PCC2 S HALTNote PCC3 R STOPNote PCC2, PCC3 clear Q STOP F/F Q S Wait release signal from BT Reset signal R Note Instruction execution Remarks 1. 18 Standby release signal from interrupt control circuit fX: System clock frequency 2. Φ = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. µPD754202, 754202(A) 6.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 6-2. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear Clear fX/25 fX/27 MPX Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution 19 µPD754202, 754202(A) 6.4 Timer Counter The µPD754202 incorporates three timer counters. Its configuration is shown in Figures 6-3, 6-4, and 6-5. The timer counter functions are shown below. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 6-2. Mode List Channel Mode Channel 0 Channel 1 Channel 2 8-bit timer counter mode TM10 TM21 TM20 0 0 0 0 0 0 0 1 PWM pulse generator mode × 16-bit timer counter mode × 1 0 1 0 Carrier generator mode × 0 0 1 1 Remark : Available ×: Not available 20 × TM11 Figure 6-3. Timer Counter (Channel 0) Block Diagram Internal bus 8 SET1Note 8 8 – TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) 0 PORT3.0 P30 output latch PMGA bit 0 Port 3 input/output mode 8 Match Comparator (8) TOUT F/F P30/PTO0 Output buffer 8 Reset T0 fx/24 From clock generator 6 fx/2 fx/28 MPX CP Count register (8) Clear fx/210 Timer operation start Instruction execution Caution Always set bits 0 and 1 to 0 when setting data to TM0. RESET IRQT0 clear signal 21 µPD754202, 754202(A) Note INTT0 IRQT0 set signal 22 Figure 6-4. Timer Counter (Channel 1) Block Diagram Internal bus 8 SET1Note TOE1 TM1 – 8 T1 enable flag TM16 TM15TM14TM13TM12TM11TM10 TMOD1 Decoder PORT3.1 P31 output latch PMGA bit 1 Port 3 input/output mode Modulo register (8) 8 Match Comparator (8) Timer counter (channel 2) output fx/25 fx/26 From clock fx/28 generator TOUT F/F 8 P31/PTO1 Output buffer Reset T1 MPX CP Count register (8) Clear fx/210 fx/212 RESET Timer operation start 16-bit timer counter mode IRQT1 clear signal Selector Timer counter (channel 2) reload signal Timer counter (channel 2) comparator (When 16-bit timer counter mode) Note Instruction execution µPD754202, 754202(A) Timer counter (channel 2) match signal (When 16-bit timer counter mode) INTT1 IRQT1 set signal Figure 6-5. Timer Counter (Channel 2) Block Diagram Internal bus Note 8 TM2 TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 TMODH High-level period setting modulo register (8) Modulo register (8) 8 0 8 Decoder – – – TC2 PORT3.2 PMGA bit 2 P32 Port 3 input/output output mode latch TOE2 REMCNRZB NRZ Reload MPX (8) 8 Match TOUT F/F Comparator (8) fx fx/2 From clock fx/24 generator fx/26 fx/28 fx/210 8 TMOD2 8 Reset T2 MPX CP Count register (8) Clear Overflow P32/PTO2 Output buffer Selector – SET1 Selector 8 Timer counter (channel 1) clock input Carrier generator mode INTT2 IRQT2 set signal 16-bit timer counter mode Timer operation start IRQT2 clear signal RESET Caution Always set bit 7 to 0 when setting data to TC2. 23 µPD754202, 754202(A) Note Instruction execution Timer counter (channel 1) clear signal (When 16-bit timer counter mode) Timer counter (channel 1) match signal Timer counter (channel 1) match signal (When carrier generator mode) (When 16-bit timer counter mode) µPD754202, 754202(A) 6.5 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 6-6. Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. 2. 24 In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. µPD754202, 754202(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD754202 is provided with five types of interrupt sources and one test source to enable a variety of applications. The interrupt control circuit of the µPD754202 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software. • Release the standby mode. The interrupt to be released can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQ2) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. 25 26 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 4 Interrupt enable flag (IE×××) IM2 IME IPS IST1 IST0 IM0 Decoder VRQn INT0/P61 Note1 KR4/P70 Selector INTBT Edge detector IRQBT IRQ0 INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 Falling edge detectorNote 2 Vector table address generator Priority control circuit IRQ2 KR7/P73 Key return reset circuit Notes 1. 2. Standby release signal Noise eliminator (Standby release is disabled when noise eliminator is selected.) The INT2 pin is not available. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0. µPD754202, 754202(A) IM2 µPD754202, 754202(A) 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD754202. Table 8-1. Operation Status in Standby Mode Mode Item STOP mode HALT mode Set instruction STOP instruction HALT instruction Operation status Clock generator Operation stops. Only the CPU clock Φ halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable BT mode : The IRQBT is set in the reference time interval. WT mode: Reset signal generation by BT overflow. Timer counter Operation stops. Operable. External interrupt The INT0 is not operableNote. The INT2 is operable at the falling edge of KRn. CPU Release signal Note Operation stops. • Reset signal • Interrupt request signal sent from interrupt enabled hardware • System reset signal (key return reset) generated by KRn falling edge when KRREN pin = 1. • Reset signal • Interrupt request signal sent from interrupt enabled hardware Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 27 µPD754202, 754202(A) 9. RESET FUNCTION 9.1 Configuration and Operation Status of Reset Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure 9-1. Figure 9-1. Configuration of Reset Function VDD Mask option RESET Internal reset signal Watchdog timer overflow S R Q WDF Q KRF Instruction KRREN S R Q R S Instruction STOP mode VDD One-shot pulse generator Interrupt Falling edge detector Mask option P71/KR5 P72/KR6 P73/KR7 28 Internal bus P70/KR4 µPD754202, 754202(A) The RESET signal generation initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following 2 time modes can be specified with mask option. 2 17/fx (21.8 ms: at 6.0-MHz operation, 31.3 ms: at 4.19-MHz operation) 2 15/fx (5.46 ms: at 6.0-MHz operation, 7.81 ms: at 4.19-MHz operation) 29 µPD754202, 754202(A) Table 9-1. Hardware Status After Reset (1/3) RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 3 bits of program memory’s address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 3 bits of program memory’s address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer counter Counter (T0) 0 0 (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer counter Counter (T1) (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter Counter (T2) (T2) Modulo register (TMOD2) FFH FFH High-level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB 30 µPD754202, 754202(A) Table 9-1. Hardware Status After Reset (2/3) Hardware RESET signal generation in the standby mode RESET signal generation in operation 0 0 Reset (0) Reset (0) Clock generator Processor clock control register (PCC) Interrupt Interrupt request flag (IRQ×××) function Interrupt enable flag (IE×××) 0 0 Interrupt master enable flag (IME) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 2 mode registers (IM0, IM2) 0, 0 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGC) 0 0 Pull-up resistor setting register (POGA, POGB) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0-BSB3) Table 9-1. Hardware Status After Reset (3/3) RESET signal generation by key return reset RESET signal generation in the standby mode RESET signal generation by WDT during operation RESET signal generation during operation Watchdog flag (WDF) Hold the previous status 0 1 0 Key return flag (KRF) 1 0 Hold the previous status 0 Hardware 31 µPD754202, 754202(A) 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is set by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated. As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on. Table 9-2 lists the contents of WDF and KRF corresponding to each signal. Figure 9-3 shows the WDF operation in generating each signal, and Figure 9-4 shows the KRF operation in generating each signal. Table 9-2. WDF and KRF Contents Correspond to Each Signal Hardware External RESET signal generation Reset signal Reset signal generation by watch- generation by the dog timer overflow KRn input WDF clear instruction execution KRF clear instruction execution Watchdog flag (WDF) 0 1 Hold 0 Hold Key return flag (KRF) 0 Hold 1 Hold 0 Figure 9-3. WDF Operation in Generating Each Signal Reset signal generation by watchdog timer overflow External RESET signal generation Reset signal generation by watchdog timer overflow WDF clear instruction execution WDF External RESET Operation mode HALT mode Operation mode HALT mode Operation mode HALT mode Operation mode Operation mode Internal reset operation 32 Internal reset operation Internal reset operation µPD754202, 754202(A) Figure 9-4. KRF Operation in Generating Each Signal Reset signal generation by the KRn input Reset signal generation by the KRn input External RESET signal generation STOP instruction execution STOP instruction execution KRF clear instruction execution KRF External RESET Operation mode STOP mode HALT mode Operation mode HALT mode Operation mode STOP mode HALT mode Operation mode Operation mode Internal reset operation Internal reset operation Internal reset operation 33 µPD754202, 754202(A) 10. MASK OPTION The µPD754202 has the following mask options: • Mask option of P70/KR4 through P73/KR7 Pull-up resistors can be connected to these pins. (1) No pull-up resistor connection (2) Connection of a 30-kΩ (typ.) pull-up resistor in 1-bit units. (3) Connection of a 100-kΩ (typ.) pull-up resistor in 1-bit units. • Mask option of RESET pin Pull-up resistors can be connected to these pins. (1) No pull-up resistor connection (2) Connection of a 100-kΩ (typ.) pull-up resistor. • Standby function mask option The wait time after RESET signal can be selected. (1) 217/fx (21.8 ms: fx = 6.0-MHz operation, 31.3 ms: fx = 4.19-MHz operation) (2) 2 15/fx (5.46 ms: fx = 6.0-MHz operation, 7.81 ms: fx = 4.19-MHz operation) 34 µPD754202, 754202(A) 11. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER PACKAGE USERS’ MANUAL — LANGUAGE (EEU-1363)”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see µPD754202 User’s Manual (U11132E). Expression format Description method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 rp2 rp' rp'1 BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1(only in Mk II mode) caddr faddr 0000H-07FFH immediate data or label 0000H-07FFH immediate data or label taddr 20H-7FH immediate data (where bit0 = 0) or label PORTn IE××× RBn MBn PORT3, 6, 7, 8 IEBT, IET0-IET2, IE0, IE2 RB0-RB3 MB0, MB15 DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' 12-bit immediate data or label 11-bit immediate data or label Note mem can be only used for even address in 8-bit data processing. 35 µPD754202, 754202(A) (2) Legend in explanation of operation 36 A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ extended register pair BC’ : BC’ extended register pair DE’ : DE’ extended register pair HL’ : HL’ extended register pair PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 3, 6, 7, 8) IME : Interrupt master enable flag IPS : Interrupt priority selection register IE××× : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (××) : The contents addressed by ×× ××H : Hexadecimal data µPD754202, 754202(A) (3) Explanation of symbols under addressing area column *1 MB = MBE•MBS (MBS = 0, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-07FFH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H-07FFH *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 addr1 = 0000H-07FFH Remarks 1. Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of the CPU clock (= tCY); time can be selected from among four types by setting PCC. 37 µPD754202, 754202(A) Instruction group Transfer instruction Mnemonic MOV XCH Table reference instructions MOVT Number of bytes Number of machine cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 XA ← (PC10–8+DE)ROM XA, @PCXA 1 3 XA ← (PC10–8+XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 3 XA ← (BCXA)ROM *6 Operand XA, @BCXA Note 38 “0” must be set to the B register. 1 Operation Addressing area Skip condition String effect A Note µPD754202, 754202(A) Instruction group Bit transfer instructions Operation instructions Number of bytes Number of machine cycles CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp' 2 2 XA ← XA ∧ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A Mnemonic MOV1 ADDS ADDC SUBS SUBC AND OR XOR Accumulator manipulation instructions Operand Operation Addressing area *1 Skip condition carry *1 *1 borrow *1 *1 *1 *1 39 µPD754202, 754202(A) Instruction group Increment and Decrement instructions Number of bytes Number of machine cycles reg 1 1+S reg ← reg+1 reg = 0 rp1 1 1+S rp1 ← rp1+1 rp1 = 00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg–1 reg = FH rp' 2 2+S rp' ← rp'–1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 1 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 2 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY SET1 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0 Mnemonic INCS DECS Comparison instruction Carry flag manipulation instruction Memory bit manipulation instructions SKE CLR1 SKT SKF 40 Operand Operation Addressing area Skip if CY = 1 Skip condition CY = 1 µPD754202, 754202(A) Instruction group Memory bit manipulation instructions Number of bytes Number of machine cycles fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 and clear *1 (@H+mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 addr – – PC10–0 ← addr Select appropriate instruction among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. *6 addr1 – – PC10-0 ← addr1 Select appropriate instruction among BR !addr, BRA !addr1, BRCB !caddr, and BR $addr1 according to the assembler being used. *11 !addr 3 3 PC10–0 ← addr *6 $addr 1 2 PC10–0 ← addr *7 $addr1 1 2 PC10–0 ← addr1 PCDE 2 3 PC10–0 ← PC10-8+DE PCXA 2 3 PC10–0 ← PC10-8+XA BCDE 2 3 PC10–0 ← BCDENote 2 *6 BCXA 2 3 PC10–0 ← BCXANote 2 *6 BRANote 1 !addr1 3 3 PC10–0 ← addr1 *11 BRCB !caddr 2 2 PC10–0 ← caddr10–0 *8 Mnemonic SKTCLR AND1 OR1 XOR1 Branch instructions Notes 1. BR Note 1 Operand Operation Addressing area Skip condition The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the MK I mode. 2. “0” must be set to the B register. 41 µPD754202, 754202(A) Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes Number of machine cycles Operation Addressing area CALLANote !addr1 3 3 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← 0, PC10–0 (SP–5) ← 0, 0, 0, 0 PC10–0 ← addr1, SP ← SP–6 *11 CALLNote !addr 3 3 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← 0, PC10–0 PC10–0 ← addr, SP ← SP–4 *6 4 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← 0, PC10–0 (SP–5) ← 0, 0, 0, 0 PC10–0 ← addr, SP ← SP–6 2 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← 0, PC10–0 PC10–0 ← 0+faddr, SP ← SP–4 3 (SP–2) ← ×, ×, MBE, RBE (SP–6) (SP–3) (SP–4) ← 0, PC10–0 (SP–5) ← 0, 0, 0, 0 PC10–0 ← 0+faddr, SP ← SP–6 3 PC10–0 ← (SP)2–0 (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 CALLFNote !faddr RETNote 2 1 Skip condition *9 ×, ×, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC10–0 ← (SP)2–0 (SP+3) (SP+2), SP ← SP+6 RETSNote 1 3+S MBE, RBE, 0, 0 ← (SP+1) PC10–0 ← (SP)2–0 (SP+3) (SP+2) SP ← SP+4 then skip unconditionally Unconditional 0, 0, 0, 0 ← (SP+1) PC10–0 ← (SP)2–0 (SP+3) (SP+2) ×, ×, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally RETINote 1 3 MBE, RBE, 0, 0 ← (SP+1) PC10–0 ← (SP)2–0 (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 0, 0, 0, 0 ← (SP+1) PC10–0 ← (SP)2–0 (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 PUSH POP Note rp 1 1 (SP–1) (SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1) (SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 42 µPD754202, 754202(A) Instruction group Interrupt control instructions Mnemonic Operand EI IE××× DI Input/output instructions CPU control instructions Special instructions Number of bytes Number of machine cycles 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 Addressing area Operation IE××× 2 2 IE××× ← 0 Note 1 IN A, PORTn 2 2 A ← PORTn (n = 3, 6, 7, 8) OUTNote 1 PORTn, A 2 2 PORTn ← A (n = 3, 6, 8) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 15) GETINotes 2, 3 taddr 1 3 • When TBR instruction PC10–0 ← (taddr) 2–0 + (taddr+1) SEL Skip condition *10 –––––––––––––––––––––––––––––––––– ––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← 0, PC10–0 (SP–3) ← MBE, RBE, 0, 0 PC10–0 ← (taddr) 2–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 • When TBR instruction PC10–0 ← (taddr) 2–0 + (taddr+1) ––––––––––––––––––––––––––––––––––––– –––– 4 Notes 1. *10 ––––––––––––– • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC10–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← ×, ×, MBE, RBE PC10–0 ← (taddr) 2–0 + (taddr+1) SP ← SP–6 ––––––––––––––––––––––––––––––––––––– –––– 3 Depending on the reference instruction • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ––––––––––––– Depending on the reference instruction While the IN instruction and OUT instruction are being executed, MBS must be set to 0, or MBE must be set to 1 and MBS must be set to 15. 2. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 3. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 43 µPD754202, 754202(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Test Conditions Ratings Unit –0.3 to +7.0 V Supply voltage V DD Input voltage VI –0.3 to V DD + 0.3 V Output voltage VO –0.3 to V DD + 0.3 V Output current, high IOH Pins except P32 –10 mA Only P32 –20 mA All pins total –30 mA Per pin 20 mA All pins total 90 mA Output current, low I OL Per pin Operating ambient temperature TA –40 to +85 °C Storage temperature T stg –65 to +150 °C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25 °C, V DD = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF 44 µPD754202, 754202(A) System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 6.0 V) Resonator Recommended Constant Ceramic Parameter Testing Conditions Oscillation resonator X1 frequency X2 C1 C2 TYP. MAX. Unit 6.0Note 2 MHz 4 ms 6.0Note 2 MHz 10 ms 30 ms 1.0 6.0Note 2 MHz 83.3 500 ns 1.0 (fX)Note 1 Oscillation After V DD reaches MIN. stabilization value of oscillation timeNote 3 voltage range Crystal Oscillation resonator frequency(fX)Note 1 X1 MIN. 1.0 X2 Oscillation stabilization C1 VDD = 4.5 to 6.0 V timeNote 3 C2 External X1 input clock frequency (fX)Note 1 X1 X2 X1 input high- and low-level widths (t XH, tXL) Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ V DD < 2.7 V, set the processor clock control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 0.95 µs is not satisfied. 3. The oscillation stabilization time is the time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: • Keep the wire length as short as possible. • Do not cross other signal lines. • Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. • Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 45 µPD754202, 754202(A) RECOMMENDED CIRCUIT CONSTANTS Ceramic Resonator (TA = –20 to +80 ˚C) Manufacturer Product Frequency Circuit constant (pF) (MHz) C1 C2 MIN.(V) MAX.(V) 2.0 6.0 Murata Mfg. CSB1000JNote 1.0 100 100 Co., Ltd. CSA2.00MG040 2.0 100 100 – – 30 30 CST4.00MGW – – CSA4.00MGU 30 30 CST4.00MGWU – – 30 30 CST4.19MGW – – CSA4.19MGU 30 30 CST4.19MGWU – – 30 30 CST6.00MGW – – CSA6.00MGU 30 30 CST6.00MGWU – – CST2.00MG040 CSA4.00MG CSA4.19MG CSA6.00MG Kyocera Corp. Oscillation voltage range (V DD) 4.0 4.19 6.0 Rd = 2.2 kΩ – Capacitor incorporated – Capacitor incorporated 1.8 – Capacitor incorporated 2.0 – Capacitor incorporated 1.8 – Capacitor incorporated 2.9 – Capacitor incorporated 2.4 – Capacitor incorporated KBR-1000F/Y 1.0 100 100 1.8 KBR-2.0MS 2.0 68 68 2.0 KBR-4.19MKC 4.19 – – 1.8 33 33 – – 33 33 – – KBR-4.19MSB Remark 6.0 – Capacitor incorporated – PBRC4.19A PBRC4.19B KBR-6.0MKC Capacitor incorporated 6.0 KBR-6.0MSB – PBRC6.00A PBRC6.00B Note Capacitor incorporated If using Murata’s CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 2.2 kΩ) is required (see figure below). If using any other recommended resonator, no limited resistor is needed. X1 X2 CSB1000J C1 Rd C2 Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed. 46 µPD754202, 754202(A) DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 6.0 V) Parameter High-level output current Symbol IOH Conditions MAX. Unit –5 mA –15 mA All pins total –20 mA Per pin 15 mA All pins total 45 mA Per pin MIN. Pins except P32 Only P32, VDD = 3.0 V, VOH = V DD–2.0 V Low-level output current High-level input voltage IOL VIH1 VIH2 Low-level input voltage High-level output voltage Low-level output voltage –7 2.7 V ≤ V DD ≤ 6.0 V 0.7 VDD VDD V 1.8 V ≤ VDD < 2.7 V 0.9 V DD VDD V Ports 6-8, KRREN, 2.7 V ≤ V DD ≤ 6.0 V 0.8 VDD VDD V RESET 1.8 V ≤ VDD < 2.7 V 0.9 V DD VDD V VDD–0.1 VDD V 2.7 V ≤ V DD ≤ 6.0 V 0 0.3 VDD V 1.8 V ≤ VDD < 2.7 V 0 0.1 V DD V Ports 6-8, KRREN, 2.7 V ≤ V DD ≤ 6.0 V 0 0.2 VDD V RESET 1.8 V ≤ VDD < 2.7 V 0 0.1 V DD V 0 0.1 V Port 3 VIH3 X1 VIL1 Port 3 VIL2 TYP. VIL3 X1 VOH VDD = 4.5 to 6.0 V, IOH = –1.0 mA VDD–1.0 V VDD = 1.8 to 6.0 V, IOH = –100 µA VDD–0.5 V V OL VDD = 4.5 to 6.0 V Port 3, IOL = 15 mA 0.6 2.0 V 0.4 V VDD = 1.8 to 6.0 V, IOL = 400 µA 0.5 V VIN = V DD Pins except X1 3.0 µA X1 20 µA Pins except X1 –3.0 µA X1 –20 µA Ports 6, 8, IOL = 1.6 mA High-level input leak ILIH1 current ILIH2 Low-level input leak ILIL1 current ILIL2 High-level output leak current ILOH VOUT = VDD 3.0 µA Low-level output ILOL VOUT = 0 V –3.0 µA RL1 VIN = 0 V VIN = 0 V leak current On-chip pull-up resistance RL2 Ports 3, 6, 8 50 100 200 kΩ Port 7 (mask option) 15 30 60 kΩ 50 100 200 kΩ 50 100 200 kΩ RESET (mask option) 47 µPD754202, 754202(A) DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 6.0 V) Parameter Supply current Note 1 Symbol IDD1 IDD2 IDD3 Test Conditions TYP. MAX. Unit VDD = 5.0 V ± 10 % Note 2 1.5 5.0 mA Crystal resonator VDD = 3.0 V ± 10 % Note 3 0.23 1.0 mA 4.19 MHz C1 = C2 = 22 pF X1 = 0 V MIN. HALT VDD = 5.0 V ± 10 % 0.64 3.0 mA mode VDD = 3.0 V ± 10 % 0.20 0.9 mA 5 µA 1 µA 0.1 3 µA 0.1 1 µA VDD = 1.8 to 6.0 V TA = 25 °C STOP mode VDD = 3.0 V ± 10 % TA = –40 to +40 °C Notes 1. Does not include current fed to on-chip pull-up resistor. 2. When processor clock control register (PCC) is set to 0011, during high-speed mode. 3. When PCC is set to 0000, during low-speed mode. 48 µPD754202, 754202(A) AC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 6.0 V) Parameter CPU clock cycle time Note 1 Symbol tCY (Minimum instruction execution Test Conditions When system tINTH, tINTL INT0 Unit 0.67 64.0 µs 1.8 V ≤ V DD < 2.7 V 0.95 64.0 µs IM02 = 1 KR4-KR7 Notes 1. MAX. 2.7 V ≤ V DD ≤ 6.0 V IM02 = 0 low-level widths RESET low-level width TYP. clock is used time = 1 machine cycle) Interrupt input high- and MIN. tRSL The CPU clock (Φ) cycle time (minimum Note 2 µs 10 µs 10 µs 10 µs tCY vs VDD instruction execution time) is determined (During system clock operation) by the oscillation frequency of the connected resonator (and external clock) and 64 60 the processor clock control register (PCC). The figure on the right shows the cycle 6 time tCY characteristics against the supply 5 voltage VDD when the system clock is used. 4 2t CY or 128/fx depending on the setting of the interrupt mode register (IM0). Cycle time tCY [µs] 2. Operation guaranteed range 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 49 µPD754202, 754202(A) AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock Timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V Interrupt Input Timing tINTH tINTL INT0, KR4-7 RESET Input Timing tRSL RESET 50 µPD754202, 754202(A) Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C) Parameter Symbol Test Conditions MIN. Release signal set time tSREL Oscillation stabilization wait timeNote 1 Notes 1. tWAIT TYP. MAX. Unit µs 0 Release by RESET Note 2 ms Release by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 2. 2 17/fx and 215/fx can be selected with mask option. 3. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM3 BTM2 BTM1 BTM0 Wait Time When fX = 4.19 MHz – – – – 0 0 1 1 0 1 0 1 0 220/fX 1 217/fX 1 215/fX 1 213/fX When fX = 6.0 MHz (Approx. 250 ms) 220/fX (Approx. 175 ms) (Approx. 31.3 ms) 217/fX (Approx. 21.8 ms) (Approx. 7.81 ms) 215/fX (Approx. 5.46 ms) (Approx. 1.95 ms) 213/fX (Approx. 1.37 ms) Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode VDD tSREL Execution of STOP instruction RESET tWAIT 51 µPD754202, 754202(A) Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 52 µPD754202, 754202(A) 13. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs V DD (System clock: 6.0-MHz crystal resonator) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 53 µPD754202, 754202(A) IDD vs V DD (System clock: 4.19-MHz crystal resonator) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 0.001 0 1 2 3 4 5 Supply Voltage VDD (V) 54 22 pF 6 7 8 µPD754202, 754202(A) 14. PACKAGE DRAWINGS 20 PIN PLASTIC SOP (300 mil) 20 11 P detail of lead end 1 10 A H J E K F G I C N D M L B M NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.00 MAX. 0.512 MAX. B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40 +0.10 –0.05 0.016 +0.004 –0.003 E 0.1±0.1 0.004±0.004 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7±0.3 0.303±0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008 +0.004 –0.002 L 0.6±0.2 0.024 +0.008 –0.009 M 0.12 0.005 N 0.10 0.004 P 3° +7° –3° 3° +7° –3° P20GM-50-300B, C-4 55 µPD754202, 754202(A) 20 PIN PLASTIC SHRINK SOP (300 mil) 20 11 3° +7° –3° detail of lead end 1 10 A H J E K F G I C D N B L M M P20GM-65-300B-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 56 ITEM MILLIMETERS INCHES A 7.00 MAX. 0.276 MAX. B 0.575 MAX. 0.023 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.30 ± 0.10 0.012+0.004 –0.005 E 0.125 ± 0.075 0.005 ± 0.003 F 2.0 MAX. 0.079 MAX. G 1.7 0.067 H 8.1 ± 0.3 0.319 ± 0.012 I 6.1 ± 0.2 0.240 ± 0.008 J 1.0 ± 0.2 0.039 –0.008 K 0.15 +0.10 –0.05 0.006+0.004 –0.002 L 0.5 ± 0.2 0.020 –0.009 M 0.12 0.005 N 0.10 0.004 +0.009 +0.008 µPD754202, 754202(A) 15. RECOMMENDED SOLDERING CONDITIONS The µ PD754202 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions µPD754202GS-×××-BA5 : 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754202GS-×××-GJG : 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) µPD754202GS(A)-×××-BA5 : 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754202GS(A)-×××-GJG : 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Reflow time: 30 seconds or below (at 210 °C or higher), Number of reflow processes: Twice or less IR35-00-2 VPS Package peak temperature: 215 °C, Reflow time: 40 seconds or below (at 200 °C or higher), Number of reflow processes: Twice or less VP15-00-2 Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of flow processes: 1 WS60-00-1 Preheating temperature: 120 °C or below (package surface temperature) Partial heating Caution Pin temperature: 300 °C or below, Time: 3 seconds or below (per side of device) — Do not use different soldering methods together (except for partial heating). 57 µPD754202, 754202(A) APPENDIX A. µPD754202, 75F4264 FUNCTION LIST µPD754202 Item Program memory Data memory Mask ROM 0000H-07FFH (2048 × 8 bits) Static RAM EEPROM TM µPD75F4264Note Flash memory 0000H-0FFFH (4096 × 8 bits) 000H-07FH (128 × 4 bits) None 400H-43FH (32 × 8 bits) CPU 75XL CPU General-purpose register (4 bits × 8 or 8 bits × 4 ) × 4 banks Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (system clock: at 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (system clock: at 6.0-MHz operation) I/O port CMOS input 4 (on-chip pull-up resistor can be connected by mask option) CMOS input/output 9 (on-chip pull-up resistor can be specified by software) Total 13 System clock oscillator Ceramic/crystal oscillator Boot time after reset 217/fX or 2 15/fX (selected by mask option) Timer 4 channels • 8-bit timer counter: 3 channels (can be used for 16-bit timer counter) 215/fX • Basic interval timer/watchdog timer: 1 channel A/D converter None • 8-bit resolution × 2 channels (successive approximation register) • Operable VDD = 1.8 V or higher Programmable threshold port None 2 channels Vectored interrupt External: 1, Internal: 4 External: 1, Internal: 5 Test input External: 1 (key return reset function provided) Supply voltage VDD = 1.8 to 6.0 V Operating ambient temperature TA = –40 to +85 ˚C Package • 20-pin plastic SOP (300 mil, 1.27-mm pitch) • 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Note Under development 58 • 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754202, 754202(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD754202. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler OS PC-9800 Series IBM PC/AT and compatible machines Supply media MS-DOSTM 3.5-inch 2HD µS5A13RA75X Ver. 3.30 to 5-inch 2HD µS5A10RA75X 3.5-inch 2HC µS7B13RA75X 5-inch 2HC µS7B10RA75X Ver. 6.2 TM Device file Part number (product name) Host machine Note Refer to “OS for IBM PC” Part number (product name) Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Supply media 3.5-inch 2HD µS5A13DF754202 5-inch 2HD µS5A10DF754202 3.5-inch 2HC µS7B13DF754202 5-inch 2HC µS7B10DF754202 Ver. 6.2Note IBM PC/AT and compatible machines Note Refer to “OS for IBM PC” Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remark Operations of the assembler and device file are guaranteed only on the above host machines and OSs. 59 µPD754202, 754202(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD754202. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing a µPD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE-75001-R In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing a µPD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R which are sold separately must be used with the IE-75001-R. By connecting with the host machine, efficient debugging can be made. IE-75300-R-EM Emulation board for evaluating the application systems that use a µPD754202. It must be used with the IE-75000-R or IE-75001-R. EP-754144GS-R Emulation probe for the µPD754202. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 20-pin flexible boards EV-9500GS-20 (compatible with 20-pin plastic shrink SOP) and EV-9501GS-20 (compatible with 20-pin plastic SOP) which facilitate connection to a target system. EV-9500GS-20 EV-9501GS-20 Software IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Supply media Part number (product name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Ver. 6.2Note 2 IBM PC/AT and compatible machines Notes 1. 2. Refer to “OS for IBM PC” Maintenance product Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. 60 µPD754202, 754202(A) OS for IBM PC The following IBM PC OS’s are supported. OS PC DOS Version TM Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to J6.2/VNote IBM DOS TM J5.02/V Note Note Only English mode is supported. Caution Ver. 5.0 or later have the task swap function, but it cannot be used for this software. 61 µPD754202, 754202(A) APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English µPD754202, 754202(A) Data Sheet U12181J This document µPD754202 User’s Manual U11132J U11132E 75XL Series Selection Guide U10453J U10453E Development tool related documents Document Number Document Name Japanese Hardware Software English IE-75000-R/IE-75001-R User’s Manual EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-754144GS-R User’s Manual U10695J U10695E Operation EEU-731 EEU-1346 Language EEU-730 EEU-1363 RA75X Assembler Package User’s Manual Other related documents Document Number Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Devices C11893J Microcomputer Product Series Guide U11416J – MEI-1202 – Caution These documents are subject to change without notice. Be sure to read the latest documents for designing, etc. 62 µPD754202, 754202(A) [MEMO] 63 µPD754202, 754202(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 64 µPD754202, 754202(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 65 µPD754202, 754202(A) EEPROM is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2