DATA SHEET MOS INTEGRATED CIRCUIT µPD75036 4 BIT SINGLE-CHIP MICROCOMPUTER The µPD75036 is a 75X series 4-bit single-chip microcomputer. The µPD75036 is an expanded version of the µPD75028. It has ROM and RAM with a larger capacity. The minimum instruction execution time of the µPD75036 is 0.95 µs. In addition to this high-speed capability, it contains an A/D converter and furnishes high-performance functions such as the serial bus interface (SBI) function that follows the NEC standard format, providing powerful features and high cost performance. A built-in PROM product, µPD75P036, is also available. The µPD75P036 is suitable for small-scale production or experimental production in system development. The following user’s manual describes the details of functions. Be sure to read it before design. µPD75028 User’s Manual: IEU-694 FEATURES • Variable instruction execution time advantageous to high-speed operation and power-saving: • 0.95 µs, 1.91 µs, or 15.3 µs (at 4.19 MHz when the main system selected) • 122 µs (at 32.768 kHz when the subsystem clock selected) • • • • Program memory (ROM) capacity: 16256 × 8 bits Data memory (RAM) capacity: 1024 × 4 bits Built-in A/D converter (8-bit resolution, successive approximation): 8 channels Powerful timer function: 4 channels • Usable for 16-bit integral A/D conversion and PWM output • Built-in NEC standard serial bus interface (SBI) • Very low-power clock operation allowed (5 µA TYP. at 3 V) APPLICATIONS Electric household appliances, air cooling/heating apparatus, cameras, and electronic measuring instruments ORDERING INFORMATION Part number Package Quality grade µPD75036CW-××× 64-pin plastic shrink DIP (750 mil) Standard µPD75036GC-×××-AB8 64-pin plastic QFP ( Standard 14 mm) Remark ××× is a mask ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-3115 (O.D. No. IC-8611) Date Published October 1993 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1993 µPD75036 FUNCTIONS Function Item Instruction execution time • 0.95, 1.91, 15.3 µs (Main system clock : 4.19 MHz operation) • 122 µs (Subsystem clock : 32.768 kHz operation) On-chip memory ROM 16256 × 8 bits RAM 1024 × 4 bits General register • 4-bit manipulation : 8 • 8-bit manipulation : 4 I/O port 48 4 channels Timer 12 CMOS input pins 24 CMOS I/O pins 12 N-ch open-drain I/O pins • On-chip pull-up resistor by software : 27 • On-chip pull-down resistor by software: 4 • Direct LED driving: 4 • Withstand voltage is 10 V • On-chip pull-up resistor by mask option • Direct LED driving: 4 • Timer/event counter • Basic interval timer : Can be used as watchdog timer • Clock timer : Buzzer output enabled Multifunction timer : Can be used as timer, free-running timer or counter for integration A/D converter, or for PWM output Serial interface • Three-wire serial I/O mode • Two-wire serial I/O mode • SBI mode Bit sequential buffer 16 bits Clock output Φ, fX/23, fX/24 , fX/26 (Main system clock: 4.19 MHz operation) A/D converter • 8-bit resolution × 8 channels (successive-approximation) • Capable of low-voltage operation: VDD = 2.7 to 6.0 V Vectored interrupt External : 3, Internal : 4 Test input External : 1, Internal : 1 System clock oscillator • Ceramic/crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode ★ Operating temperature range –40 to +85 °C ★ Operating voltage 2.7 to 6.0 V Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP ( 14 mm) 2 µPD75036 CONTENTS 1. PIN CONFIGURATIONS (TOP VIEW) ....................................................................................... 4 2. BLOCK DIAGRAM ...................................................................................................................... 6 3. PIN FUNCTIONS ....................................................................................................................... 7 3.1 PORT PINS ..................................................................................................................................... 7 3.2 NON-PORT PINS ........................................................................................................................... 9 3.3 PIN INPUT/OUTPUT CIRCUITS .................................................................................................. 11 3.4 MASK OPTION SELECTION ....................................................................................................... 13 3.5 CONNECTION OF UNUSED PINS ................................................................................................ 14 4. ARCHITECTURE AND MEMORY MAP OF THE µPD75036 .................................................. 15 5. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 17 5.1 PORTS ............................................................................................................................................. 17 5.2 CLOCK GENERATOR .................................................................................................................... 17 5.3 CLOCK OUTPUT CIRCUIT ............................................................................................................ 19 5.4 BASIC INTERVAL TIMER .............................................................................................................. 20 5.5 CLOCK TIMER ................................................................................................................................ 21 5.6 TIMER/EVENT COUNTER .............................................................................................................. 22 5.7 SERIAL INTERFACE ...................................................................................................................... 24 5.8 A/D CONVERTER .......................................................................................................................... 26 5.9 MULTIFUNCTION TIMER (MFT) .................................................................................................... 27 6. INTERRUPT FUNCTION ............................................................................................................ 29 7. STANDBY FUNCTION ................................................................................................................ 31 8. RESET FUNCTION ..................................................................................................................... 31 9. INSTRUCTION SET ................................................................................................................... 32 10. ELECTRICAL CHARACTERISTICS .......................................................................................... 39 11. PACKAGE DIMENSIONS ........................................................................................................... 52 APPENDIX A DEVELOPMENT TOOLS ........................................................................................ 54 APPENDIX B RELATED DOCUMENTS ........................................................................................ 55 3 µPD75036 1. PIN CONFIGURATIONS (TOP VIEW) • 64-pin plastic shrink DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µ PD75036CW-××× SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 IC XT1 XT2 VDD AVDD AVREF+ AVREF– AN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TI0/P13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P30 P31 P32 P33 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 • 64-pin plastic QFP 64 63 62 6160 59 58 57 56 55 54 53 52 51 50 4948 1 47 2 46 3 45 4 44 5 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 313233 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 IC XT1 XT2 VDD AVDD AVREF+ AVREF– AN7 µ PD75036GC-×××-AB8 P43 P42 P41 P40 P33 P32 P31 P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 IC: Internally connected (Should be directly connected to VDD) 4 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6 µPD75036 Pin names : Port 0 : Port 0 P10-13 : Port 1 : Port 1 P20-23 : Port 2 : Port 2 P30-33 : Port 3 : Port 3 P40-43 : Port 4 : Port 4 P50-53 : Port 5 : Port 5 P60-63 : Port 6 : Port 6 P70-73 : Port 7 : Port 7 P80-83 : Port 8 : Port 8 P90-93 : Port 9 : Port 9 P100-103: Port 10 : Port 10 P110-113: Port 11 : Port 11 KR0-7 : Key Return : Key interrupt input SCK : Serial Clock : Serial clock I/0 SI : Serial Input : Serial data input SO : Serial Output : Serial data output SB0, 1 : RESET : Serial Bus 0, 1 : Serial bus I/O Reset Input : Reset input TI0 : Timer Input 0 : External event pulse input PTO0 : Programmable Timer Output 0 : Timer/event counter output BUZ : Buzzer Clock : Arbitrary frequency output PCL : Programmable Clock : Clock output INT0, 1, 4: External Vectored Interrupt 0, 1, 4 : External vectored interrupt input INT2 : External Test Input 2 : External test input X1, 2 : Main System Clock Oscillation 1, 2 : Main system clock oscillation pin XT1, 2 : Subsystem Clock Oscillation 1, 2 : Subsystem clock oscillation pin MAR : Reference Integration Control MAI : Integration Control MAZ : Autozero Control MAT : External Comparate Timing Input PPO : : Reverse integration signal output MFT A/D : Integration signal output : Autozero signal output mode : External comparator signal input P00-03 MFT A/D mode Programmable Pulse Output ... MFT timer mode : Pulse output ... MFT timer mode AN0-7 : Analog Input 0-7 : Analog input AVREF+ : Analog Reference (+) : Analog reference voltage (+) input AVREF- : Analog Reference (-) : Analog reference voltage (-) input AVDD : Analog VDD : A/D converter power supply input AVSS : Analog VSS : A/D converter GND input VDD : Positive Power Supply : Main power supply pin VSS : Ground : GND potential pin Remark MFT: Multifunction timer 5 INTBT TI0/P13 PTO0/P20 Timer/ counter 0 Program counter P00-P03 Port 1 P10-P13 Port 2 P20-P23 Port 3 P30-P33 Port 4 P40-P43 Port 5 P50-P53 Port 6 P60-P63 Port 7 P70-P73 Port 8 P80-P83 Port 9 P90-P93 Port 10 P100-P103 SP CY ALU INTT0 Bank SI/SB1/P03 SO/SB0/P02 Port 0 Serial interface 2. BLOCK DIAGRAM 6 Bit sequential buffer Basic interval timer SCK/P01 INTCS1 INT0/P10 General register INT1/P11 INT2/P12 Interrupt control ROM program memory 16256 × 8 bits INT4/P00 KR0-KR3/P60-P63 KR4-KR7/P70-P73 BUZ/P23 Decode and control Watch timer RAM data memory 1024 × 4 bits INTW AVDD AVREF+ AVREF– AVSS A/D converter AN0-AN3/P110-P113 AN4-AN7 fX/2N MAR/P100 MAI/P101 MAZ/P102 Multi function timer Clock output control Clock divider CPU clock Φ Clock generator Sub Main Stand by control Port 11 MAT/P103 PCL/P22 INTMFT XT1 XT2 X1 X2 VDD VSS RESET P110-P113 µPD75036 PPO/P21 µPD75036 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Input/ output Shared pin P00 Input INT4 P01 I/O SCK P02 I/O SO/SB0 FF-B P03 I/O SI/SB1 MF-C P10 Input INT0 P11 INT1 P12 INT2 P13 TI0 P20 I/O PTO0 P21 PPO P22 PCL P23 BUZ P30Note 2 I/O – P31Note 2 – P32Note 2 – P33Note 2 – Function 4-bit input port (PORT0). For P01 - P03, pull-up resistors can be provided by software in units of 3 bits. 8-bit I/O When reset I/O circuit typeNote 1 × Input B FF-A × Input BF-C 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. × Input E-B Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. × Input E-B With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. P40 - P43 Note 2 I/O – N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided for each bit (mask option). This opendrain port has a withstand voltage of 10 V. High level (when pullup resistors are provided) or high impedance M P50 - P53 Note 2 I/O – N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided for each bit (mask option). This open-drain port has a withstand voltage of 10 V. High level (when pullup resistors are provided) or high impedance M Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. Can directly drive the LED. 7 µPD75036 3.1 PORT PINS (2/2) Pin Input/ output Shared pin P60 I/O KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 4-bit I/O port (PORT7). Pull-up resistors can be provided by software in units of 4 bits. Input FF-A Input E-B Input E-D 4-bit I/O port (PORT8). Pull-up resistors can be provided by software in units of 4 bits. P90-P93 I/O – 4-bit I/O port (PORT9). Pull-down resistors can be provided by software in units of 4 bits. P100Note 2 I/O MAR P101Note 2 MAI P102Note 2 MAZ P103Note 2 MAT N-ch open-drain 4-bit I/O port (PORT10). A pull-up resistor can be provided bit by bit (mask option). This open-drain port has a withstand voltage of 10 V. AN0 4-bit input port (PORT11) AN1 P112 AN2 P113 AN3 Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. Can directly drive the LED. I/O circuit typeNote 1 FF-A – P111 When reset Input I/O Input 8-bit I/O Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. P80-P83 P110 8 Function × × High level (when pull-up resistors are provided) or high impedance Input M Y-A µPD75036 3.2 NON-PORT PINS (1/2) Pin Input/ output Shared pin TI0 Input P13 Input for receiving external event pulse signal for timer/event counter PTO0 I/O P20 Timer/event counter output Input E-B PCL I/O P22 Clock output Input E-B BUZ I/O P23 Output for arbitrary frequency output (for buzzer output or system clock trimming) Input E-B SCK I/O P01 Serial clock I/O Input FF-A SO/SB0 I/O P02 Serial data output Serial bus I/O Input FF-B SI/SB1 I/O P03 Serial data input Serial bus I/O Input MF-C INT4 Input P00 Edge detection vectored interrupt input (either rising edge or falling edge detection) – B INT0 Input P10 Edge detection vectored interrupt input (detection edge selectable) P11 INT1 Function I/O circuit typeNote 1 – BF-C – BF-C – BF-C Note 3 INT2 Input P12 KR0 - KR3 I/O P60 - P63 Parallel falling edge detection testable input Input FF-A KR4-KR7 I/O P70 - P73 Parallel falling edge detection testable input Input FF-A MAR I/O P100 Reverse integration signal output Note 4 M MAI I/O P101 Integration signal output Note 4 M MAZ I/O P102 Autozero signal output Note 4 M MAT I/O P103 Comparator input Note 4 M PPO I/O P21 Timer pulse output Input E-B AN0 - AN3 Input 8-bit analog input Input Y-A AN4 - AN7 AVREF+ Input AV REF- Input AVDD AV SS Edge detection testable input (rising edge detection) Note 2 When reset In MFT integral A/D converter mode In MFT timer mode P110 - P113 For A /D converter – only – Note 3 Y Reference voltage input (on AVDD side) – Z-A – Reference voltage input (on AVSS side) – Z-A – – Operating power supply – – – – Reference GND potential – – Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. Clock synchronous 3. Asynchronous 4. High level (when pull-up resistors are provided) or high impedance Remark MFT: Multifunction Timer 9 µPD75036 3.2 NON-PORT PINS (2/2) Pin Input/ output Shared pin Function When reset I/O circuit typeNote X1, X2 Input – Crystal/ceramic connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. – – XT1, XT2 Input – Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2, XT1 can be used as a 1-bit input (test). – – RESET Input – System reset input – B IC – – Internally connected. (To be directly connected to VDD) – – VDD – – Positive power supply – – VSS – – GND potential – – Note The circle ( 10 ) indicates the Schmitt trigger input. µPD75036 3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each µPD75036 pin is shown below in a simplified manner. (1/3) Type A (For type E-B) Type D (For type E-B, F-A) VDD VDD Data P-ch P-ch OUT IN N-ch CMOS input buffer Type B Output disable N-ch Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis Type B-C Type E-D Data VDD Output disable IN/OUT Type D P.U.R. P-ch P.U.R. enable Type A P.D.R. enable N-ch IN P.D.R. P.U.R.: Pull-Up Resistor P.D.R.: Pull-Down Resistor 11 µPD75036 (2/3) Type F-A Type M-C VDD VDD P.U.R. P.U.R. P.U.R. enable P.U.R. enable P-ch P-ch IN/OUT Data IN/OUT Type D Data Output disable N-ch Output disable Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type F-B Type Y VDD P.U.R. AVDD P.U.R. enable Output disable (P) P-ch IN VDD P-ch N-ch + Sampling C AVDD P-ch – IN/OUT Data AVSS Output disable AVSS N-ch Output disable (N) Reference voltage (from voltage tap of serial resistor string) Input enable P.U.R.: Pull-Up Resistor Type M Type Y-A VDD IN P.U.R. enable (Mask option) IN/OUT Input buffer Data Output disable N-ch (Can sustain +10 V) IN AVDD P-ch N-ch AVDD Sampling C + – AVSS AVSS Middle-voltage input buffer (Can sustain +10 V) P.U.R.: Pull-Up Resistor 12 Reference voltage (from voltage tap of serial resistor string) µPD75036 (3/3) Type Z-A AVREF+ Reference voltage AVREF- 3.4 MASK OPTION SELECTION The following mask options are available for selection for each pin. Mask option Pin name P40 - P43, P50 - P53, P100-P103 1 Pull-up resistor provided (specifiable bit by bit) 2 Pull-up resistor not provided (specifiable bit by bit) XT1, XT2 1 Feedback resistor provided (if a subsystem clock is used) 2 Feedback resistor not provided (if a subsystem clock is not used) 13 µPD75036 ★ 3.5 CONNECTION OF UNUSED PINS Pin Recommended connection P00/INT4 To be connected to VSS P01/SCK To be connected to VSS or VDD P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 To be connected to VSS P13/TI0 P20/PTO0 P21/PPO Input state : To be connected to VSS or VDD Output state:To be open P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 To be connected to VSS or VDD AN4-AN7 AVREF+ To be connected to VSS AVREFAVSS 14 AVDD To be connected to VDD XT1 To be connected to VSS or VDD XT2 To be open IC To be directly connected to VDD µPD75036 4. ARCHITECTURE AND MEMORY MAP OF THE µPD75036 The µPD75036 has two architectural features: • Bank configuration of data memory : Static RAM (1024 words × 4 bits) Peripheral hardware (128 × 4 bits) • Memory mapped I/O Fig. 4-1 and 4-2 show the memory maps for the µPD75036. Fig. 4-1 Program Memory Map Address 0000H 0002H 0004H 0006H 0008H 000AH 7 6 5 MBE 0 0 MBE MBE MBE MBE MBE 0 0 0 0 0 0 0 0 0 0 0 Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 6 bits) CALLF !faddr (low-order 8 bits) instruction (high-order 6 bits) entry address (low-order 8 bits) INTT0 start address 000CH MBE 0 0 INTMFT start address INTMFT start address CALL !addr instruction subroutine entry address BR !addr instruction branch address BRCB !caddr instruction branch address BR $addr instruction relative branch address (-15 to -1, +2 to +16) Branch address and subroutine entry address specified in GETI instruction 0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3F7FH Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the low-order 8 bits of the PC changed. 15 µPD75036 Fig. 4-2 Data Memory Map Data memory General register area Stack area Memory bank 000H (8 × 4) 007H 0 008H 256 × 4 0FFH 100H Data area Static RAM (1024 × 4) 256 × 4 1 256 × 4 2 256 × 4 3 1FFH 200H 2FFH 300H 3FFH Not contained F80H Peripheral hardware area 128 × 4 FFFH 16 15 µPD75036 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS The µPD75036 has the following three types of I/O port: • 12 CMOS input ports (Ports 0, 1, and 11) • 24 CMOS I/O ports (Ports 2, 3, 6, 7, 8, and 9) • 12 N-ch open-drain I/O ports (Ports 4, 5, and 10) Total: 48 ports Table 5-1 Port (symbol) Function Functions of Ports Operation and feature Remarks PORT0 PORT1 4-bit input Allows input and test at any time regardless of the operation modes of dual function pins. Also used as SO/SB0, SI/ SB1, SCK, INT0-INT2, INT4, and TI0 pins. PORT3Note 4-bit I/O Allows input or output mode setting in units of one bit. Port 6 is also used as KR0KR3 pins. Allows input or output mode setting in units of four bits. Ports 6 and 7 make a pair, allowing data I/O in units of eight bits. Port 2 is also used as PTO0, PPO, PCL, and BUZ pins. 4-bit I/O (N-ch open-drain, withstand voltage: 10 V) Allows input or output mode setting in units of four bits. Ports 4 and 5 make a pair, allowing data I/O in units of eight bits. Use of an internal pull-up registor can be maskprogrammed in units of one bit. PORT8 PORT9 4-bit I/O Allows input or output mode setting in units of four bits. PORT11 4-bit input Port for 4-bit input PORT6 PORT2 PORT7 PORT4Note PORT5Note PORT10Note Also used as KR4-KR7 pins. Port 10 is also used as MAR, MAI, MAZ, and MAT pins. Port 11 is also used as AN0AN3 pins. Note Ports 3, 4, 5 and 10 can directly drive an LED. 5.2 CLOCK GENERATOR Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock or subsystem clock can be selected. The instruction execution time is variable. • 0.95 µ s, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz) • 122 µ s (subsystem clock: 32.768 kHz) 17 µPD75036 Fig. 5-1 ★ Block Diagram of the Clock Generator XT1 VDD XT2 Subsystem clock generator fXT Main system clock generator fX Clock timer X1 Multifunction timers Basic interval timer (BT) Timer/event counter Serial interface Clock timer A/D converter (successive approximation) • INT0 noise eliminator • Clock output circuit • • • • • • VDD X2 1/2 to 1/4096 Frequency divider 1/2 WM.3 SCC 1/16 Selector Oscillator disable signal Frequency divider SCC3 Selector 1/4 Internal bus SCC0 PCC PCC0 Φ •CPU •INT0 noise eliminator •Clock output circuit PCC1 4 HALT F/F HALTNote STOPNote PCC2 S PCC3 R PCC2, PCC3 clear signal STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. 18 fX : Main system clock frequency fXT : Subsystem clock frequency Φ = CPU clock PCC: Processor clock control register SCC: System clock control register One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction. See Chapter 10 for details of tCY. µPD75036 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying clock pulses to a peripheral LSI device. Fig. 5-2 Configuration of the Clock Output Circuit From the clock generator Φ f X/2 Output buffer 3 Selector f X/24 f X/2 PCL/P22 6 PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output. 19 µPD75036 5.4 BASIC INTERVAL TIMER The basic interval timer provides the following functions: • Interval timer operation that generates a reference time interrupt • Application of watchdog timer for detecting program crashes • Selection of a wait time for releasing the standby mode, and counting • Reading the count value Fig. 5-3 Configuration of the Basic Interval Timer From the clock generator Clear signal Clear signal fX/25 Set signal 7 fX/2 Basic interval timer (8-bit frequency divider circuit) MPX 9 BT interrupt request flag fX/2 12 BT fX/2 3 BTM3 SET1Note BTM2 BTM1 Wait release signal for standby release BTM0 BTM 8 4 Internal bus Note Instruction execution 20 IRQBT Vectored interrupt request signal µPD75036 5.5 CLOCK TIMER The µPD75036 contains one channel for a clock timer. The clock timer provides the following functions: • The clock timer sets the test flag (IRQW) every 0.5 seconds. The standby mode can be released with IRQW. • Either the main system clock or subsystem clock can produce 0.5-second intervals. • The fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program debugging and testing. • An arbitrary frequency (2.048, 4.096, or 32.768 kHz) can be output to the P23/BUZ pin, so that it can be used for sounding the buzzer and system clock frequency trimming. • The frequency divider can be cleared, so the clock can start from zero seconds. Fig. 5-4 Block Diagram of the Clock Timer fW 27 fX From 128 the (32.768 kHz) clock gener- fXT ator (32.768 kHz) (256 Hz: 3.91 ms) fW fW (32.768 kHz) 214 Selector INTW IRQW set signal Selector Frequency divider 2 Hz 0.5 sec 4 kHz 2 kHz Clear signal Selector Output buffer P23/BUZ WM WM7 PORT2.3 WM6 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch Bit 2 of PMGB Port 2 input/ output mode Bit test instruction Internal bus The values in parentheses indicates are for fX = 4.194304 MHz and fXT = 32.768 kHz 21 µPD75036 5.6 TIMER/EVENT COUNTER The µ PD75036 contains one channel of timer/event counter. The timer/event counter provides the following functions: • Programmable interval timer operation • Output of a square wave at a given frequency to the PTO0 pin • Event counter operation • Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin • Supply of serial shift clock signal to a serial interface circuit • Function of reading the state of counting 22 Fig. 5-5 Block Diagram of the Timer/Event Counter Internal bus 8 Note SET1 TM0 8 8 TOE0 TMOD0 TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 TO enable flag Modulo register (8) PORT2.0 P20 output latch signal Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 Match Comparator (8) 8 TOUT F/F P20/PTO0 Reset Input buffer Output buffer T0 P13/ TI0 INTT0 From the clock generator Count register (8) CP MPX Clear signal IRQT0 set signal Timer operation start signal (See Fig. 5-1.) RESET IRQT0 clear signal Note Instruction execution µPD75036 23 µPD75036 5.7 SERIAL INTERFACE The µPD75036 has three modes. • Three-wire serial I/O mode (The first bit is switchable between MSB and LSB.) • Two-wire serial I/O mode (The first bit is MSB.) • SBI mode (The first bit is MSB.) The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of I/O devices. The two-wire serial I/O mode and SBI mode enable communication with two or more devices. 24 Fig. 5-6 Block Diagram of the Serial Interface Internal bus 8/4 CSIM Bit test Bit manipulation 8 8 Bit test 8 SBIC Slave address register (SVA) (8) Match signal Address comparator RELT CMDT (8) P03/SI/SB1 SET CLR SO latch D Q BSYE (8) ACKE Shift register (SIO) ACKT Selector P02/SO/SB0 Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD INTCSI P01/SCK Serial clock counter P01 output latch Serial clock control circuit INTCSI control circuit IRQCSI set signal Serial clock selector External SCK 25 µPD75036 fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter) µPD75036 5.8 A/D CONVERTER The µ PD75036 contains an 8-bit resolution analog/digital (A/D) converter that has eight analog input channels (AN0 - AN7). The A /D converter employs the successive-approximation method. Fig. 5-7 Configuration of the A/D Converter Internal bus 8 0 ADM6 ADM5 ADM4 SOC EOC 0 0 ADM 8 AN0/P110 Control circuit AN1/P111 Sample and hold circuit AN2/P112 + AN3/P113 Multiplexer SA register (8) – AN4 Comparator AN5 AN6 8 AN7 Tap decoder AVREF+ R/2 AVREF-- 26 R R Series resistor string R R/2 µPD75036 5.9 MULTIFUNCTION TIMER (MFT) The µPD75036 contains one multifunction timer (MFT). The MFT has four operation modes. Each mode provides the following functions: • 8-bit timer mode • Operates as a programmable interval timer. • Outputs a square wave of an arbitrary frequency on the PPO pin. • PWM output mode • Outputs a 6-bit, 7-bit, or 8-bit precision PWM signal on the PPO pin. • 16-bit free-running timer mode • Operates as an interval timer that generates an interrupt at specified time intervals. • Usable as a one-shot timer. • Integral A/D converter modes • Outputs a control signal for a 16-bit integral A/D converter. • Allows a resolution to be selected from 13 bits, 14 bits, 15 bits, and 16 bits. 27 28 Fig. 5-8 Block Diagram of the Multifunction Timer Internal bus 8 8 Clear signal Output latch P21 P100 P101 P102 Selector MAT/ P103 Edge selector Input/output mode register Count register (MFTL) MAZ/P102 Modulo latch Integral A/D control circuit MAI/P101 8 MAR/P100 fX/2 fX/23 fX/25 fX/27 Comparator PPO/P21 Match MFT F/F MPX 8 fX/29 Overflow fX/211 Selector Count register (MFTH) Tap selector INTMFT IRQMFT set signal Interrupt selector RESET Selector IRQMFT clear signal MFTM7 MFTM6 MFTM5 MFTM4 MFTM3 MFTM2 MFTM1 MFTM0 MFTM 1/4 Internal bus µPD75036 8 MFTC3 MFTC2 MFTC1 MFTC0 MFTC µPD75036 6. INTERRUPT FUNCTION The µPD75036 has nine vectored interrupt sources and provides multiple interrupts by software control. It also has two types of edge detected testable input pins. The interrupt control circuitry of the µPD75036 has the following features: • Vectored interrupts are controlled by the hardware. Whether to accept an interrupt is controlled by an interrupt flag (IE×××) and interrupt master enable flag (IME). • An interrupt start address can be freely set. • An interrupt request flag (IRQ×××) can be tested. (Whether an interrupt has occurred can be checked by software.) • A standby mode can be released. (What interrupt source to release can be selected using an interrupt enable flag.) 29 30 Fig. 6-1 Block Diagram of Interrupt Control Circuit Internal bus 2 2 2 IM2 IM1 IM0 IME IST0 Interrupt enable flag (IE×××) INT BT INT4/ P00 INT0/ P10 INT1/ P11 Note Both-edge detection circuit Edge detection circuit Edge detection circuit IRQ1 INTT0 IRQT0 INTW Rising edge detection circuit KR0/P60 Falling edge detection circuit KR7/P73 IRQ0 IRQCSI INTMFT Selector VRQn IRQ4 INTCSI INT2/ P12 Decoder IRQBT Priority control circuit Vector table address generator IRQMFT IRQW IRQ2 Note Noise eliminator µPD75036 IM2 Standby release signal µPD75036 7. STANDBY FUNCTION To reduce the power consumption of the system waiting for a program input, the µPD75036 has two standby modes STOP and HALT modes. Table 7-1 Standby Modes and Operation Status HALT mode STOP mode STOP instruction HALT instruction System clock at setting This mode can be set only when the main system clock is used. This mode can be set when either the main system clock or subsystem clock is used. Clock generator Only the main system clock is stopped. Only CPU clock Φ is stopped (with oscillation continued). Basic interval timer Operation is stopped. Operation is possible only when the main system clock is oscillated. (Sets IRQBT at reference time intervals) Serial interface Operation is possible only when external Operation is possible only when external SCK input is selected for the serial clock or the main system clock is oscillated. Operation status Instruction for setting SCK input is selected for the serial clock. Timer/event counter Operation is possible only when TI0 pin input is selected for the count clock. Operation is possible only when TI0 pin input is selected for the count count clock or the main system clock is oscillated. Clock timer Operation is possible when fXT is selected for the count clock. Operation is possible. A/D converter Operation is stopped. Operation is possible.Note Multifunction timer Operation is stopped. Operation is possible.Note External interrupt INT1, INT2, and INT4 are enabled. INT0 is disabled. CPU Operation is stopped. Release signal Interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or RESET input Interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or RESET input Note Operation is possible only when the main system clock operates. 8. RESET FUNCTION The µPD75036 is reset by RESET signal input. 31 µPD75036 9. INSTRUCTION SET (1) Operand identifier and its descriptive method The operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions (refer to RA75X Assembler Package User's Manual, Language (EEU-1363) for details). For descriptions in which alternatives exist, one element should be selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as they are. For immediate data, the appropriate numerical values or labels should be described. Identifier Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 XA, BC, DE, HL BC, DE, HL BC, DE rpa rpa1 HL, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label memNote bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H - FBFH, FF0H - FFFH immediate data or label FC0H - FFFH immediate data or label addr caddr faddr 0000H - 3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H - 7FH immediate data (however, bit 0 = 0) or label PORTn PORT0 - PORT11 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW, IEMFT MB0, MB1, MB2, MB3, MB15 IE××× MBn Note Only even address can be specified for mem when processing 8-bit data. (2) Symbol definitions in operation description 32 A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register µPD75036 X : X register XA : Pair register (XA); 8-bit accumulator BC : Pair register (BC) DE : Pair register (DE) HL : Pair register (HL) PC : Program counter SP : Stack pointer CY : Carry flag; Bit accumulator PSW : Program status word MBE : Memory bank enable flag PORTn : Port n (n = 0 to 11) IME : Interrupt master enable flag IE××× : Interrupt enable flag MBS : Memory bank selection register PCC : Processor clock control register . : Address bit delimiter (××) : Contents addressed by ×× ××H : Hexadecimal data (3) Explanation of the symbols in the addressing area field *1 MB = MBE•MBS (MBS = 0, 1, 2, 3, or 15) *2 MB = 0 *3 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15) *4 MB = 15, fmem = FB0H-FBFH or FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-3F7FH *7 addr = (Current PC) - 15 to (Current PC) - 1 or (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H-0FFFH (PC13,12 = 00B) or 1000H-1FFFH (PC13,12 = 01B) or 2000H-2FFFH (PC13,12 = 10B) or 3000H-3F7FH (PC13,12 = 11B) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Data memory addressing Program memory addressing Remarks 1. MB indicates an accessible memory bank. 2. For *2, MB is always 0 irrespective of MBE and MBS. 3. For *4 and *5, MB is always 15 irrespective of MBE and MBS. 4. *6 to *10 indicate each addressable area. 33 µPD75036 (4) Description of machine cycle column S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes as follows: • When no skip is performed··················································································································· S=0 • When a 1-byte or 2-byte instruction is skipped ··················································································· S=1 • When a 3-byte instruction (BR !addr, CALL !addr instruction) is skipped ········································· S=2 Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equivalent to one CPU clock Φ cycle (tCY). Therefore, the length of the machine cycle can be selected from three different lengths by the PCC setting. 34 µPD75036 Group Transfer Mnemonic Operand MachinBytes ing cycle Operation Addressing area Skip condition A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String A HL, #n8 2 2 HL ← n8 String B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg1 2 2 A ← reg1 XA, rp 2 2 XA ← rp reg1, A 2 2 reg1 ← A rp1, XA 2 2 rp1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp 2 2 XA ↔ rp XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM A, #n4 1 1+S A ← A + n4 A, @HL 1 1+S A ← A + (HL) *1 ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1 SUBS A, @HL 1 1+S A ← A – (HL) *1 SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1 AND A, #n4 2 2 A, @HL 1 1 A, #n4 2 2 A, @HL 1 1 A, #n4 2 2 A, @HL 1 1 MOV XCH Table reference MOVT Arithmetic ADDS OR XOR ∧ n4 A ← A ∧ (HL) A ← A ∨ n4 A ← A ∨ (HL) A ← A ∨ n4 A ← A ∨ (HL) String A carry carry borrow A←A *1 *1 *1 35 µPD75036 Group Accumulator manipulation Increment/ decrement Comparison Carry flag manipulation Memory bit manipulation Mnemonic MachinBytes ing cycle Operation Addressing area Skip condition RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A INCS reg 1 1+S reg ← reg + 1 @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 DECS reg 1 1+S reg ← reg – 1 reg = FH SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) A, reg 2 2+S Skip if A = reg SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY SET1 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem. @L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1 *5 @H+mem.bit 2 2 (H + mem3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem. @L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0 *5 @H+mem.bit 2 2 (H + mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem. @L 2 2+S Skip if (pmem7-2 + L 3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem. @L 2 2+S Skip if (pmem7-2 + L 3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 0 *1 (@H + mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem. @L 2 2+S Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY, pmem. @L 2 2 CY, @H+mem.bit 2 2 CY, fmem.bit 2 2 CY, pmem. @L 2 2 CY, @H+mem.bit 2 2 CLR1 SKT SKF SKTCLR AND1 OR1 36 Operand reg = 0 A = reg CY = 1 Skip if CY = 1 ∧ (fmem.bit) CY ← CY ∧ (pmem7-2 + L 3-2.bit(L1-0 )) CY ← CY ∧ (H + mem3-0.bit) CY ← CY ∨ (fmem.bit) CY ← CY ∨ (pmem7-2 + L 3-2.bit(L1-0 )) CY ← CY ∨ (H + mem3-0.bit) CY ← CY *4 *5 *1 *4 *5 *1 µPD75036 Group Mnemonic MachinBytes ing cycle Addressing area Operation ∨ (fmem.bit) CY ← CY ∨ (pmem7-2 + L3-2.bit(L1-0)) CY ← CY ∨ (H + mem3-0.bit) CY ← CY CY, fmem.bit 2 2 CY, pmem.@L 2 2 CY, @H+mem.bit 2 2 addr – – PC13-0 ← addr (Appropriate instructions are selected from BR !addr, BRCB !caddr, and BR $addr by the assembler.) *6 !addr 3 3 PC13-0 ← addr *6 $addr 1 2 PC13-0 ← addr *7 BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8 CALL !addr 3 3 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 (SP – 3) ← MBE, 0, PC13, PC12 PC13-0 ← addr, SP ← SP – 4 *6 CALLF !faddr 2 2 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 *9 Memory bit manipulation XOR1 Branch BR Subroutine stack control Operand Skip condition *4 *5 *1 (SP–3) ← MBE, 0, PC13, PC12 PC13-0 ← 000, faddr, SP ← SP – 4 1 3 RETS 1 3+S RETI 1 3 MBE, 0, PC13, PC12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6 rp 1 1 (SP – 1)(SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← 0, SP ← SP – 2 rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), SP ← SP + 2 2 2 IME ← 1 2 2 IE××× ← 1 2 2 IME ← 0 IE××× 2 2 IExxx ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6) PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORTn+1 ,PORTn ← XA (n = 4, 6) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation PUSH POP Interrupt control EI IE××× DI Input/ output INNote OUTNote CPU control MBE, 0, PC13, PC12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4 RET MBE, 0, PC13, PC12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4, then skip unconditionally Unconditional (n = 0 - 11) (n = 2 - 10) 37 µPD75036 Group Special Mnemonic Operand MachinBytes ing cycle Operation SEL MBn 2 2 MBS ← n (n = 0, 1, 2, 3, or 15) GETI taddr 1 3 • For the TBR instruction PC 13-0 ← (taddr)5-0 + (taddr + 1) ---------------------------------------------• For the TCALL instruction (SP – 4)(SP – 1)(SP – 2) ← PC11-0 (SP – 3) ← MBE, 0, PC13, PC12 PC 13-0 ← (taddr)5-0 + (taddr + 1) SP ← SP – 4 ---------------------------------------------• For other than the TBR and TCALL instruction (taddr) (taddr + 1) is executed. Addressing area Skip condition *10 ----------------- ----------------Depends on the reference instruction Caution When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and 15, respectively. 38 µPD75036 10. ELECTRICAL CHARACTERISTICS ★ ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) Parameter Symbol Conditions Rated value Unit –0.3 to +7.0 V Supply voltage VDD Input voltage VI1 Ports other than ports 4, 5, and 10 –0.3 to VDD + 0.3 V VI2 Ports 4, 5, Built-in pull-up resistor and 10 Open drain –0.3 to VDD + 0.3 V –0.3 to +11 V –0.3 to VDD + 0.3 V 1 pin –10 mA All pins –30 mA Peak value 30 mA rms 15 mA 1 pin of ports other than ports 0, 3, 4 and 5 Peak value 20 mA 5 mA Total of all pins of ports 3 to 9 and 11 Peak value 170 mA rms 120 mA Total of all pins of ports 0, 2, and 10 Peak value 30 mA rms 20 mA Output voltage VO High-level output current IOH Low-level output current IOLNote 1 pin of parts 0, 3, 4, and 5 rms Operating temperature Topt –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Note Calculate rms with [rms] = [peak value] × √duty. 39 µPD75036 CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) Resonator Recommended constant Ceramic resonator X1 X2 VDD C2 C1 VDD Crystal resonator X1 C1 X2 VDD C2 VDD External clock X1 X2 Parameter Conditions Min. Max. Unit 5.0 MHz 4 ms 5.0Note 3 MHz 10 ms 30 ms 1.0 5.0 MHz 100 500 ns Typ. 1.0 Oscillator frequency (f X) Note 1 Oscillation settling time Note 2 1.0 Oscillator frequency (fX) Note 1 Oscillation settling time 4.19 VDD = 4.5 to 6.0 V Note 2 X1 input frequency (fX) Note 1 X1 input µ PD74HCU04 high/low level width (tXH, tXL) Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released. 3. When 4.19 MHz < fX ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When PCC = 0011, one machine cycle falls short of 0.95 µs, the minimum value for the standard. Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. 40 µPD75036 CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) Recommended constant Resonator Crystal resonator XT1 XT2 VDD R C3 C4 VDD External clock XT1 Notes 1. 2. Parameter Conditions Oscillator frequency (fXT) Note 1 Oscillation settling time Min. Typ. Max. Unit 32 32.768 35 kHz 1.0 2 s 10 s VDD = 4.5 to 6.0 V Note 2 XT2 XT1 input frequency (fXT ) Note 1 32 100 kHz XT1 input high/low level width (tXTH, tXTL ) 5 15 µs The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min. of the oscillation voltage range. Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. CAPACITANCE (Ta = 25 °C, VDD = 0 V) Parameter Symbol Input capacitance CI Output capacitance CO I/O capacitance CIO Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. Unit 15 pF 15 pF 15 pF 41 µPD75036 DC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input leakage current Symbol Min. Max. Unit 0.7VDD VDD V Ports 0, 1, 6, and 7 and RESET 0.8VDD VDD V Ports 4, 5, Built-in pull-up resistor and 10 Open drain 0.7VDD VDD V 0.7VDD 10 V VDD – 0.5 VDD V Conditions VIH1 Ports 2, 3, 8, 9, and 11 VIH2 VIH3 Typ. VIH4 X1, X2, XT1, and XT2 VIL1 Ports 2 to 5 and 8 to 11 0 0.3VDD V VIL2 Ports 0, 1, 6, and 7 and RESET 0 0.2VDD V VIL3 X1, X2, XT1, and XT2 0 0.4 V VOH VDD = 4.5 to 6.0 V, IOH = –1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V VOL ILIH1 Ports 3, 4, VDD = 4.5 to 6.0 V, IOL = 15 mA and 5 0.5 2.0 V VDD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2VDD V SB0 and SB1 Open drain Pull-up resistor: 1 kΩ or more VI = VDD Other than X1, X2, XT1, and XT2 3 µA X1, X2, XT1, and XT2 20 µA ILIH2 ILIH3 VI = 10 V Ports 4, 5, and 10 (open drain) 20 µA Low-level input leakage current ILIL1 VI = 0 V Other than X1, X2, XT1, and XT2 –3 µA X1, X2, XT1, and XT2 –20 µA High-level output leakage current ILOH1 VO = VDD 3 µA ILOH2 VO = 10 V Ports 4, 5, and 10 (open drain) 20 µA Low-level output leakage current ILOL VO = 0 V –3 µA Built-in pull-up resistor RU1 Ports 0, 1, 2, 3, 6, 7, and 8 (excl. P00) VI = 0 V VDD = 5.0 V ±10 % 15 80 kΩ VDD = 3.0 V ±10 % 30 300 kΩ Ports 4, 5, and 10 VO = VDD – 2.0 V VDD = 5.0 V ±10 % 15 70 kΩ VDD = 3.0 V ±10 % 10 60 kΩ Port 9 VDD = 5.0 V ±10 % 10 70 kΩ VI = VDD VDD = 3.0 V ±10 % 10 60 kΩ ILIL2 RU2 Built-in pull-down resistor 42 RD Other than ports 4, 5, and 10 40 40 40 µPD75036 Parameter Power supply currentNote 1 Symbol IDD1 IDD2 IDD3 IDD4 IDD5 Typ. Max. VDD = 5 V ±10 %Note 3 4.19 crystal resonance C1 = C2 = 22 pF 3.2 10 mA VDD = 3 V ±10 %Note 4 0.25 0.75 mA HALT mode VDD = 5 V ±10 % 500 1500 µA Unit VDD = 3 V ±10 % 150 450 µA 32.768 kHzNote 5 crystal HALT mode resonance VDD = 3 V ±10 % 15 45 µA VDD = 3 V ±10 % 5 15 µA XT1 = 0 V STOP mode VDD = 5 V ±10 % 0.5 20 µA 0.1 10 µA 0.1 5 µA VDD = 3 V ±10 % Notes 1. Min. Conditions MHzNote 2 Ta = 25 ˚C This current excludes the current which flows through the built-in pull-up resistors. 2. This value applies also when the subsystem clock oscillates. 3. Value when the processor clock control register (PCC) is set to 0011 and the µPD75036 is operated in the high-speed mode 4. Value when the PCC is set to 0000 and the µPD75036 is operated in the low-speed mode 5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. 43 µPD75036 AC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.0 to 6.0 V) Parameter Symbol CPU clock cycle time (minimum instruction execution time = 1 machine cycle)Note 1 tCY TI0 input frequency fTI VDD = 4.5 to 6.0 V Operated by subsystem clock pulse Max. Unit 0.95 64 µs 3.8 64 µs 125 µs 0 1 MHz 0 275 kHz 122 0.48 µs 1.8 µs Note 2 µs INT1, INT2, and INT4 10 µs KR0 to KR7 10 µs 10 µs tTIH, tTIL VDD = 4.5 to 6.0 V Interrupt input high/low level width tINTH, tINTL INT0 tRSL Notes 1. The cycle time of the CPU clock (Φ) tCY vs VDD depends on the connected resonator (Main system clock in operation) 70 frequency, the system clock control reg- 64 60 ister (SCC), and the processor clock control register (PCC). The figure on the right side shows the 6 cycle time tCY characteristics for the supply 5 voltage VDD during main system clock 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt Operation guaranteed range 4 Cycle time tCY [ µs] operation. mode register (IM0). Typ. 114 VDD = 4.5 to 6.0 V TI0 input high/low level width RESET low level width Min. Conditions Operated by main system clock pulse 3 2 1 0.5 0 1 2 3 4 5 Power supply voltage VDD [V] 44 6 µPD75036 Serial transfer operation Two-wire and three-wire serial I/O modes (SCK ... Internal clock output): Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V Min. Typ. Max. Unit 1600 ns 3800 ns tKCY1/2 – 50 ns SCK high/low level width tKL1 tKH1 tKCY1/2 – 150 ns SI setup time tSIK1 150 ns tKSI1 400 ns (referred to SCK↑) SI hold time (referred to SCK↑) Delay time from tKSO1 SCK↓ to SO output RL = 1 kΩ, CL = 100 pFNote VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns Max. Unit Two-wire and three-wire serial I/O modes (SCK ... External clock input): Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 4.5 to 6.0 V Min. Typ. 800 ns 3200 ns 400 ns SCK high/low level width tKL2 tKH2 1600 ns SI setup time tSIK2 100 ns tKSI2 400 ns VDD = 4.5 to 6.0 V (referred to SCK↑) SI hold time (referred to SCK↑) Delay time from SCK↓ to SO output tKSO2 RL = 1 kΩ, CL = 100 pFNote VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. 45 µPD75036 SBI mode (SCK ... Internal clock output (master)): Parameter Conditions Symbol Min. Typ. Max. Unit 1600 ns 3800 ns tKCY3/2 - 50 ns tKH3 tKCY3/2 - 150 ns SB0/SB1 setup time (referred to SCK↑) tSIK3 150 ns SB0/SB1 hold time (referred to SCK↑) tKSI3 tKCY3/2 ns Delay time from SCK↓ to SB0/SB1 output tKSO3 From SCK↑ to SB0/SB1↓ tKSB tKCY3 ns From SB0/SB1↓ to SCK↓ tSBK tKCY3 ns SB0/SB1 low level width tSBL tKCY3 ns SB0/SB1 high level width tSBH tKCY3 ns SCK cycle time SCK high/low level width tKCY3 tKL3 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pFNote VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns SBI mode (SCK ... External clock input (slave)): Parameter Symbol Min. Typ. Max. Unit 800 ns 3200 ns 400 ns tKH4 1600 ns SB0/SB1 setup time (referred to SCK↑) tSIK4 100 ns SB0/SB1 hold time (referred to SCK↑) tKSI4 tKCY4/2 ns Delay time from SCK↓ to SB0/SB1 output tKSO4 From SCK↑ to SB0/SB1↓ tKSB tKCY4 ns From SB0/SB1↓ to SCK↓ tSBK tKCY4 ns SB0/SB1 low level width tSBL tKCY4 ns SB0/SB1 high level width tSBH tKCY4 ns SCK cycle time SCK high/low level width tKCY4 Conditions tKL4 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pFNote VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns Note RL and CL are the resistance and capacitance of the SB0/SB1 output line load respectively. 46 µPD75036 A/D converter (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Conditions Symbol Resolution Absolute accuracyNote 1 2.5 V ≤ AVREF ≤ VDD Min. Typ. 8 8 -10 ≤ Ta ≤ +85˚C Max. Unit 8 bit ±1.5 LSB ±2.0 -40 ≤ Ta < -10˚C Conversion timeNote 2 tCONV 168/fX µs Sampling timeNote 3 tSAMP 44/fX µs Analog input voltage VIAN AVREF- AVREF+ V Analog power supply voltage AVDD 2.5 VDD V Reference input voltageNote4 AVREF+ 2.5 V ≤ (AVREF +) – (AVREF -) 2.5 AVDD V Reference output voltageNote 4 AVREF- 2.5 V ≤ (AVREF +) – (AVREF -) 0 1.0 V Analog input impedance AV REF current RAN 1000 AI REF 1.0 MΩ 2.0 mA Notes 1. Absolute accuracy excluding quantization error (±1/2 LSB) 2. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1) (40.1 µ s: fX = 4.19 MHz) 3. Time from the execution of a conversion start instruction till the end of sampling (10.5 µ s: f X = 4.19 MHz) 4. The value resulting from subtracting (AVREF–) from (AVREF+) must be greater than or equal to 2.5 V. 47 µPD75036 AC Timing Measurement Points (Excluding (X1 and XT1 Inputs) 0.8VDD 0.8VDD Measurement point 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VDD – 0.5 V X1 input 0.4 V 1/fXT tXTL tXTH VDD – 0.5 V XT1 input 0.4 V TI0 Timing 1/fTI tTIL TI0 48 tTIH µPD75036 Serial Transfer Timing Three-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 Input data SI tKSO1 Output data SO Two-wire serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0 and SB1 tKSO2 49 µPD75036 Serial Transfer Timing Bus release signal transfer: tKCY3 tKCY4 tKL3 tKL4 tKH3 tKH4 SCK tKSB tSBL tSBH tSIK3 tSIK4 tSBK SB0 and SB1 tKSO3 tKSO4 Command signal transfer: tKCY3 tKCY4 tKL3 tKL4 tKH3 tKH4 SCK tKSB tSIK3 tSIK4 tSBK SB0 and SB1 tKSO3 tKSO4 Interrupt Input Timing tINTL INT0, INT1, INT2 and INT4 KR0-KR7 RESET Input Timing tRSL RESET 50 tINTH tKSI3 tKSI4 tKSI3 tKSI4 µPD75036 DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 °C) Parameter Symbol Data hold supply voltage VDDDR Data hold supply currentNote 1 IDDDR Release signal setting time tSREL Oscillation settling timeNote 2 tWAIT Notes 1. 2. 3. Conditions Min. Typ. Max. Unit 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Release by RESET 217/f X ms Release by interrupt request Note 3 ms Excluding the current which flows through the built-in pull-up resistors CPU operation stop time for preventing unstable operation at the beginning of oscillation This value depends on the settings of the basic interval timer mode register (BTM) shown below. Wait time (Values at fx = 4.19 MHz in parentheses) BTM3 BTM2 BTM1 BTM0 — 0 0 0 220/fX (approx. 250 ms) — 0 1 1 217/fX (approx. 31.3 ms) — 1 0 1 215/fX (approx. 7.82 ms) — 1 1 1 213/fX (approx. 1.95 ms) Data Hold Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operation mode STOP mode Data hold mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode Operation mode STOP mode Data hold mode VDD VDDDR tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 51 µPD75036 11. PACKAGE DIMENSIONS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE M B C ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010+0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 52 µPD75036 64 PIN PLASTIC QFP ( 14) A B 33 32 48 49 F Q 5°±5° S D C detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. 53 µPD75036 APPENDIX A DEVELOPMENT TOOLS The following development tools are provided for developing systems including the µPD75036: IE-75000-RNote 1 In-circuit emulator for the 75X series Hardware IE-75001-R Software ★ IE-75000-R-EMNote 2 Emulation board for the IE-75000-R and IE-75001-R EP-75028CW-R Emulation probe for the µPD75036CW Emulation probe for the µPD75036GC. A 64-pin conversion socket, the EV-9200GC-64, is EV-9200GC-64 attached to the probe. EP-75028GC-R PG-1500 PROM programmer PA-75P036CW PROM programmer adapter for the µPD75P036CW. Connected to the PG-1500. PA-75P036GC PROM programmer adapter for the µPD75P036GC. Connected to the PG-1500. IE control program Host machine • PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) • IBM PC/AT TM series (PC DOSTM Ver. 3.10) PG-1500 controller RA75X relocatable assembler Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A. 54 µPD75036 ★ APPENDIX B RELATED DOCUMENTS Documents related to the device Document No. Document Name User’s manual IEU-1294 Application note IEM-1294 75X series selection guide IF-1027 Documents related to development tools Document No. Software Hardware Document Name IE-75000-R User’s Manual EEU-1297 IE-75001-R User’s Manual EEU-1416 IE-75000-R-EM User’s Manual EEU-1294 EP-75028CW-R User’s Manual EEU-1314 EP-75028GC-R User’s Manual EEU-1306 PG-1500 User’s Manual EEU-1335 RA75X Assembler Package User’s Manual Operation EEU-1346 Language EEU-1363 PG-1500 Controller User’s Manual EEU-1291 Other documents Document Name Document No. PACKAGE MANUAL IEI-1213 SMD SURFACE MOUNT TECHNOLOGY MANUAL IEI-1207 QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES IEI-1209 NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM IEI-1203 ELECTROSTATIC DISCHARGE (ESD) TEST IEI-1201 GUIDE TO QUALITY ASSURANCE FOR SEMICONDUCTOR DEVICES MEI-1202 Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 55 µPD75036 [MEMO] 56 µPD75036 Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. 57 µPD75036 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 68