SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 D D D D D D D D, DGV, OR PW PACKAGE (TOP VIEW) Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTL+ Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTL+ Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Polarity Control Selects True or Complementary Outputs Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages OEBY Y1 Y2 VCC A1 A2 OEAB ERC 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 BIAS VCC GND B1 GND B2 GND VREF T/C description The SN74GTLP1394 is a high-drive 2-bit 3-wire bus transceiver that provides LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels and is especially designed to work with the Texas Instruments TSB14C01A 1394 Backplane Physical-Layer Controller. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output edge control (OEC). Improved GTLP OEC circuits minimize bus settling time and have been designed and tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The AC specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTL+, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTL or GTL+ levels. The A inputs, Y outputs, and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW D SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 description (continued) When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74GTLP1394 is characterized for operation from –40°C to 85°C. functional description The output-enable (OEAB) input controls the activity of the B port. When OEAB is low, the B-port outputs are active. When OEAB is high, the B-port outputs are disabled. Separate input and output pins allow the device to transmit and receive simultaneously. The OEBY input controls the Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are disabled. PRODUCT PREVIEW The polarity-control (T/C) input is provided to select polarity of data transmission in both directions. When T/C is high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary, and A data goes to the B bus and B data goes to the Y bus. Function Tables OUTPUT ENABLE INPUTS T/C OEAB OEBY OPERATION OR FUNCTION X H H Z Isolation H L H A data to B bus True driver H H L B data to Y bus True driver H L L A data to B bus, B data to Y bus True transceiver L L H A data to B bus Inverted driver L H L B data to Y bus Inverted driver L L L A data to B bus, B data to Y bus Inverted transceiver OUTPUT EDGE-RATE CONTROL (ERC) INPUT ERC 2 MODE LOGIC LEVEL NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE L GND Slow H VCC Fast POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 logic diagram (positive logic) 10 VREF 8 ERC 7 OEAB T/C 9 1 OEBY Y1 A2 Y2 5 14 B1 2 12 6 B2 3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port, ERC, and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1): Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Note 1): Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Current into any output in the low state, IO: Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PRODUCT PREVIEW A1 SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 recommended operating conditions (see Notes 4 through 6) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTL+ 0.87 1 1.1 B port VTT VCC Except B port B port ERC Except B port and ERC VREF+0.05 VCC–0.6 Low-level input voltage ERC PRODUCT PREVIEW Except B port and ERC IIK IOH Input clamp current IOL Low level output current Low-level High-level output current Y Y V V VCC GND VREF–0.05 0.6 V 0.8 –18 mA –24 mA 24 B port V 2 B port VIL V 100 mA TA Operating free-air temperature –40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range for GTL+ (unless otherwise noted) TEST CONDITIONS VIK VOH VCC = 3.15 V, VCC = 3.15 V to 3.45 V, Y II = –18 mA IOH = –100 µA IOH = –12 mA VCC = 3 15 V 3.15 VCC = 3 3.15 15 V VOL B port II‡ ICC VCC = 3.15 V VCC = 3.45 V, A and control inputs inp ts VCC = 3 3.45 45 V Y or B port VCC = 3.45 V, IO = 0, VI (A or control input) = VCC or GND VI (B port) = VTT or GND Control inputs Co Y UNIT –1.2 V V IOL = 100 µA IOL = 12 mA 0.2 IOL = 24 mA IOL = 10 mA 0.5 0.4 0.2 V 0.4 0.55 VI = 0 to 1.5 V VI = 0 to VCC ±5 VI = 5.5 V Outputs high ±5 20 Outputs low 20 Outputs disabled 20 ±5 VCC = 3.45 V, One A or control input at VCC – 0.6 V, Other A or control inputs at VCC or GND A MAX 2 IOL = 64 mA IOL = 100 mA B port ∆ICC§ Ci TYP† VCC–0.2 2.4 IOH = –24 mA VCC = 3.15 V to 3.45 V, Y MIN 1.5 µA mA mA VI = 3.15 3 15 V or 0 pF VO = 3.15 V or 0 pF Cio B port VO = 1.5 V or 0 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameter II includes the off-state output leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF live-insertion specifications for A and Y over recommended operating free-air temperature range PARAMETER TEST CONDITIONS Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, MIN VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 VO = 0.5 V to 3 V, OE = 0 MAX UNIT 100 µA ±100 µA ±100 µA live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V ICC (BIAS VCC) VO IO VCC = 3.15 V to 3.45 V VCC = 0, VCC = 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, VO = 0.5 V to 1.5 V, 15 V to 3 45 V BIAS VCC = 3 3.15 3.45 V, MIN VI or VO = 0 to 1.5 V OE = 0 OE = 0 15V VO (B port) = 0 to 1.5 BIAS VCC = 3.3 V 0.95 BIAS VCC = 3.15 V to 3.45 V, POST OFFICE BOX 655303 VO (B port) = 0.6 V • DALLAS, TEXAS 75265 –1 MAX UNIT 100 µA ±100 µA ±100 µA 5 mA 10 µA 1.05 V µA 5 PRODUCT PREVIEW PARAMETER SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† MAX UNIT Fast A PRODUCT PREVIEW TYP‡ Slow B tpd d MIN Slow Y Fast ns Slow T/C B ten tdis OEAB B Slow ns ten tdis OEAB B Fast ns Fast tr Rise time,, B outputs (0.6 V to 1.3 V) Slow tf Fall time,, B outputs (1.3 V to 0.6 V) Slow Fast Fast ns ns B tpd ten tdis T/C OEBY Y ns Y ns † Slow (ERC = GND) and Fast (ERC = VCC) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open 12.5 Ω From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω S1 Open 6V GND LOAD CIRCUIT FOR Y OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A to B port) 1V 0V tPLH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH Output 1.5 V tPZL 1.5 V 1V Input 3V Output Control 1.5 V VOL PRODUCT PREVIEW 1V Output Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to Y) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≤ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS This data sheet is specified for and tested to the lump load shown in Figure 1. However, the designer probably uses this GTLP device in a distributed load like that shown in Figure 2, in which actual B-port backplane switching characteristics are different. Therefore, the device is modeled as shown in Figure 3, which very closely matches the results obtained using Figure 2. Switching characteristics based on Figure 3 more closely match actual backplane design requirements. RTT .25” .875” .625” .875” .625” .625” RTT VTT VTT .25” .625” 1.5 V Conn. PRODUCT PREVIEW 1” Conn. 1” Conn. Conn. 1” Rcvr 1” Rcvr From Output Under Test Rcvr LL = 21 nH Test Point CL = 13 pF Drvr Slot 1 14 Ω Slot 2 Slot 15 Slot 16 Figure 2. Test Backplane Model Figure 3. Distributed-Load Circuit for B Outputs switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† MAX UNIT Fast A Slow Y Fast ns Slow T/C B ten tdis OEAB B Slow ns ten tdis OEAB B Fast ns Fast tr Rise time,, B outputs (0.6 V to 1.3 V) Slow tf Fall time, B outputs (1.3 V to 0.6 V) Slow Fast Fast † Slow (ERC = GND) and Fast (ERC = VCC) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 8 TYP‡ Slow B tpd d MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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