CEM3252 N-Channel Enhancement Mode Field Effect Transistor FEATURES 5 30V, 7.5A, RDS(ON) = 28mΩ @VGS = 10V. RDS(ON) = 40mΩ @VGS = 4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. D D D D 8 7 6 5 1 S 2 S 3 S 4 G Surface mount Package. SO-8 1 ABSOLUTE MAXIMUM RATINGS Parameter TA = 25 C unless otherwise noted Symbol Limit Drain-Source Voltage VDS 30 Units V Gate-Source Voltage VGS ±20 V ID 7.5 A IDM 25 A PD 2.5 W TJ,Tstg -55 to 150 C Units Drain Current-Continuous Drain Current-Pulsed a Maximum Power Dissipation Operating and Store Temperature Range Thermal Characteristics Symbol Limit Thermal Resistance, Junction-to-Ambient b Parameter RθJA 50 C/W Thermal Resistance, Junction-to-Case RθJC 25 C/W Rev 2. 2009.Nov http://www.cetsemi.com Details are subject to change without notice . 1 CEM3252 Electrical Characteristics Parameter TA = 25 C unless otherwise noted Symbol Test Condition Min Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 30 Zero Gate Voltage Drain Current IDSS Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse Typ Max Units VDS = 30V, VGS = 0V 1 µA IGSSF VGS = 20V, VDS = 0V 100 nA IGSSR VGS = -20V, VDS = 0V -100 nA Off Characteristics V On Characteristics Gate Threshold Voltage Static Drain-Source On-Resistance VGS(th) RDS(on) VGS = VDS, ID = 250µA 3.0 V VGS = 10V, ID = 7A 1.0 22 28 mΩ VGS = 4.5V, ID = 3.5A 30 40 mΩ Dynamic Characteristics d Forward Transconductance gFS Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VDS = 15V, ID = 7A VDS = 15V, VGS = 0V, f = 1.0 MHz 4 S 610 pF 145 pF 95 pF Switching Characteristics d Turn-On Delay Time td(on) Turn-On Rise Time tr Turn-Off Delay Time td(off) VDD = 15V, ID = 7A, VGS = 10V, RGEN = 3Ω 9 20 ns 3 8 ns 24 50 ns Turn-Off Fall Time tf 4 10 ns Total Gate Charge Qg 12.3 16 nC Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS = 15V, ID = 7A, VGS = 10V 1.5 nC 2.5 nC Drain-Source Diode Characteristics and Maximun Ratings Drain-Source Diode Forward Current b IS Drain-Source Diode Forward Voltage c VSD VGS = 0V, IS = 2.3A Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. . e.RθJA is the sum of junction-to-case-ambient thermal resistance where the case tmermal reference is defined as the solder mounting surface of the drain pins. RθJc is guaranteed by design while RθJA is determined by the user's board design 1. 50CW when mounted on a 1in 2 pad of 2 oz copper 2. 105CW when mounted on a 0.4in 2 pad of 2 oz copper Scale 1 : 1 on letter size paper f.Pulse Test : Pluse Width < 300us,Duty cycle <2% 2 3. 125CW when mounted on a minimun pad 2.3 A 1.2 V CEM3252 40 20 VGS=5V ID, Drain Current (A) ID, Drain Current (A) VGS=10,9,8,7,6V 30 20 VGS=4V 10 15 10 25 C 5 0 0 0 1 2 3 4 5 1.5 RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) 3.5 4.0 4.5 Figure 2. Transfer Characteristics 600 450 300 Coss 150 Crss 0 0 3 6 9 12 15 2.2 1.9 ID=7A VGS=10V 1.6 1.3 1.0 0.7 0.4 -100 -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature( C) Figure 3. Capacitance Figure 4. On-Resistance Variation with Temperature VDS=VGS IS, Source-drain current (A) VTH, Normalized Gate-Source Threshold Voltage 3.0 Figure 1. Output Characteristics Ciss ID=250µA 1.1 1.0 0.9 0.8 0.7 0.6 -50 2.5 VGS, Gate-to-Source Voltage (V) 750 1.2 2.0 VDS, Drain-to-Source Voltage (V) 900 1.3 -55 C TJ=125 C VGS=3V VGS=0V 10 10 10 -25 0 25 50 75 100 125 150 1 0 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) VSD, Body Diode Forward Voltage (V) Figure 5. Gate Threshold Variation with Temperature Figure 6. Body Diode Forward Voltage Variation with Source Current 3 10 10 V =15V DS ID=7A 6 4 2 0 0 2 RDS(ON)Limit 8 ID, Drain Current (A) VGS, Gate to Source Voltage (V) CEM3252 3 6 9 12 10 10 10 10 15 1ms 10ms 100ms 1s DC 1 0 -1 TA=25 C TJ=150 C Single Pulse -2 10 -2 10 -1 10 0 10 1 10 Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Figure 7. Gate Charge Figure 8. Maximum Safe Operating Area VDD t on RL V IN D td(off) tf 90% 90% VOUT VOUT VGS RGEN toff tr td(on) 10% INVERTED 10% G 90% S VIN 50% 50% 10% PULSE WIDTH Figure 10. Switching Waveforms Figure 9. Switching Test Circuit r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 10 PDM 0.02 0.01 -2 t1 t2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJA (t) 4. Duty Cycle, D=t1/t2 Single Pulse 10 -3 10 -4 10 -3 10 -2 10 -1 10 0 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4 10 1 10 2 2