TI SN65HVD233DR

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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
FEATURES
D Bus-Pin Fault Protection Exceeds ±36 V
D Bus-Pin ESD Protection Exceeds 16-kV HBM
D GIFT/ICT Compliant (SN65HVD234)
D Compatible With ISO 11898
D Signaling Rates(1) up to 1 Mbps
D Extended –7-V to 12-V Common-Mode Range
D High-Input Impedance Allows for 120 Nodes
D LVTTL I/Os Are 5-V Tolerant
D Adjustable Driver Transition Times for
D
D
D
Improved Signal Quality
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode . . . 200-µA
Typical
Low-Current Sleep Mode . . . 50-nA Typical
(SN65HVD234)
D Thermal Shutdown Protection
D Power-Up / Down Glitch-Free Bus Inputs and
D
D
D
Outputs
− High Input Impedance With Low VCC
− Monolithic Output During Power Cycling
Loopback for Diagnostic Functions Available
(SN65HVD233)
Loopback for Autobaud Function Available
(SN65HVD235)
DeviceNet Vendor ID #806
APPLICATIONS
D CAN Data Bus
D Industrial Automation
− DeviceNet Data Buses
− Smart Distributed Systems (SDS)
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
D
D
D ISO 11783 Standard Data Bus Interface
DESCRIPTION
The SN65HVD233, SN65HVD234, and SN65HVD235
are used in applications employing the controller area
network (CAN) serial communication physical layer in
accordance with the ISO 11898 standard. As a CAN
transceiver, each provides transmit and receive capability
between the differential CAN bus and a CAN controller,
with signaling rates up to 1 Mbps.
Designed for operation in especially harsh environments,
the devices feature cross-wire, overvoltage and loss of
ground protection to ±36 V, with overtemperature
protection and common-mode transient protection of
±100 V. These devices operate over a –7-V to 12-V
common-mode range with a maximum of 60 nodes on a
bus.
SN65HVD233
FUNCTIONAL BLOCK DIAGRAM
RS 8
1
D
R
LBK
7
6
CANH
CANL
4
5
SN65HVD234
FUNCTIONAL BLOCK DIAGRAM
8
RS
D 1
5
EN
7
CANH
6 CANL
4
R
SN65HVD235
FUNCTIONAL BLOCK DIAGRAM
AB 5
8
RS
1
D
R
7
6
CANH
CANL
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
DeviceNet is a trademark of Open DeviceNet Vendor Association.
Other trademarks are the property of their respective owners.
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Copyright  2002−2003, Texas Instruments Incorporated
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DESCRIPTION (Continued)
If the common-mode range is restricted to the ISO-11898 Standard range of –2 V to 7 V, up to 120 nodes may be connected
on a bus. These transceivers interface the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications.
The RS, pin 8 of the SN65HVD233, SN65HVD234, and SN65HVD235 provides for three modes of operation: high-speed,
slope control, or low-power standby mode. The high-speed mode of operation is selected by connecting pin 8 directly to
ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall
slope. The rise and fall slope can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional
to the pin’s output current. Slope control is implemented with a resistor value of 10 kΩ to achieve a slew rate of ≈15 V/us
and a value of 100 kΩ to achieve ≈ 2.0 V/µs slew rate. For more information about slope control, refer to the application
information section.
The SN65HVD233, SN65HVD234, and SN65HVD235 enter a low-current standby mode during which the driver is
switched off and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses
this low-current standby mode when it needs to transmit to the bus.
A logic high on the loopback LBK pin 5 of the SN65HVD233 places the bus output and bus input in a high-impedance state.
The remaining circuit remains active and available for driver to receiver loopback, self-diagnostic node functions without
disturbing the bus.
The SN65HVD234 enters an ultralow-current sleep mode in which both the driver and receiver circuits are deactivated if
a low logic level is applied to EN pin 5. The device remains in this sleep mode until the circuit is reactivated by applying
a high logic level to pin 5.
The AB pin 5 of the SN65HVD235 implements a bus listen-only loopback feature which allows the local node controller
to synchronize its baud rate with that of the CAN bus. In autobaud mode, the driver’s bus output is placed in a
high-impedance state while the receiver’s bus input remains active. For more information on the autobaud mode, refer to
the application information section.
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
LOW POWER MODE
SLOPE
CONTROL
DIAGNOSTIC
LOOPBACK
AUTOBAUD
LOOPBACK
SN65HVD233D
200-µA standby mode
Adjustable
Yes
No
SN65HVD234D
200-µA standby mode or 50-nA sleep mode
Adjustable
No
No
PART NUMBER
SN65HVD235D
200-µA standby mode
Adjustable
No
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
Yes
ORDERING INFORMATION
PACKAGE (D)
MARKED AS
SN65HVD233D
SN65HVD233DR(1)
VP233
SN65HVD234D
SN65HVD234DR(1)
VP234
SN65HVD235D
SN65HVD235DR(1)
VP235
(1) R suffix indicated tape and reel
POWER DISSIPATION RATINGS
PACKAGE
CIRCUIT
BOARD
TA ≤ 25°C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
D
Low-K
596.6 mW
5.7 mW/°C
255.7 mW
28.4 mW
D
High-K
1076.9 mW
10.3 mW/°C
461.5 mW
51.3 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range unless otherwise noted
PARAMETER
VALUE
Supply voltage range, VCC
−0.3 V to 7 V
Voltage range at any bus terminal (CANH or CANL)
−36 V to 36 V
Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7)
Input voltage range, VI (D, R, RS, EN, LBK, AB)
−0.5 V to 7 V
Receiver output current, IO
Electrostatic discharge
Electrostatic discharge
−100 V to 100 V
−10 mA to 10 mA
Human Body Model(3)
Human Body Model(3)
CANH, CANL and GND
16 kV
All pins
3 kV
Charged-Device Mode(4)
All pins
1 kV
Continuous total power dissipation
See Dissipation Rating Table
Operating junction temperature, TJ
150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114−A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
3
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
Supply voltage, VCC
3
Voltage at any bus terminal (separately or common mode)
−7
12
UNIT
3.6
High−level input voltage, VIH
D, EN, AB, LBK
2
5.5
Low−level input voltage, VIL
D, EN, AB, LBK
0
0.8
V
Differential input voltage, VID
−6
Resistance from RS to ground
0
100
kΩ
0.75 VCC
5.5
V
Input Voltage at RS for standby, VI(Rs)
High−level output current, IOH
Low−level output current, IOL
Operating junction temperature, TJ
Operating free−air temperature(1), TA
6
Driver
−50
Receiver
−10
mA
Driver
50
Receiver
10
mA
150
°C
125
°C
MIN TYP(1)
MAX
UNIT
2.45
VCC
1.25
V
HVD233, HVD234, HVD235
HVD233, HVD234, HVD235
−40
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
CANH
D at 0 V, RS at 0 V, See Figures 1 and 2
VO(D)
Bus output voltage (Dominant)
VO
Bus output voltage (Recessive)
VOD(D)
Differential output voltage (Dominant)
VOD
Differential output voltage (Recessive)
VOC(pp)
IIH
Peak-to-peak common-mode output voltage
See Figure 10
High-level input current; D, EN, LBK, AB
D at 2 V
IIL
Low-level input current; D, EN, LBK, AB
D at 0.8 V
CANL
0.5
CANH
IOS
Short−circuit output current
CO
IIRs(s)
Output capacitance
CANL
RS input current for standby
Standby
Supply current
Dominant
Recessive
(1) All typical values are at 25°C and with a 3.3 V supply.
4
V
2.3
D at 0 V, RS at 0 V, See Figures 1 and 2
D at 0 V, RS at 0 V, See Figures 2 and 3
1.5
2
3
1.2
2
3
D at 3 V, RS at 0 V, See Figures 1 and 2
−120
12
D at 3 V, RS at 0 V, No Load
−0.5
0.05
V
−30
30
µA
−30
30
µA
1
VCANH = −7 V, CANL Open, See Figure 15
VCANH = 12 V, CANL Open, See Figure 15
−250
VCANL = −7 V, CANH Open, See Figure 15
VCANL = 12 V, CANH Open, See Figure 15
−1
V
mV
V
1
mA
250
See receiver input capacitance
Sleep
ICC
2.3
D at 3 V, RS at 0 V, See Figures 1 and 2
RS at 0.75 VCC
EN at 0 V, D at VCC, RS at 0 V or VCC
RS at VCC, D at VCC, AB at 0 V, LBK at 0 V,
EN at VCC
D at 0 V, No Load, AB at 0 V, LBK at 0 V,
RS at 0 V, EN at VCC
D at VCC, No Load, AB at 0 V,
LBK at 0 V, RS at 0 V, EN at VCC
µA
−10
0.05
2
200
600
µA
6
mA
6
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
TYP(1)
MAX
RS at 0 V, See Figure 4
RS with 10 kΩ to ground, See Figure 4
35
85
70
125
RS with 100 kΩ to ground, See Figure 4
RS at 0 V, See Figure 4
500
870
70
120
RS with 10 kΩ to ground, See Figure 4
RS with 100 kΩ to ground, See Figure 4
130
180
870
1200
RS at 0 V, See Figure 4
RS with 10 kΩ to ground, See Figure 4
35
RS with 100 kΩ to ground, See Figure 4
370
PARAMETER
tPLH
tPHL
tsk(p)
TEST CONDITIONS
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tPHL – tPLH|)
tr
tf
Differential output signal rise time
tr
tf
Differential output signal rise time
tr
tf
Differential output signal rise time
ten(s)
ten(z)
Enable time from standby to dominant
RS at 0 V, See Figure 4
Differential output signal fall time
RS with 10 kΩ to ground, See Figure 4
Differential output signal fall time
RS with 100 kΩ to ground, See Figure 4
Differential output signal fall time
MIN
60
ns
ns
ns
20
70
20
70
30
135
30
135
350
1400
350
1400
See Figures 8 and 9
Enable time from sleep to dominant
UNIT
0.6
1.5
1
5
TYP(1)
MAX
750
900
ns
ns
ns
µss
(1) All typical values are at 25°C and with a 3.3 V supply.
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
VIT−
Positive-going input threshold voltage
Vhys
VOH
Hysteresis voltage (VIT+ − VIT−)
VOL
Low-level output voltage
II
Negative-going input threshold voltage
High-level output voltage
AB at 0 V, LBK at 0 V, EN at VCC, See Table 1
500
IO = −4 mA, See Figure 6
IO = 4 mA, See Figure 6
2.4
650
CANH or CANL at 12 V
150
500
200
600
−610
−150
−450
−130
CANH or CANL at −7 V
CANH or CANL at −7 V,
VCC at 0 V
Other bus pin at 0 V,
D at 3 V, AB at 0 V,
LBK at 0 V, RS at 0 V,
EN at VCC
Input capacitance (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5V,
D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC
40
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5V,
D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC
20
RID
RIN
Differential input resistance
ICC
Supply current
mV
0.4
CI
Input resistance (CANH or CANL)
UNIT
100
CANH or CANL at 12 V,
VCC at 0 V
Bus input current
MIN
D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC
V
µA
A
pF
40
100
20
50
Sleep
EN at 0 V, D at VCC, Rs at 0 V or VCC
0.05
2
Standby
RS at VCC, D at VCC, AB at 0 V, LBK at 0 V,
EN at VCC
200
600
Dominant
D at 0 V, No Load, RS at 0 V, LBK at 0 V,
AB at 0 V, EN at VCC
6
Recessive
D at VCC, No Load, RS at 0 V, LBK at 0 V,
AB at 0 V, EN at VCC
6
kΩ
µA
mA
(1) All typical values are at 25°C and with a 3.3 V supply.
5
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
35
60
Propagation delay time, high-to-low-level output
35
60
tsk(p)
tr
Pulse skew (|tPHL − tPLH|)
7
See Figure 6
Output signal rise time
UNIT
ns
2
5
2
5
TYP(1)
MAX
See Figure 12
7.5
12
ns
See Figure 13
10
20
ns
See Figure 14
35
60
ns
RS at 0 V, See Figure 11
RS with 10 kΩ to ground,
See Figure 11
70
135
105
190
535
1000
70
135
105
190
535
1000
tf
Output signal fall time
(1) All typical values are at 25°C and with a 3.3 V supply.
DEVICE SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
t(LBK)
t(AB1)
Loopback delay, driver input to receiver output
t(AB2)
Loopback delay, bus input to receiver output
TEST CONDITIONS
HVD233
Loopback delay, driver input to receiver output
HVD235
Total loop delay, driver input to receiver output, recessive to
t(loop1)
dominant
RS with 100 kΩ to ground,
See Figure 11
Total loop delay, driver input to receiver output, dominant to
t(loop2)
recessive
RS at 0 V, See Figure 11
RS with 10 kΩ to ground,
See Figure 11
RS with 100 kΩ to ground,
See Figure 11
(1) All typical values are at 25°C and with a 3.3 V supply.
6
MIN
UNIT
ns
ns
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
IO(CANH)
II
D
60 Ω ±1%
VO(CANH)
VOD
VI
VO(CANH) + VO(CANL)
2
IIRs
RS
+
VI(Rs)
−
VOC
IO(CANL)
VO(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
Dominant
≈3V
Recessive
VO(CANH)
≈ 2.3 V
≈1V
VO(CANL)
Figure 2. Bus Logic State Voltage Definitions
VI
D
CANH
330 Ω ±1%
VOD
60 Ω ±1%
+
_
RS
CANL
−7 V ≤ VTEST ≤ 12 V
330 Ω ±1%
Figure 3. Driver VOD
CANH
CL = 50 pF ±20%
(see Note B)
D
VI
RL = 60 Ω ±1%
RS +
(see Note A)
VI(Rs)
−
VCC/2
VI
VO
0V
tPLH
VO
VCC
VCC/2
tPHL
0.9 V
VO(D)
90%
0.5 V
10%
CANL
tr
VO(R)
tf
NOTES:A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle,
tr ≤ 6ns, tf ≤ 6ns, ZO = 50Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
CANH
R
VI(CANH)
VI(CANH + VI(CANL)
VIC =
2
IO
VID
VO
CANL
VI(CANL)
Figure 5. Receiver Voltage and Current Definitions
2.9 V
CANH
R
VI
(see Note C)
1.5 V
IO
2.2 V
1.5 V
tPLH
CL = 50 pF ±20%
(see Note D)
CANL
2.2 V
VI
VO
tPHL
90%
50%
10%
VO
tr
90%
VOH
50%
10%
VOL
tf
NOTES:C. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle,
tr ≤ 6ns, tf ≤ 6ns, ZO = 50Ω.
D. CL includes fixture and instrumentation capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
VCANH
−6.1 V
VCANL
−7 V
L
12 V
11.1 V
L
OUTPUT
MEASURED
R
|VID|
900 mV
900 mV
VOL
−1 V
−7 V
L
12 V
6V
L
6V
6V
−6.5 V
−7 V
H
500 mV
12 V
11.5 V
H
500 mV
−7 V
−1 V
H
6V
12 V
H
6V
open
open
H
X
6V
VOH
CANH
R
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tf ≤ 100 ns
CANL
D at 0 V or VCC
Rs, AB, EN, LBK, at 0 V or VCC
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Over Voltage Test
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
HVD234
HVD233 or HVD235
VI
RS
CANH
D
60 Ω ±1%
0V
AB or LBK
CANL
VO
VO
+
15 pF ±20%
−
60 Ω ±1%
EN
VCC
R
CANH
D
0V
CANL
+
RS
VI
−
15 pF ±20%
VCC
50%
VI
0V
VOH
50%
VO
VOL
ten(s)
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50%
duty cycle.
Figure 8. ten(s) Test Circuit and Voltage Waveforms
HVD234
RS
0V
VI
VCC
CANH
D
60 Ω ±1%
+
−
VI
0V
EN
VOH
CANL
50%
VO
R
VO
50%
VOL
ten(z)
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 50 kHz, 50% duty cycle.
Figure 9. ten(z) Test Circuit and Voltage Waveforms
CANH
VI
27 Ω ±1%
VOC(PP)
D
VOC
RS
CANL
27 Ω ±1%
VOC
50 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 10. VOC(pp) Test Circuit and Voltage Waveforms
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
0Ω, 10 kΩ,
or 100 kΩ ±5%
DUT
RS
CANH
D
VI
60 Ω ±1%
LBK or AB
HVD233/235
EN
HVD234
R
VCC
+
VO
−
VCC
50%
VI
50%
0V
t(loop2)
CANL
t(loop1)
50%
VO
VOH
50%
VOL
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 11. t(loop) Test Circuit and Voltage Waveforms
RS
HVD233
+
VOD
−
D
VI
LBK
VCC
VCC
CANH
50%
VI
50%
0V
60 Ω ±1%
CANL
t(LBK1)
t(LBK2)
50%
VO
R
VO
t(LBK) =t(LBK1) =t(LBK2)
VOD
+
−
VOH
50%
VOL
≈ 2.3 V
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 12. t(LBK) Test Circuit and Voltage Waveforms
RS
VI
VCC
D
HVD235
CANH
+
60 Ω ±1%
VOD
−
CANL
VCC
50%
VI
50%
0V
t(ABH)
AB
R
≈ 2.3 V
VOD
VO
t(ABL)
50%
VOL
t(AB1) = t(ABH) = t(ABL)
VO
+
−
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr
or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 13. t(AB1) Test Circuit and Voltage Waveforms
10
VOH
50%
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
RS
HVD235
CANH
D
VCC
VI
60 Ω ±1%
2.2 V
1.5 V
t(ABH)
1.5 V
CANL
AB
VCC
2.9 V
2.2 V
VI
t(ABL)
50%
VO
R
t(AB2) = t(ABH) = t(ABL)
VO
+
−
VOH
50%
VOL
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 14. t(AB2) Test Circuit and Voltage Waveforms
 IOS 
IOS
D
0 V or VCC
15 s
CANH
+
_
IOS
0V
VI
12 V
CANL
VI
0V
0V
10 µs
and
VI
−7 V
Figure 15. IOS Test Circuit and Waveforms
3.3 V
R2 ± 1%
R1 ± 1%
+
VID
CANL −
TA = 25°C
VCC = 3.3 V
CANH
R
R2 ± 1%
Vac
R1 ± 1%
VI
The R Output State Does Not Change During
Application of the Input Waveform.
VID
500 mV
900 mV
R1
50 Ω
50 Ω
R2
280 Ω
130 Ω
12 V
VI
−7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 16. Common-Mode Voltage Rejection
11
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DEVICE INFORMATION
SN65HVD233D
(Marked as VP233)
(TOP VIEW)
D
GND
VCC
R
1
8
2
7
3
6
4
5
SN65HVD234D
(Marked as VP234)
(TOP VIEW)
RS
CANH
CANL
LBK
D
GND
VCC
R
1
8
2
7
3
6
4
5
SN65HVD235D
(Marked as VP235)
(TOP VIEW)
RS
CANH
CANL
EN
D
GND
VCC
R
1
8
2
7
3
6
4
5
RS
CANH
CANL
AB
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D INPUT
RS INPUT
VCC
VCC
CANH INPUT
VCC
110 kΩ
100 kΩ
INPUT
1 kΩ
45 kΩ
INPUT
9V
+
_
CANL INPUT
VCC
110 kΩ
9 kΩ
40 V
INPUT
CANH and CANL OUTPUTS
VCC
R OUTPUT
VCC
9 kΩ
5Ω
45 kΩ
INPUT
OUTPUT
OUTPUT
9 kΩ
40 V
9V
40 V
EN INPUT
LBK or AB INPUT
VCC
INPUT
1 kΩ
9V
12
9 kΩ
VCC
INPUT
100 kΩ
1 kΩ
9V
100 kΩ
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
Table 2. Thermal Characteristics
PARAMETERS
ΘJA
Junction-to-ambient thermal resistance(1)
ΘJB
ΘJC
Junction-to-board thermal resistance
P(AVG)
TEST CONDITIONS
(2)
Low-K board, no air flow
High-K(3) board, no air flow
VALUE
185
101
High-K(3) board, no air flow
Junction-to-case thermal resistance
RL = 60 Ω, RS at 0 V, input to D a 1-MHz 50%
duty cycle square wave
VCC at 3.3 V, TA = 25°C
Average power dissipation
T(SD)
Thermal shutdown junction temperature
(1) See TI literature number SZZA003 for an explanation of this parameter.
(2) JESD51−3 low effective thermal conductivity test board for leaded surface mount packages.
(3) JESD51−7 high effective thermal conductivity test board for leaded surface mount packages.
UNIT
°C/W
82.8
°C/W
26.5
°C/W
36.4
mW
170
°C
FUNCTION TABLES
DRIVER (SN65HVD233 OR SN65HVD235)
INPUTS
D
LBK/AB
OUTPUTS
RS
> 0.75 VCC
X
X
L
L or open
H or open
X
≤ 0.33 VCC
X
H
≤ 0.33 VCC
CANH
CANL
BUS STATE
Recessive
Z
Z
H
L
Dominant
Z
Z
Recessive
Z
Z
Recessive
RECEIVER (SN65HVD233)
INPUTS
BUS STATE
Dominant
VID = V(CANH)−V(CANL)
VID ≥ 0.9 V
?
VID ≤ 0.5 V or open
0.5 V < VID < 0.9 V
X
X
Recessive
X
OUTPUT
LBK
D
R
L or open
X
L
L or open
H or open
H
L or open
H or open
?
L
L
H
H
H
X
RECEIVER (SN65HVD235)
INPUTS
BUS STATE
OUTPUT
AB
D
R
L or open
X
L
VID ≤ 0.5 V or open
0.5 V < VID < 0.9 V
L or open
H or open
H
L or open
H or open
?
H
X
L
H
H
H
Recessive
VID ≥ 0.9 V
VID ≤ 0.5 V or open
VID ≤ 0.5 V or open
H
L
L
?
0.5 V < VID < 0.9 V
H
L
L
Dominant
Recessive
?
Dominant
Recessive
VID = V(CANH)−V(CANL)
VID ≥ 0.9 V
13
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DRIVER (SN65HVD234)
INPUTS
D
EN
OUTPUTS
L
H
RS
≤ 0.33 VCC
CANH
CANL
Bus State
H
L
Dominant
H
X
≤ 0.33 VCC
Z
Z
Recessive
Open
X
X
Z
Z
Recessive
X
X
> 0.75 VCC
Z
Z
Recessive
X
L or open
X
Z
Z
Recessive
RECEIVER (SN65HVD234)
INPUTS
Bus State
OUTPUT
VID = V(CANH)−V(CANL)
VID ≥ 0.9 V
EN
H
L
H
H
?
VID ≤ 0.5 V or open
0.5 V < VID < 0.9 V
H
?
X
X
L or open
H
Dominant
Recessive
H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
14
R
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
TYPICAL CHARACTERISTICS
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE
t (LOOPL2)− Dominant−To−Recessive Loop Time − ns
t (LOOPL1)− Ressive−To−Dominant Loop Time − ns
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE
90
Rs, LBK, AB = 0 V
EN = VCC
85
VCC = 3 V
80
VCC = 3.3 V
VCC = 3.6 V
75
70
65
60
−40
5
45
80
TA − Free-Air Temperature − °C
125
95
Rs, LBK, AB = 0 V
EN = VCC
90
85
VCC = 3.6 V
80
VCC = 3.3 V
75
70
VCC = 3 V
65
−40
Figure 17
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
20
160
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
140
I OL − Driver Output Current − mA
I CC − Supply Current − mA
125
Figure 18
SUPPLY CURRENT
vs
FREQUENCY
19
45
5
80
TA − Free-Air Temperature − °C
18
17
16
120
100
80
60
40
20
15
200
300
500
f − Frequency − kbps
Figure 19
700
1000
0
0
1
2
3
VOL − Low-Level Output Voltage − V
4
Figure 20
15
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
2.2
VCC = 3.3 V,
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
0.1
VCC = 3.6 V
VOD − Differential Output Voltage − V
I OH − Driver High-Level Output Current − mA
0.12
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
3
VOH − High-Level Output Voltage − V
2
VCC = 3.3 V
1.8
VCC = 3 V
1.6
1.4
RL = 60 Ω
Rs, LBK, AB = 0 V
EN = VCC
1.2
1
−40
3.5
Figure 21
42
Rs, LBK, AB = 0 V
EN = VCC
See Figure 6
VCC = 3.3 V
VCC = 3 V
41
40
39
38
VCC = 3.6 V
37
36
35
−40
5
45
80
TA − Free-Air Temperature − °C
Figure 23
16
125
RECEIVER HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
t PHL− Receiver High-To-Low Propagation Delay − ns
t PLH − Receiver Low-To-High Propagation Delay − ns
45
43
80
Figure 22
RECEIVER LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
44
45
5
TA − Free-Air Temperature − °C
125
38
37
Rs, LBK, AB = 0 V
EN = VCC
See Figure 6
36
35
VCC = 3 V
34
VCC = 3.3 V
33
VCC = 3.6 V
32
−40
5
45
80
TA − Free-Air Temperature − °C
Figure 24
125
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
50
Rs, LBK, AB = 0 V
EN = VCC
See Figure 4
VCC = 3.3 V
VCC = 3 V
45
40
35
VCC = 3.6 V
30
25
−40
5
45
DRIVER HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
t PHL− Driver High-To-Low Proragation Delay − ns
55
80
125
65
60
VCC = 3 V
55
50
VCC = 3.3 V
45
VCC = 3.6 V
40
Rs, LBK, AB = 0 V
EN = VCC
See Figure 4
35
30
−40
5
45
80
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 25
125
Figure 26
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
35
I O − Driver Output Current − mA
t PLH − Driver Low-To-High Propagation Delay − ns
DRIVER LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
Rs, LBK, AB = 0 V,
EN = VCC,
TA = 25°C
RL = 60 Ω
30
25
20
15
10
5
0
−5
0
0.6
1.2
1.8
2.4
VCC − Supply Voltage − V
3
3.6
Figure 27
17
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
APPLICATION INFORMATION
Diagnostic Loopback (SN65HVD233)
The loopback (LBK) function of the HVD233 is enabled with a high-level input to pin 5. This forces the driver into a
recessive state and redirects the data (D) input at pin 1 to the received-data output (R) at pin 4. This allows the host
controller to input and read back a bit sequence to perform diagnostic routines without disturbing the CAN bus. A
typical CAN bus application is displayed in Figure 28.
If the LBK pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a low−level
input) and may be left open if not in use.
Autobaud Loopback (SN65HVD235)
The autobaud feature of the HVD235 is implemented by placing a logic high on pin 5 (AB). In autobaud, the
bus-transmit function of the transceiver is disabled, while the bus-receive function and all of the normal operating
functions of the device remain intact. With the autobaud function engaged, normal bus activity can be monitored by
the device. However, if an error frame is generated by the local CAN controller, it is not transmitted to the bus. Only
the host microprocessor can detect the error frame.
Autobaud detection is best suited to applications that have a known selection of baud rates. For example, a popular
industrial application has optional settings of 125 kbps, 250 kbps, or 500 kbps. Once the logic high has been applied
to pin 5 (AB) of the HVD235, assume a baud rate such as 125 kbps, then wait for a message to be transmitted by
another node on the bus. If the wrong baud rate has been selected, an error message is generated by the host CAN
controller. However, since the bus-transmit function of the device has been disabled, no other nodes receive the error
message of the controller.
This procedure makes use of the CAN controller’s status register indications of message received and error warning
status to signal if the current baud rate is correct or not. The warning status indicates that the CAN chip error counters
have been incremented. A message received status indicates that a good message has been received.
If an error is generated, reset the CAN controller with another baud rate, and wait to receive another message. When
an error-free message has been received, the correct baud rate has been detected. A logic low may now be applied
to pin 5 (AB) of the HVD235, returning the bus-transmit normal operating function to the transceiver.
CANH
Bus Lines −− 40 m max
120 Ω
120 Ω
Stub Lines −− 0.3 m max
CANL
5V
Vref
Vcc
0.1µ F
SN65HVD251
Rs
3.3 V
Vcc
Rs
D
CANTX
R
GND
D
LBK
CANRX
0.1µ F
SN65HVD233
GND
3.3 V
Vref
GPIO
CANTX
R
CANRX
Vcc
0.1µ F
SN65HVD230
Rs
GND
D
CANTX
R
CANRX
TMS320LF243
TMS320F2812
TMS320LF2407A
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Figure 28. Typical HVD233 Application
Interoperability With 5-V CAN Systems
ISO−11898 specifies the interface characteristics to a CAN bus with the purpose of insuring interchangeability among
compatible transceivers. While the levels specified in the standard assume a 5-V supply, there is nothing in the
standard that makes this a requirement. The SN65HVD233 is compatible with these requirements with a 3.3-V
supply, assuring interoperability with 5-V supplied transceivers.
Bus Cable
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a maximum
of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes
to a bus. A large number of nodes requires a transceiver with high input impedance such as the HVD233.
18
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
The standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept
as short as possible to minimize signal reflections.
Slope Control
The rise and fall slope of the SN65HVD233, SN65HVD234, and SN65HVD235 driver output can be adjusted by
connecting a resistor from the Rs (pin 8) to ground (GND), or to a low-level input voltage as shown in Figure 29.
The slope of the driver output signal is proportional to the pin’s output current. This slope control is implemented with
an external resistor value of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew
rate as displayed in Figure 30. Typical driver output waveforms with slope control are displayed in Figure 31.
10 kΩ
to
100 kΩ
D
GND
Vcc
R
1
2
3
4
8
Rs
7
6
5
CANH
CANL
LBK
IOPF6
TMS320LF2407
Figure 29. Slope Control/Standby Connection to a DSP
25
Slope (V/us)
20
15
10
5
0
0
4.7 6.8
10
15
22
33
47
68
100
Slope Control Resistance − kΩ
Figure 30. HVD233 Driver Output Signal Slope vs Slope Control Resistance Value
19
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
Rs = 0 Ω
Rs = 10 k Ω
Rs = 100 k Ω
Figure 31. Typical SN65HVD233 250-kbps Output Pulse Waveforms With Slope Control
Standby
If a high−level input (> 0.75 VCC) is applied to Rs (pin 8), the circuit enters a low-current, listen only standby mode
during which the driver is switched off and the receiver remains active. The local controller can reverse this low-power
standby mode when the rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
20
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD233D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD233DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD233DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD233DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD234D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD234DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD234DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD234DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD235D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD235DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD235DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD235DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD233DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD234DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD235DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD233DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD234DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD235DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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