IRF830A, SiHF830A Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Low Gate Charge Qg Results in Simple Drive Available Requirement • Improved Gate, Avalanche and Dynamic dV/dt RoHS* COMPLIANT Ruggedness • Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss Specified • Lead (Pb)-free Available 500 RDS(on) (Ω) VGS = 10 V 1.4 Qg (Max.) (nC) 24 Qgs (nC) 6.3 Qgd (nC) 11 Configuration Single D TO-220 APPLICATIONS • Switch Mode Power Supply (SMPS) • Uninterruptable Power Supply • High Speed power Switching G S G TYPICAL SMPS TOPOLOGIES D S • Two Transistor Forward • Half Bridge • Full Bridge N-Channel MOSFET ORDERING INFORMATION Package TO-220 IRF830APbF SiHF830A-E3 IRF830A SiHF830A Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor UNIT V 5.0 3.2 A 20 0.59 W/°C Single Pulse Avalanche Energyb EAS 230 mJ Repetitive Avalanche Currenta IAR 5.0 A Repetitive Avalanche Energya EAR 7.4 mJ Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque for 10 s 6-32 or M3 screw PD 74 W dV/dt 5.3 V/ns TJ, Tstg - 55 to + 150 300d °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 18 mH, RG = 25 Ω, IAS = 5.0 A (see fig. 12). c. ISD ≤ 5.0 A, dI/dt ≤ 370 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91061 S-81145-Rev. B, 02-Jun-08 www.vishay.com 1 IRF830A, SiHF830A Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Case-to-Sink, Flat, Greased Surface RthCS 0.50 - Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 µA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.60 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.5 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS Gate-Source Threshold Voltage VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 µA - - 1.4 Ω gfs VDS = 50 V, ID = 3.0 Ab 2.8 - - S Input Capacitance Ciss VGS = 0 V, - 620 - 93 - 4.3 - Drain-Source On-State Resistance Forward Transconductance RDS(on) ID = 3.0 Ab VGS = 10 V Dynamic Output Capacitance Coss VDS = 25 V, - Reverse Transfer Capacitance Crss f = 1.0 MHz, see fig. 5 - Output Capacitance Coss VGS = 0 V; VDS = 1.0 V, f = 1.0 MHz 886 Coss VGS = 0 V; VDS = 400 V, f = 1.0 MHz 27 Coss eff. VGS = 0 V; VDS = 0 V to 400 Vc 39 Output Capacitance Effective Output Capacitance Total Gate Charge Qg VGS = 10 V ID = 5.0 A, VDS = 400 V, - - 24 - - 6.3 Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 11 Turn-On Delay Time td(on) - 10 - Rise Time Turn-Off Delay Time Fall Time tr td(off) see fig. 6 and 13b VDD = 250 V, ID = 5.0 A, RG = 14 Ω, RD = 49 Ω, see fig. 10b tf pF nC - 21 - - 21 - - 15 - - - 5.0 - - 20 - - 1.5 V - 430 650 ns - 1.62 2.4 µC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 5.0 A, VGS = 0 Vb TJ = 25 °C, IF = 5.0 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. www.vishay.com 2 Document Number: 91061 S-81145-Rev. B, 02-Jun-08 IRF830A, SiHF830A Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91061 S-81145-Rev. B, 02-Jun-08 www.vishay.com 3 IRF830A, SiHF830A Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 91061 S-81145-Rev. B, 02-Jun-08 IRF830A, SiHF830A Vishay Siliconix RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 t1 0.02 0.01 t2 SINGLE PULSE (THERMAL RESPONSE) 0.01 0.00001 0.0001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS D.U.T. RG IAS 20 V tp Driver + A - VDD IAS 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91061 S-81145-Rev. B, 02-Jun-08 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 IRF830A, SiHF830A Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91061 S-81145-Rev. B, 02-Jun-08 IRF830A, SiHF830A Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91061. Document Number: 91061 S-81145-Rev. B, 02-Jun-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. 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