Typical Size 6.4 mm X 9.7 mm SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 34 V, Digital-Input Serializer for 5V Systems FEATURES 1 • Eight Digital Sensor Inputs – High Input Voltage up to 34 V – Selectable Debounce Filters From 0 ms to 3 ms – Flexible Input Current-Limited – 0.2 mA to 5.2 mA – Field Inputs Protected to 15-kV ESD • Single 5V Supply • Output Drivers for External Status LEDs • Cascadable for More Inputs in Multiples of Eight 2 • • SPI-Compatible Interface Over-Temperature Indicator APPLICATIONS • • • • Industrial PCs Digital I/O Cards High Channel Count Digital Input Modules Decentralized I/O Modules DESCRIPTION The SN65HVS885 is an eight channel, digital-input serializer for high-channel density digital input modules in industrial and building automation. Operating from a 5V supply the device accepts field input voltages of up to 34V. In combination with galvanic isolators the device completes the interface between the high voltage signals on the field-side and the low-voltage signals on the controller side. Inputs signals are current limited and then validated by internal debounce filters. With the addition of few external components, the input switching characteristic can be configured in accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches. Upon the application of load and clock signals, input data is latched in parallel into the shift register and afterwards clocked out serially. Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial input of the following device, enabling the design of high-channel count input modules. Multiple devices can be cascaded through a single serial port, reducing both the isolation channels and controller inputs required. Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a single, external, precision resistor. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system safety. The SN65HVS885 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The device is specified for operation at temperatures from –40°C to 125°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com 8 GND LED Outputs RE 0:7 IREF Adjust: RLIM 8 Serial Input 3 8 SERIALIZER Field Inputs IP 0:7 2 Signal Conditioning Debounce Select DB 0:1 Control Inp[uts LD, CE, CLK VCC Serial Output DB0 DB1 IP0 RE0 IP1 RE1 IP2 RE2 IP3 RE3 IP4 RE4 RLIM NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND SIP LD CLK CE SOP IP7 RE7 IP6 RE6 IP5 RE5 HOT VCC FUNCTIONAL BLOCK DIAGRAM Vcc HOT RLIM Adj. Current Thresholds RE0 IP0 Current Sense Thermal Protection SIP Debounce Filter Channel 0 GND RE7 IP7 SERIALIZER & Voltage Sense DB0 DB1 Debounce Select LD CE CLK Channel 7 SOP 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 TERMINAL FUNCTIONS TERMINAL PIN NO. NAME DESCRIPTION 1, 2 DB0, DB1 3, 5, 7, 9, 11, 18, 20, 22 Debounce select inputs IPx Input Channel x 4, 6, 8, 10, 12, 17, 19, 21 REx Return Path x (LED drive) 13 RLIM Current Limiting Resistor 14 NC Not Connected 15 VCC 5 V Device Supply 16 HOT Over-Temperature Flag 23 SOP Serial Data Output 24 CE Clock Enable Input 25 CLK Serial Clock Input 26 LD Load Pulse Input 27 SIP Serial Data Input 28 GND Device Ground Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 3 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VCC Device power input VCC –0.5 to 6 V VIPx Field digital inputs IPx –0.3 to 36 V VID Voltage at any logic input DB0, DB1, CLK, SIP, CE, LD –0.5 to 6 V IO Output current HOT, SOP ±8 mA All pins ±4 IPx ±15 Human-Body Model (2) VESD Electrostatic discharge Charged-Device Model (3) All pins ±1 kV Machine Model (4) All pins ±100 V PTOT Continuous total power dissipation TJ Junction temperature (1) (2) (3) (4) kV See Thermal Characteristics table 170 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. JEDEC Standard 22, Method A114-A. JEDEC Standard 22, Method C101 JEDEC Standard 22, Method A115-A THERMAL CHARACTERISTICS PARAMETER θJA Junction-to-air thermal resistance θJB Junction-to-board thermal resistance θJC Junction-to-case thermal resistance PD Device power dissipation TEST CONDITIONS MIN High-K thermal resistance VCC = 5 V, RIN = 0Ω, RLIM = 25 kΩ, RE0 – RE7 = GND, fCLK = 100 MHz TYP MAX UNIT 35 °C/W 15 °C/W 4.27 °C/W IP0-IP7 = 34V IP0-IP7 = 30V 1100 IP0-IP7 = 24V mW IP0-IP7 = 12V RECOMMENDED OPERATING CONDITIONS MIN TYP MAX 4.5 5 5.5 V 0 4 V 5.5 34 V 0 0.8 V 2.0 5.5 V 500 kΩ VCC Device supply voltage VIPL Field input low-state input voltage VIPH Field input high-state input voltage VIL Logic low-state input voltage VIH Logic high-state input voltage RLIM Current limiter resistor 17 fIP (1) Input data rate TA Device 0 1 –40 125 °C 150 °C TJ (1) 4 25 UNIT Mbps Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 ELECTRICAL CHARACTERISTICS over full-range of recommended operating conditions (unless otherwise noted) all voltages measured against device ground, see Figure 9 PARAMETER TERMINAL TEST CONDITIONS MIN TYP MAX UNIT FIELD INPUTS VTH–(IP) Low-level device input threshold voltage VTH+(IP) High-level device input threshold voltage VHYS(IP) Device input hysteresis VTH–(IN) Low-level field input threshold voltage VTH+(IN) High-level field input threshold voltage VHYS(IN) Field input hysteresis 4.0 IP0–IP7 RLIM = 25 kΩ measured at field side of RIN 4.5 V < VCC < 5.5 V, RIN = 1.2 kΩ ± 5%, RLIM = 25 kΩ, TA ≤ 125°C RIP Input resistance IP0–IP7 IIP-LIM Input current limit IP0–IP7 RLIM = 25 kΩ IRE-on 5.2 V 5.5 0.9 3 V < VIPx < 6 V, RLIM = 25 kΩ tDB 4.3 Debounce times of input channels IP0–IP7 RE on-state current RE0–RE7 6 V 10 1 V V 0.2 0.63 1.1 kΩ 3.15 3.6 4 mA DB0 = open, DB1 = GND 0 DB0 = GND, DB1 = open 1 DB0 = DB1 = open 3 RLIM = 25 kΩ, REX = GND V 8.4 9.4 V 2.8 ms 3.15 3.5 mA 6.5 10 mA 0.4 V DEVICE SUPPLY ICC(VCC) Supply current IP0 to IP7 = 24V, REX = GND, All logic inputs open VCC LOGIC INPUTS AND OUTPUTS IOL = 20 µA VOL Logic low-level output voltage VOH Logic high-level output voltage IIL Logic input leakage current TOVER Over-temperature indication 150 °C TSHDN Shutdown temperature 170 °C SOP, HOT IOH = –20 µA 4 DB0, DB1, SIP, LD, CE, CLK V –50 50 µA TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tW1 CLK pulse width See Figure 6 4 ns tW2 LD pulse width See Figure 4 6 ns tSU1 SIP to CLK setup time See Figure 7 4 ns tH1 SIP to CLK hold time See Figure 7 2 ns tSU2 Falling edge to rising edge (CE to CLK) setup time See Figure 8 4 ns tREC LD to CLK recovery time See Figure 5 2 ns fCLK Clock pulse frequency See Figure 6 DC 100 MHz SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1, tPHL1 CLK to SOP CL = 15 pF, see Figure 6 10 ns tPLH2, tPHL2 LD to SOP CL = 15 pF, see Figure 4 14 ns tr, tf Rise and fall times CL = 15 pF, see Figure 6 6 ns Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 5 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com INPUT CHARACTERISTICS 30 RIN = 1.2 kW 25 VIN / V 20 a) IIP-LIM = 2.5mA (RLIM = 36.1 kW) c) b) a) b) IIP-LIM = 3.0mA (RLIM = 30.1 kW) c) IIP-LIM = 3.6mA (RLIM = 24.9 kW) 15 10 Off On 5 Field Input Thresholds 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I IN / mA Figure 1. Typical Input Characteristics IIP–LIM/IIP–LIM –25°C - % 102.0 VCC = 5 V, 101.5 VIN = 24 V, RIN = 1.2 kW, 101.0 RLIM = 24.9 kW 100.5 100.0 99.5 99.0 98.5 98.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TA - Ambient Temperature - °C Figure 2. Typical Current Limiter Variation vs Ambient Temperature 9.6 9.4 VTH+(IN) VIN – V 9.2 9.0 8.8 VCC = 5 V, RIN = 1.2 kW, RLIM = 24.9 kW 8.6 8.4 VTH–(IN) 8.2 8.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 TA - Ambient Temperature - °C Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 PARAMETER MEASUREMENT INFORMATION Waveforms For the complete serial interface timing, refer to Figure 17. tW2 LD LD tREC tLPH2 tPLH2 CLK SOP Figure 4. Parallel – Load Mode Figure 5. Serial – Shift Mode 1/fCLK valid tW1 SIP CLK tPLH1 tSU1 tPHL1 tH1 CLK SOP tr tf Figure 6. Serial – Shift Mode Figure 7. Serial – Shift Mode CLK tSU2 CLK inhibited CE Figure 8. Serial – Shift Clock Inhibit Mode Signal Conventions R IN IPx IIN VTH(IN) VTH(IP) SN65HVS885 GND Figure 9. On/Off Threshold Voltage Measurements Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 7 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com DEVICE INFORMATION Digital Inputs 1.25 VREF 5V ILIM Mirror n = 72 IIN IPx ILIM Limiter IINmax = ILIM IREF RLIM Figure 10. Digital Input Stage Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM. Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM. Inserting the actual values for n and VREF gives: RLIM = 90 V / ILIM. While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate: RLIM = 90 V 90 V = = 36 kΩ ILIM 2.5 mA Debounce Filter The HVS885 applies a simple analog/digital filtering technique to remove unintended signal transitions due to contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration of the selected debounce time to be latched into the shift register as a valid state. The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the different debounce times listed in the following truth table. Table 1. Debounce Times 8 DB1 DB0 FUNCTION Open Open 3 ms delay Open GND 1 ms delay GND Open 0 ms delay (Filter bypassed) GND GND Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 5V IPx REF REx RLIM GND Figure 11. Equivalent Input Diagram Shift Register The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register also provides a clock-enable function. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock enable (CE) input is held low. Parallel loading is inhibited when LD is held high. The parallel inputs to the register are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs. SIP D CLK CE Logic Q CP R D Q CP S R D Q CP S R D Q CP S R D Q CP S R D Q CP S R D Q CP S R D Q SOP CP S R S LD PIP 0 PIP 1 PIP 2 PIP 3 PIP 4 PIP 5 PIP 6 PIP 7 Figure 12. Shift Register Logic Structure Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 9 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com Table 2. Function Table INPUTS (1) FUNCTION LD CLK CE L X X Parallel load H X H No change H ↑ L Shift (1) Shift = content of each internal register shifts towards serial outputs. Data at SIP is shifted into first register. Temperature Sensor An on-chip temperature sensor monitors the device temperature and signals a fault condition if the temperature exceeds a first trip point at 150°C by pulling the HOT output low. If the junction temperature continues to rise, passing a second trip point at 170 °C, all device outputs assume high impedance state. A special condition occurs when the chip temperature exceeds the second temperature trip point due to an output short; the HOT output buffer becomes high impedance, thus separating the buffer from the external circuitry. An internal 100-kΩ pulldown resistor, connecting the HOT-pin to ground, is used as a "cooling down" resistor, which continues to provide a logic low level to the external circuitry. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 APPLICATION INFORMATION System-Level EMC The SN65HVS885 is designed to operate reliably in harsh industrial environments. At a system level, the device is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the device internal ESD structures, external protection circuitry shown in Figure 13, can be used to absorb as much energy from burst- and surge-transients as possible. R IN INx RIN 1.2 kW, 1/4 W MELF Resistor CIN 220 nF, 60 V Ceramic Capacitor CS 4.7 nF, 2 kV Ceramic Capacitor IP0 – IP7 V CC 5V C IN 1mF SN65HVS885 0V GND CS FE Figure 13. Typical EMC Protection Circuitry for Supply and Signal Inputs Input Channel Switching Characteristics The input stage of the HVS885 is so designed, that for an input resistor RIN = 1.2 kΩ the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC61131-2 Type 1 and Type 3 switches. Type 2 Type 3 30 30 30 25 25 25 15 10 5 ON 20 VIN (V) ON 20 VIN (V) VIN (V) Type 1 15 10 5 OFF 0 –30 5 10 IIN (mA) 15 10 5 OFF 0 –3 15 ON 20 0 5 10 15 OFF 0 –3 20 25 IIN (mA) 30 0 5 10 IIN (mA) 15 Figure 14. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator LED, the RE-pin of the other input channel should be connected to ground (GND). Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by two shift register bits. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 11 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com RIN RIN IN0 IN0 IP0 IP0 CIN CIN RE0 RE0 RIN RIN IN1 IP1 IP1 CIN CIN RE1 RE1 Figure 15. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input Digital Interface Timing The digital interface of the SN65HVS885 is SPI compatible and interfaces, isolated or non-isolated, to a wide variety of standard micro controllers. SN65HVS885 SIP IP7 SERIALIZER IP0 HOST CONTROLLER ISO7241 LD OUTA INA CE OUTB INB CLK OUTC INC SOP IND OUTD LOAD STE SCLK SOMI Figure 16. Simple Isolation of the Shift Register Interface Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift register. Taking /LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data is clocked at the rising edge of CLK. Thus after eight consecutive clock cycles all field input data have been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP. 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 SN65HVS885 www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009 CLK CE SIP high LD PIP0–PIP6 PIP7 IP 6 IP7 SOP don’t care IP 5 IP4 inhibit IP3 IP2 IP1 IP 0 SIP Serial shift Figure 17. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register Cascading for High Channel Count Input Modules Designing high-channel count modules require cascading multiple SN65HVS885 devices. Simply connect the serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the processor interface. HOST CONTROLLER ISO7241 4 x SN65HVS885 OUTA INA OUTB INB OUTC INC SCLK SOMI SOP CE OUTD STE IP7 SERIALIZER IP0 IP7 IP0 SERIALIZER CLK LD SIP SOP CE CLK LD SIP CE SOP IP7 SERIALIZER IP0 IP7 IP0 SERIALIZER CLK LD SIP SOP CE CLK LD SIP IND LOAD Figure 18. Cascading Four SN65HVS885 for a 32-Channel Input Module Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 13 SN65HVS885 SLAS638 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com Typical Digital Input Module Application Isolated DC-DC SM15T39A 24V Power 0V Supply 5VO 3VIN 3V-ISO 0VO 0VIN 0V-ISO 4.7nF 2kV 4.7nF 2kV FE SN65HVS885 1.2k MELF NC VCC IP0 HOT RE0 SIP 0.1 mF ISO7242 VCC2 VCC1 HOST CONTROLLER 22nF S0 1.2k MELF EN2 EN1 VCC LD OUTA INA LOAD CLK OUTB INB SCLK CE INC OUTC INT RE7 SOP IND OUTD SOMI RLIM DB0 GND2 GND1 DGND GND DB1 IP7 22nF S7 24.9k Figure 19. Typical Digital Input Module Application 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVS885 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVS885PWP ACTIVE HTSSOP PWP 28 SN65HVS885PWPR ACTIVE HTSSOP PWP 28 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65HVS885PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVS885PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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