5504 DCR Direct Conversion Receiver Advanced Information April 2000 DESCRIPTION FEATURES The 5504 is a low cost, high performance direct conversion receiver (DCR) specifically designed for digital wireless applications. The DCR architecture provides a receiver design with fewer external components than the conventional dual conversion approach. The 5504 is designed to operate over an input frequency range of 950 to 2150 MHz. The device accepts an input signal in this frequency range and down converts directly to baseband. The local oscillator signal is generated by a completely integrated phase lock loop that is fully programmable through a standard serial port interface. • Wideband I/Q demodulator – RF input 950 to 2150 MHz – External lowpass filter - Integrated post-filter baseband drivers • Integrated VCO and frequency synthesizer • AGC Amplifier APPLICATIONS • Digital Satellite • VSAT Receivers Iin Qin QO1 IO1 TP2 TP1 VPD2 VPD1 VPA6 VPA5b VPA5a VPA4 VPA3b VPA3a VPA1 BLOCK DIAGRAM AGC IO2 RFp Power Splitter RFn QO2 Serial Port R3 R2 R1 R0 Xtal Osc. Divide 10-bit VCO1 C1 FILN RSHP RSHN Modulo 6-bit VCO Charge Pump RSLP Divide 11-bit RSLN Div 32/33 1 VND1 VNA5 VNA4 VNA3b 216............. 26 VNA3a Rext Phase Detect VNS EON VCO0 25 ............. 20 C0 VNA1 XTLP XTLN VNA6a Din 90 VNA6b Dclk 0 5504 DCR Direct Conversion Receiver FUNCTIONAL DESCRIPTION +5 AGC Amplifier L2 The 5504 RF input can be driven differentially or single ended. The RFp and RFn inputs are selfbiasing and are designed to be driven from a 50 Ohm source. For single-ended operation, the RFn pin should be AC coupled to analog ground. A gain control input, AGC, provides a 25 dB gain variation with 0V providing minimum gain and 4V providing maximum gain. Vtune 10 kΩ 12pF L2 47 Ω 47 Ω L1 29 BB835 28 L1 12pF 32 33 C1 High Low 5503 10 kΩ I/Q Mixer The AGC amplifier drives the RF port of two identical double balanced mixers. The LO ports of these mixers are driven from an on-chip quadrature network. Note: A separate resonator circuit is required for each oscillator Low Pass Filtering and Buffering The synthesizer derives its reference from a source which can be either an externally derived clock or an external crystal coupled to the internal oscillator. This source drives a programmable reference divider with 15 preset divide ratios from 2 to 320. This divider output provides the PLL reference by driving one input of a phase/frequency detector. The VCO output drives a divider chain incorporating a variable modulus prescaler and divider. The divider is programmed by a 17-bit control word. This divider chain output drives the other input of the phase/frequency detector. PLL Synthesizer Following each mixer, a buffer amplifier is provided for driving an external passive low-pass filter. The nominal output impedance for IO1 and Q01 is 50 ohms. A second high impedance buffer amplifier is provided (IIN or QIN) for additional gain and isolation after the filter. The figure below shows a typical filter designed for 20 Megasymbol per second operation: 0.1 F IO1/QO1 470nH 12pF 68pF Loop Filter 680nH 68pF IIN/QIN The phase/frequency detector interface consists of two ports, FILN and EON. The EON drives the base of an external NPN transistor, and the FILN provides a feedback path for the loop filter elements. The external transistor permits VCO tune voltages of greater than 30V and also provides the final stage of the loop amplifier. Below is shown a typical loop filter: Dual VCO The 5504 uses two VCOs to cover the entire specified tuning range. Both VCOs use nearly identical architecture with the only difference being slight design modifications to optimize the range of operation. The lower range VCO requires an external resonator that supports a tuning range of 950 to 1473 MHz. The higher range VCO requires a similar resonator with inductor values designed to support the range of 1390 to 2150 MHz. A typical lumped-element resonator circuit incorporating varactor tuning is shown in the following figure: +28V 1000pF 0.1 F FILN EON 10 kW Vtune 10 k Q1 2 5504 DCR Direct Conversion Receiver LOW PASS FILTER +5V LOW PASS FILTER VPA3a LNA PIN ATTEN. VPA3b AGC VPA4 VPA5a VPA5b 42 11 4 5 30 31 VPA1 15 VPD2 2 VPD1 3 RFP 7 RFN 6 IO1 QO1 QIN IIN 14 21 23 18 TP1C TP2C Rxt 43 44 24 7.68k 17 IO2 AGC AMP QUAD GEN 22 QO2 12 XTALP 46 XTAL 45 OSC VNS 41 VNA4 9 VNA5b PLL SYNTH. 8 VNA5a XTALN 47 SHIFT REGISTER/ DIN 48 RAM DCLK 1 19 35 25 36 VND1 VNA1 VNA3a VNA3b RSLN DUAL VCO 32 29 26 39 37 RSLP RSHN RSHP EON FILN LOW HIGH RESONATOR RESONATOR DCR Application Drawing 3 PLL LOOP FILTER DEMOD/FEC ADC ADC 5504 DCR Direct Conversion Receiver PIN DESCRIPTIONS ANALOG PINS NAME RFP, RFN AGC Eon, Filn TYPE I I I/O XTLP, XTLN I IO2, QO2 O IO1, QO1 O IIN, QIN I Rxt I RSHP, RSHN RSLP, RSLN I I DESCRIPTION RF inputs: balanced differential inputs to the receiver. The input signals placed on this line are amplified with a variable gain amplifier before being passed to the I/Q demodulator. Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input amplifier gain from minimum to maximum. The gain increase is 25 dB typical External loop filter interface. Eon drives the base of an external common emitter transistor. Filn is the feedback input from the loop filter capacitor. Reference crystal input. An external crystal connected between these pins establishes the reference frequency for the PLL synthesizer. Following this oscillator is a programmable divider that establishes the synthesizer step size. Baseband outputs. These typically drive an A/D converter prior to digital demodulation and processing. I and Q channel outputs to external low pass filter. An external series resistor can be connected between this output and the filter to provide the source match. I and Q channel inputs from external low pass filter. These are high impedance inputs (>5000Ω). The low pass filter must be designed for low input and high output impedance. External reference resistor. This resistor is connected to ground and must be 7.68k ±1%. It is used as a reference for internal bias currents. High range VCO resonator inputs Low range VCO resonator inputs DIGITAL PINS Din I/O Dclk I I2C data. This signal is connected to the I2C internal block. An external resistor (typically 2.2 kΩ) is connected between Din and Vcc for proper operation I2C clock Input. Dclk should nominally be a square wave with a maximum frequency of 400kHz. SCL is generated by the system I2C master. 4 5504 DCR Direct Conversion Receiver POWER PINS VPA1, VPA3a, VPA3b, VPA4, VPA5a, VPA5b, VPA6 VPD1, VPD2 VNA1, VNA3a, VNA3b, VNA4, VNA6, VNA7 VND1 VNS I Analog Vcc pins I I Digital Vcc pin. Analog ground pins. I I Digital ground pin. Substrate ground pin. MICROCONTROLLER SERIAL INTERFACE 2 I C REGISTERS: WRITE MODE S address 0 A reg0 A reg1 A reg2 A reg3 5504 address 1 1 0 0 0 0 1 S: start bit A: acknowledge bit P: stop bit TABLE 1: MICROCONTROLLER INTERFACE REGISTER REGISTER 0 7(MSB) 0 7 6 14 2 6 1 2 2 2 1 2 3 C1 C0 16 5 4 13 12 2 2 5 4 2 3 11 2 3 2 1 10 9 2 2 2 1 0 (LSB) 8 2 0 2 2 2 2 2 2 x R3 R2 R1 R0 test1 test0 Pdisab vco1 vco0 15 5 x 5504 DCR Direct Conversion Receiver DESCRIPTION OF INTERNAL REGISTERS Register 0 VCO divide ratio, bits 14 through 8, msb always set to 0 Register 1 Register 2 VCO divide ratio, bits 7 through 0 msb not used. Always set to 1 VCO divide ratio, bits 16 and 15 R3, R2, R1, R0 Reference division ratio, as shown in following table: R3 R2 R1 R0 Register 3 C1, C0 Reference division ratio 0000 2 0001 4 0010 8 0011 16 0100 32 0101 64 0110 128 0111 256 1000 Undefined 1001 5 1010 10 1011 20 1100 40 1101 80 1110 160 1111 320 Phase detector current control, as shown in following table: ipump word C1 C0 Phase Detector charge current µA 00 100 01 200 10 300 11 400 6 5504 DCR Direct Conversion Receiver test0, test1 Pdisab Test point select as shown in following table: test1 test0 tp1 tp2 0 0 disabled disabled 0 1 pump up pump down 1 0 M cnt N cnt 1 1 prescaler modulus Phase detector disable (1 = disable, 0 = enable) (vco0, vco1) Vco select word as shown in following table: vco1 vco0 Low band VCO High band VCO 0 0 disabled disabled 0 1 enabled disabled 1 0 disabled enabled 1 1 undefined undefined 7 5504 DCR Direct Conversion Receiver ABSOLUTE MAXIMUM RATINGS Operation beyond maximum rating may permanently damage the device. PARAMETER Storage temperature Junction operating temperature Positive supply voltage (Vp) Voltage applied to any pin RATING -55 to 150 °C +110 °C -0.3 to 6V -0.3V to VCCn+0.3V TARGET SPECIFICATIONS Unless otherwise specified: 0° < Ta < 70 °C; positive power supply (VCCn) = +5.0 V ±5%. OPERATING CHARACTERISTICS PARAMETER CONDITION Supply current All outputs loaded MIN NOM MAX UNIT 120 150 mA Digital I/O Characteristics (Din, Dclk) High level input voltage 2 Vcc+0.3 V Low level input voltage Gnd - 0.3 0.8 V 100 uA - 400 uA 100 Ω High level input current Vin = Vcc - 1.0V Low level input current Vin = 1.0V Receiver Characteristics Unless otherwise noted, input source impedance is 75 Ω Input impedance, RFp RFn bypassed to ground with 100 pf 40 70 Input signal range -50 -28 dBm Input frequency range 950 2150 MHz AGC Range 0V < VAGC < 4V 22 25 AGC Control Input current 0V < Vagc < 4V DCR Max. Gain, Lower Band Range Fin = 950 MHz, AGC = 4V, Gain measured from RFp to IO2/Q02 50 dB DCR Max. Gain, Upper Band Range Fin = 2150 MHz, AGC = 4V, Gain measured from RFp to IO2/Q02 49 dB Noise figure Measured at maximum gain 7 15 dB 10 18 uA dB nd Vrf_in = -28 dBm/tone 10 12 dBm rd 3 order IIP Vrf_in = -28 dBm/tone -4 -2 dBm Lo Leakage Measured at RFp 2 order IIP -70 -60 dBm VCO Characteristics Tuning range, Low OSC L1 = 8.2nH L2 = 27nH C1 = 1pF 950 1475 MHz Tuning range, High OSC L1 = 3.9nH L2 = 22nH C1 = .6pF 1380 2150 MHz Phase Noise 10kHz offset -78 -75 dBc/Hz 8 10 MHz 100 Ω Crystal Characteristics Frequency 6 ESR Load Capacitance 20 8 pF 5504 DCR Direct Conversion Receiver OPERATING CHARACTERISTICS (continued) Low Pass Filter Interface IO1, QO1 output impedance 40 50 Filter Loss 60 Ω 1db Filter Input Impedance 50 10000 Ω 10000 Ω 16 dB 10 Ω I and Q Buffer Amplifier (each output loaded with 4pF in parallel with 20kΩ) Input resistance Freq. = 30 MHz Input capacitance Freq. = 30 MHz Voltage Gain Freq. = 30 MHz 5000 8000 5pf 14 15 Output impedance I/Q output amplitude -3dB frequency, Frf-Flo 0.75 0.5 Vpp 78 82 MHz Buffer THD 1% 2% Amplitude and Phase Characteristics I/Q quadrature accuracy -3 +3 degree I/Q amplitude matching -1 +1 dB 9 5504 DCR Direct Conversion Receiver PACKAGE PIN DESIGNATIONS 48 47 46 45 44 43 42 41 40 39 38 FILN N/C EON N/C VNA4 VPA4 TP2C TP1C XTLN XTLP DIN DCLK (Top View) N/C VPA5a 4 33 N/C VPA5b 5 32 RSLP RFN 6 31 VPA3b RFP 7 30 VPA3a VNA5a 8 29 RSHN VNA5b 9 28 N/C N/C 10 27 N/C AGC 11 26 RSHP VNS 12 13 14 15 16 17 18 19 20 21 22 48-TQFP (JEDEC LQFP) 5504-CGT 10 RXT 25 23 24 QIN QO2 34 QO1 3 N/C VPD1 VNA1 RSLN IIN 35 IO2 2 N/C VPD2 VPA1 37 36 IO1 1 N/C VND1 VNA3b VNA3a 5504 DCR Direct Conversion Receiver MECHANICAL DRAWING 8.7 (0.343) 9.3 (0.366) 8.7 (0.343) 9.3 (0.366) INDEX 1 6.8 (0.267) 7.2 (0.283) 1.40 (0.055) 1.60 (0.063) 0.0 (0) 0.20 (0.008) 0.2 (0.008) Typ. 0.60 (0.024) Typ. 0.50 (0.0197) Typ. 48-Lead Thin Quad Flatpack (JEDEC LQFP) Note: Controlling dimensions are in mm PART DESCRIPTION ORDER NO. PACKAGE MARK 5504-CGT 5504-CGT 5504 DCR Direct Conversion Receiver Advanced Information: The Advanced Information data sheet is to be approved for Beta Site and advanced customer information purposes only. It is not intended to replace the electrical specification for the specific device it represents. This document will be updated and converted into a Final (Preliminary Data Sheet) upon completion of Design Engineering Validation. Design Engineering should review this documentation for its accuracy to the definition and the design goals for the product it represents. No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. 2 2 Purchase of I C components of TDK Corporation or one of its sublicensed Associated Companies conveys a license under the Philips I C 2 2 Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com 2000 TDK Semiconductor Corporation 04/20/00- rev. A 11