TI 5962-9959501Q2A

THS4031
THS4032
www.ti.com
SLOS224G – JULY 1999 – REVISED MARCH 2010
100-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
Check for Samples: THS4031, THS4032
FEATURES
1
The THS4031 and THS4032 are ultralow-voltage
noise, high-speed voltage feedback amplifiers that
are ideal for applications requiring low voltage noise,
including communications and imaging. The single
amplifier THS4031 and the dual amplifier THS4032
offer very good ac performance with 100-MHz
bandwidth (G = 2), 100-V/ms slew rate, and 60-ns
settling time (0.1%). The THS4031 and THS4032 are
unity gain stable with 275-MHz bandwidth. These
amplifiers have a high drive capability of 90 mA and
draw only 8.5-mA supply current per channel. With
–90 dBc of total harmonic distortion (THD) at f = 1
MHz and a very low noise of 1.6 nV/√Hz, the
THS4031 and THS4032 are ideally suited for
applications requiring low distortion and low noise
such as buffering analog-to-digital converters.
RELATED DEVICES
8
2
7
3
6
4
5
NULL
VCC+
OUT
NC
NC − No internal connection
THS4032
D AND DGN PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
−VCC
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN−
2IN+
Cross-Section View Showing
PowerPAD Option (DGN)
THS4031
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
NC
DESCRIPTION
1
NULL
•
NULL
IN−
IN+
VCC−
NC
•
•
•
•
THS4031
D, DGN, AND JG PACKAGE
(TOP VIEW)
NULL
•
Ultralow 1.6 nV/√Hz Voltage Noise
High Speed:
– 100-MHz Bandwidth [G = 2 (-1), –3 dB]
– 100-V/ms Slew Rate
Very Low Distortion
– THD = –72 dBc (f = 1 MHz, RL = 150 Ω)
– THD = –90 dBc (f = 1 MHz, RL = 1 kΩ)
Low 0.5-mV (Typ) Input Offset Voltage
90-mA Output Current Drive (Typical)
±5 V to ±15 V Typical Operation
Available in Standard SOIC, MSOP
PowerPAD™, JG, or FK Package
Evaluation Module Available
NC
•
•
2
NC
4
18 NC
IN−
5
17 VCC+
NC
6
16 NC
IN+
7
15 OUT
THS4051/2
70-MHz High-Speed Amplifiers
NC
8
14 NC
THS4081/2
175-MHz Low Power High-Speed Amplifiers
NC
10 11 12 13
NC
space
9
VCC−
NC
DESCRIPTION
NC
DEVICE
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2010, Texas Instruments Incorporated
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
20
I n − Current Noise − pA/ Hz
Vn − Voltage Noise − nV/ Hz
VCC = ± 15 V AND ± 5 V
TA = 25°C
10
Vn
In
1
10
100
1k
10 k
100 k
f − Frequency − Hz
AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
(1)
(2)
(3)
2
NUMBER OF
CHANNELS
PLASTIC
SMALL
OUTLINE (2) (D)
PLASTIC MSOP (2)(DGN) (3)
DEVICE
SYMBOL
CERAMIC DIP
(JG)
CHIP CARRIER
(FK)
EVALUATION
MODULE
1
THS4031CD
THS4031CDGN
TIACM
—
—
THS4031EVM
2
THS4032CD
THS4032CDGN
TIABD
—
—
THS4032EVM
1
THS4031ID
THS4031IDGN
TIACN
—
—
—
2
THS4032ID
THS4032IDGN
TIABG
—
—
—
1
—
—
—
THS4031MJG
THS4031MFK
—
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (that is, THS4031CDGNR).
The PowerPAD™ on the underside of the DGN package is electrically isolated from all other pins and active circuitry. Connection to the
PCB ground plane is recommended, although not required, as this copper plane is typically the largest copper plane on the PCB.
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
THS4031
THS4032
www.ti.com
SLOS224G – JULY 1999 – REVISED MARCH 2010
FUNCTIONAL BLOCK DIAGRAMS
Null
2
IN−
3
IN+
VCC
1
1IN−
8
−
2
−
8
1
6
OUT
1IN+
+
2IN−
3
6
−
7
2IN+
5
1OUT
+
2OUT
+
4
−VCC
Figure 1. THS4031 – Single Channel
Figure 2. THS4032 – Dual Channel
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
UNIT
33
V
VCC
Supply voltage, VCC+ to VCC–
VI
Input voltage
IO
Output current
150
mA
VIO
Differential input voltage
±4
V
±VCC
Continuous total power dissipation
See Dissipation Ratings Table
C-suffix
0 to 70
I-suffix
–40 to 85
M-suffix
–55 to 125
TA
Operating free-air
temperature
TJ
Maximum junction temperature, (any condition)
150
°C
Maximum junction temperature, continuous operation, long term reliability (2)
130
°C
Tstg
(1)
(2)
Storage temperature
°C
–65 to 150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package
300
°C
Case temperature for 60 seconds, FK package
260
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device. Does not apply to the JG package or FK package.
DISSIPATION RATINGS TABLE
PACKAGE
qJA
(°C/W)
qJC
(°C/W)
TA = 25°C,
POWER RATING
D
167 (1)
38.3
629 mW, TJ = 130°C, continuous
DGN
(1)
(2)
(2)
58.4
4.7
1.8 W, TJ = 130°C, continuous
JG
119
28
1050 mW, TJ = 150°C, continuous
FK
87.7
20
1375 mW, TJ = 150°C, continuous
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, the qJA is 95°C/W with a
power rating at TA = 25°C of 1.32 W.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3-in. × 3-in. PC. For further information, refer to
Application Information section of this data sheet.
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
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3
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
Dual supply
VCC+ and VCC– Supply voltage
MAX
±16
9
32
0
70
Single supply
C-suffix
Operating free-air
temperature
TA
NOM
±4.5
I-suffix
–40
85
M-suffix
–55
125
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
At TA = 25°C, VCC = ±15 V, and RL = 150 Ω (unless otherwise noted).
THS403xC, THS403xI
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Small-signal bandwidth (–3 dB)
BW
Bandwidth for 0.1-dB flatness
Full power bandwidth (2)
Slew rate (3)
SR
Settling time to 0.1%
tS
Settling time to 0.01%
VCC = ±15 V
Gain = –1 or 2
VCC = ±5 V
VCC = ±15 V
Gain = –1 or 2
VCC = ±5 V
VO(pp) = 20 V,
VCC = ±15 V
VO(pp) = 5 V,
VCC = ±5 V
VCC = ±15 V,
20-V step
VCC = ±5 V,
5-V step
VCC = ±15 V,
5-V step
VCC = ±5 V,
2.5-V step
VCC = ±15 V,
5-V step
VCC = ±5 V,
2.5-V step
RL = 1 kΩ
Gain = –1
Gain = –1
Gain = –1
100
90
50
45
2.3
7.2
100
80
60
45
90
80
MHz
MHz
MHz
V/ms
ns
ns
NOISE/DISTORTION PERFORMANCE
THS4031
THD
Total harmonic
distortion
VCC = ±5 V or ±15 V, VO(pp) = 2 V,
f = 1 MHz
Gain = 2
THS4032
RL = 150 Ω
–81
RL = 1 kΩ
–96
RL = 150 Ω
–72
RL = 1 kΩ
–90
dBc
Vn
Input voltage noise
VCC = ±5 V or ±15 V, f > 10 kHz
1.6
nV/√Hz
In
Input current noise
VCC = ±5 V or ±15 V, f > 10 kHz
1.2
pA/√Hz
Differential gain error
Gain = 2,
40 IRE modulation,
NTSC and PAL,
±100 IRE ramp
Differential phase error
Channel-to-channel crosstalk
(THS4032 only)
(1)
(2)
(3)
4
VCC = ±15 V
0.015%
VCC = ±5 V
0.02%
VCC = ±15 V
0.025
VCC = ±5 V
0.03
VCC = ±5 V or ±15 V, f = 1 MHz
–61
°
dBc
Full range = 0°C to 70°C for THS403xC and –40°C to 85°C for THS403xI suffix.
Full power bandwidth = slew rate / [√2 pVOC(Peak)].
Slew rate is measured from an output level range of 25% to 75%.
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
THS4031
THS4032
www.ti.com
SLOS224G – JULY 1999 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = ±15 V, and RL = 150 Ω (unless otherwise noted).
THS403xC, THS403xI
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
TA = 25°C
93
98
TA = full range
92
TA = 25°C
90
TA = full range
89
UNIT
MAX
DC PERFORMANCE
VCC = ±15 V, RL = 1 kΩ, VO = ±10 V
Open loop gain
VCC = ±5 V, RL = 1 kΩ, VO = ±2.5 V
TA = 25°C
dB
95
0.5
2
VOS
Input offset voltage
VCC = ±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
IOS
Input offset current
VCC = ±5 V or ±15 V
Offset voltage drift
VCC = ±5 V or ±15 V
TA = full range
2
mV/°C
Input offset current drift
VCC = ±5 V or ±15 V
TA = full range
0.2
nA/°C
TA = full range
mV
3
TA = 25°C
3
TA = full range
6
mA
8
TA = 25°C
30
TA = full range
250
nA
400
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
VCC = ±15 V
±13.5
±14.0
VCC = ±5 V
±3.8
±4.0
TA = 25°C
85
95
TA = full range
80
TA = 25°C
90
TA = full range
85
VCC = ±15 V, VICR = ±12 V
CMRR Common-mode rejection ratio
VCC = ±5 V, VICR = ±2.5 V
ri
Input resistance
Ci
Input capacitance
V
dB
100
2
MΩ
1.5
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VO
Output voltage swing
VCC = ±5 V
VCC = ±15 V
RL = 150 Ω
VCC = ±5 V
RL = 250 Ω
VCC = ±15 V
IO
Output current (4)
ISC
Short-circuit current (4)
VCC = ±15 V
RO
Output resistance
Open loop
VCC = ±5 V
±13
RL = 1 kΩ
RL = 20 Ω
±13.6
±3.4
±3.8
±12
±12.9
±3
±3.5
60
90
50
70
V
mA
150
mA
13
Ω
POWER SUPPLY
VCC
Supply voltage operating range
Dual supply
Single supply
VCC = ±15 V
ICC
Supply current (each amplifier)
VCC = ±5 V
PSRR
(4)
Power-supply rejection ratio
VCC = ±5 V or ±15 V
±4.5
±16.5
9
33
TA = 25°C
8.5
TA = full range
10
11
TA = 25°C
7.5
TA = full range
V
9
mA
10.5
TA = 25°C
85
TA = full range
80
95
dB
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily
loaded or shorted. See the Absolute Maximum Ratings table in this data sheet for more information.
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
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5
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = full range, VCC = ±15 V, and RL = 1 kΩ (unless otherwise noted).
THS403xC, THS403xI
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
100 (2)
120
MAX
UNIT
DYNAMIC PERFORMANCE
Unity gain bandwidth
Small-signal bandwidth (–3 dB)
BW
Bandwidth for 0.1-dB flatness
Full power bandwidth (3)
SR
Slew rate
Settling time to 0.1%
tS
Settling time to 0.01%
VCC = ±15 V,
Closed loop
VCC = ±15 V
RL = 1 kΩ
100
Gain = –1 or 2
VCC = ±5 V
VCC = ±15 V
VO(pp) = 20 V,
VCC = ±15 V
VO(pp) = 5 V,
VCC = ±5 V
VCC = ±15 V
50
VCC = ±15 V,
5-V step
VCC = ±5 V,
2.5-V step
VCC = ±15 V,
5-V step
VCC = ±5 V,
2.5-V step
MHz
45
2.3
RL = 1 kΩ
RL = 1 kΩ
MHz
90
Gain = –1 or 2
VCC = ±5 V
MHz
MHz
7.1
80 (2)
100
V/ms
60
Gain = –1
ns
45
90
Gain = –1
ns
80
NOISE/DISTORTION PERFORMANCE
RL = 150 Ω
–81
RL = 1 kΩ
–96
VCC = ±5 V or ±15 V,
f > 10 kHz
TA = 25°C
RL = 150 Ω
1.6
nV/√Hz
VCC = ±5 V or ±15 V,
f > 10 kHz
TA = 25°C
RL = 150 Ω
1.2
pA/√Hz
THD
Total harmonic distortion
VCC = ±5 V or ±15 V, VO(pp) = 2 V,
f = 1 MHz, Gain = 2, TA = 25°C
Vn
Input voltage noise
In
Input current noise
Differential gain error
Differential phase error
Gain = 2,
40 IRE modulation,
TA = 25°C
NTSC and PAL,
±100 IRE ramp,
RL = 150 Ω
VCC = ±15 V
0.015%
VCC = ±5 V
0.02%
VCC = ±15 V
0.025
VCC = ±5 V
0.03
dBc
°
DC PERFORMANCE
VCC = ±15 V, RL = 1 kΩ, VO = ±10 V
Open loop gain
VCC = ±5 V, RL = 1 kΩ, VO = ±2.5 V
TA = 25°C
93
TA = full range
92
TA = 25°C
92
TA = full range
91
TA = 25°C
98
dB
95
0.5
2
VOS
Input offset voltage
VCC = ±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
IOS
Input offset current
VCC = ±5 V or ±15 V
Offset voltage drift
VCC = ±5 V or ±15 V
TA = full range
2
mV/°C
Input offset current drift
VCC = ±5 V or ±15 V
TA = full range
0.2
nA/°C
(1)
(2)
(3)
6
TA = full range
TA = 25°C
3
3
TA = full range
TA = 25°C
6
8
30
TA = full range
250
400
mV
mA
nA
Full range = 0°C to 70°C for THS403xC and –40°C to 85°C for THS403xI suffix.
This parameter is not tested.
Full power bandwidth = slew rate / [√2 pVOC(Peak)].
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
THS4031
THS4032
www.ti.com
SLOS224G – JULY 1999 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
At TA = full range, VCC = ±15 V, and RL = 1 kΩ (unless otherwise noted).
THS403xC, THS403xI
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
VCC = ±15 V
±13.5
±14.3
VCC = ±5 V
±3.8
±4.3
TA = 25°C
85
95
TA = full range
80
TA = 25°C
90
TA = full range
85
MAX
UNIT
INPUT CHARACTERISTICS
VICR
Common-mode input voltage
range
VCC = ±15 V, VICR = ±12 V
CMRR Common-mode rejection ratio
VCC = ±5 V, VICR = ±2.5 V
ri
Input resistance
Ci
Input capacitance
V
dB
100
2
MΩ
1.5
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VO
Output voltage swing
VCC = ±5 V
VCC = ±15 V
RL = 150 Ω
VCC = ±5 V
RL = 250 Ω
VCC = ±15 V
IO
Output current (4)
ISC
Short-circuit current (4)
VCC = ±15 V
RO
Output resistance
Open loop
VCC = ±5 V
±13
RL = 1 kΩ
RL = 20 Ω
±13.6
±3.4
±3.8
±12
±12.9
±3
±3.5
60
90
50
70
V
mA
150
mA
13
Ω
POWER SUPPLY
VCC
Supply voltage operating range
Dual supply
Single supply
VCC = ±15 V
ICC
Supply current (each amplifier)
VCC = ±5 V
PSRR
(4)
Power-supply rejection ratio
VCC = ±5 V or ±15 V
±4.5
±16.5
9
33
TA = 25°C
8.5
TA = full range
10
11
TA = 25°C
7.5
TA = full range
V
9
mA
10
TA = 25°C
85
TA = full range
80
95
dB
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily
loaded or shorted. See the Absolute Maximum Ratings table in this data sheet for more information.
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
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7
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
330 Ω
330 Ω
330 Ω
_
VI1
330 Ω
_
VO1
+
CH1
150 Ω
50 Ω
VO2
VI2
+
CH2
150 Ω
50 Ω
Figure 3. THS4032 Crosstalk Test Circuit
Rg
Rf
Rg
Rf
VI
_
VI
+
50 Ω
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_
VO
+
RL
RL
Figure 4. Step Response Test Circuit
8
50 Ω
VO
Figure 5. Step Response Test Circuit
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
THS4031
THS4032
www.ti.com
SLOS224G – JULY 1999 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Input offset voltage distribution
6, 7
Input offset voltage
vs Free-air temperature
8
Input bias current
vs Free-air temperature
9
Output voltage swing
vs Supply voltage
10
Maximum output voltage swing
vs Free-air temperature
11
Maximum output current
vs Free-air temperature
12
Supply current
vs Free-air temperature
13
Common-mode input voltage
vs Supply voltage
14
Closed-loop output impedance
vs Frequency
15
Open-loop gain and phase response
vs Frequency
16
Power-supply rejection ratio
vs Frequency
17
Common-mode rejection ratio
vs Frequency
18
Crosstalk
vs Frequency
19
Harmonic distortion
vs Frequency
20, 21
Harmonic distortion
vs Peak-to-peak output voltage
22, 23
Slew rate
vs Free-air temperature
24
0.1% settling time
vs Output voltage step size
25
Small signal frequency response with varying feedback resistance
Gain = 1, VCC = ±15V, RL = 1kΩ
26
Frequency response with varying output voltage swing
Gain = 1, VCC = ±15V, RL = 1kΩ
27
Small signal frequency response with varying feedback resistance
Gain = 1, VCC = ±15V, RL = 150kΩ
28
Frequency response with varying output voltage swing
Gain = 1, VCC = ±15V, RL = 150kΩ
29
Small signal frequency response with varying feedback resistance
Gain = 1, VCC = ±5V, RL = 1kΩ
30
Frequency response with varying output voltage swing
Gain = 1, VCC = ±5V, RL = 1kΩ
31
Small signal frequency response with varying feedback resistance
Gain = 1, VCC = ±5V, RL = 150kΩ
32
Frequency response with varying output voltage swing
Gain = 1, VCC = ±5V, RL = 150kΩ
33
Small signal frequency response with varying feedback resistance
Gain = 2, VCC = ±5V, RL = 150kΩ
34
Small signal frequency response with varying feedback resistance
Gain = 2, VCC = ±5V, RL = 150kΩ
35
Small signal frequency response with varying feedback resistance
Gain = –1, VCC = ±15V, RL = 150kΩ
36
Frequency response with varying output voltage swing
Gain = –1, VCC = ±5V, RL = 150kΩ
37
Small signal frequency response
Gain = 5, VCC = ±15V, ±5V
38
Output amplitude
vs Frequency, Gain = 2, VS = ±15V
39
Output amplitude
vs Frequency, Gain = 2, VS = ±5V
40
Output amplitude
vs Frequency, Gain = –1, VS = ±15V
41
Output amplitude
vs Frequency, Gain = –1, VS = ±5V
Differential phase
vs Number of 150Ω loads
43, 44
Differential gain
vs Number of 150Ω loads
45, 46
1-V step response
vs Time
47, 48
4-V step response
vs Time
49
20-V step response
vs Time
50
Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4031 THS4032
42
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9
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE DISTRIBUTION
14
250 Samples
3 Wafer Lots
TA = 25°C
VCC = ± 15 V
10
8
6
4
2
17.5
15
12.5
10
7.5
5
2.5
0
−2
0.4
0.8
−1.6 −1.2 −0.8 −0.4
0
VIO − Input Offset Voltage − mV
0
1.2
−2
−1.6 −1.2 −0.8 −0.4
0
0.4
VIO − Input Offset Voltage − mV
Figure 6.
Figure 7.
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
0.8
1.2
3.10
−0.3
3.05
−0.35
I IB − Input Bias Current − µ A
V IO − Input Offset Voltage − mV
250 Samples
3 Wafer Lots
TA = 25°C
VCC = ± 5 V
20
Percentage of Amplifiers − %
12
Percentage of Amplifiers − %
INPUT OFFSET VOLTAGE DISTRIBUTION
22.5
VCC = ± 5 V
−0.4
−0.45
VCC = ± 15 V
−0.5
VCC = ± 15 V
3
2.95
2.90
2.85
VCC = ± 5 V
2.80
−0.55
2.75
−0.6
−40
−20
60
0
20
40
80
TA − Free-Air Temperature − °C
100
2.70
−40
−20
Figure 8.
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0
20
40
60
80
TA − Free-Air Temperature − °C
100
Figure 9.
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SLOS224G – JULY 1999 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
14
VOM − Maximum Output Voltage Swing − ± V
14
|VO | – Output Voltage Swing – ± V
TA = 25°C
12
RL = 1 KΩ
10
RL = 150 Ω
8
6
4
2
13
7
9
11
± VCC – Supply Voltage – ± V
5
12
4.5
VCC = ± 5 V
RL = 1 kΩ
4
3.5
VCC = ± 5 V
RL = 150 Ω
3
−20
60
80
0
20
40
TA − Free-Air Temperature − °C
Figure 11.
MAXIMUM OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
100
11
RL = 20 Ω
Each Amplifier
VCC = ± 15 V
Source Current
100
10
I CC − Supply Current − mA
I O − Maximum Output Current − mA
VCC = ± 15 V
RL = 250 Ω
12.5
Figure 10.
110
90
80
13
2.5
−40
15
VCC = ± 15 V
RL = 1 kΩ
13.5
VCC = ± 15 V
Sink Current
VCC = ± 5 V
Sink Current
70
VCC = ± 5 V
Source Current
VCC = ± 10 V
8
VCC = ± 5 V
7
6
60
50
−40
VCC = ± 15 V
9
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
5
−40
−20
Figure 12.
0
20
60
80
40
TA − Free-Air Temperature − °C
100
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
100
15
VIC− Common-Mode Input − ± V
13
11
9
7
5
3
5
7
Gain = 1
RF = 1 kΩ
PI = + 3 dBm
Z O− Closed-Loop Output Impedance − Ω
TA = 25°C
9
11
13
± VCC − Supply Voltage − ± V
10
1
1 kΩ
−
0.1
+
50 Ω
VI
THS403x
1000
VO
Zo =
−1
VI
(
0.01
100 k
15
VO
1 kΩ
10 M
1M
100 M
)
500 M
f − Frequency − Hz
Figure 14.
Figure 15.
OPEN-LOOP GAIN AND PHASE RESPONSE
100
45°
VCC = ± 15 V
RL = 150 Ω
80
0°
60
−45°
Phase
40
−90°
20
−135°
0
−180°
−20
100
Phase Response
Open-Loop Gain − dB
Gain
−225°
1k
10 k
100 k
1M
10 M 100 M
1G
f − Frequency − Hz
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
THS4032 − VCC+
CMRR − Common-Mode Rejection Ratio − dB
PSRR − Power-Supply Rejection Ratio − dB
120
100
THS4031 − VCC+
THS4031 − VCC−
80
60
THS4032 − VCC−
40
20
VCC = ± 15 V and ± 5 V
VCC = ± 5 V
100
VCC = ± 15 V
80
60
1 kΩ
1 kΩ
40
_
VI
VO
+
20
1 kΩ
1 kΩ
RL
150 Ω
0
0
10
100
1k
10 k
100 k
1M
10 M
10
100 M
100
1k
10 k
100 k
1M
10 M 100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 17.
Figure 18.
THS4032
CROSSTALK
vs
FREQUENCY
0
VCC = ± 15 V
PI = 0 dBm
See Figure 3
−10
Crosstalk − dB
−20
−30
−40
−50
Input = CH 2
Output = CH 1
−60
−70
Input = CH 1
Output = CH 2
−80
−90
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
vs
FREQUENCY
−40
−40
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 1 kΩ
VO(PP) = 2 V
−60
THS4031 and THS4032
Third Harmonics
−70
THS4031
Second Harmonic
−80
VCC = ± 15 V and ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
VO(PP) = 2 V
THS4031
Second Harmonic
−50
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
THS4032
Second Harmonic
−90
−100
−60
THS4032
Second Harmonic
−70
−80
−90
−100
THS4031 and THS4032
Third Harmonics
−110
100 k
−110
100 k
10 M
1M
f − Frequency − Hz
Figure 20.
Figure 21.
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
HARMONIC DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
−10
−50
THS4031 and THS4032
Third Harmonics
−30
Harmonic Distortion − dBc
Harmonic Distortion − dBc
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 150 Ω
f = 1 MHz
−20
−60
THS4032
Second Harmonic
−70
−80
THS4031
Second Harmonic
−90
VCC = ± 15 V
Gain = 5
RF = 300 Ω
RL = 1 kΩ
f = 1 MHz
−100
−40
−50
THS4032
Second Harmonic
−60
−70
−80
THS4031
Second Harmonic
−90
THS4031 and THS4032
Third Harmonics
−100
−110
−110
0
2
4
6
8
10 12 14 16 18
VO(PP) − Peak-to-Peak Output Voltage − V
20
0
2
4
6
8
10 12 14 16 18
VO(PP) − Peak-to-Peak Output Voltage − V
Figure 22.
14
10 M
1M
f − Frequency − Hz
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Figure 23.
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TYPICAL CHARACTERISTICS (continued)
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.1% SETTLING TIME
vs
OUTPUT VOLTAGE STEP SIZE
80
120
Gain = −1
RL = 150 Ω
Vcc = ± 15 V
Step = 20 V
t s − 0.1% Settling Time − ns
SR − Slew Rate − V/ µ s
110
100
90
80
Vcc = ± 5 V
Step = 4 V
70
60
Output Amplitude − dB
0
VCC = ± 5 V
50
40
VCC = ± 15 V
30
20
0
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
4
2
3
VO − Output Voltage Step Size − V
1
100
Figure 24.
Figure 25.
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
FREQUENCY RESPONSE WITH
VARYING OUTPUT VOLTAGE SWING
VCC = ±15 V,
RL = 150 W,
VO(PP) = 200 mV,
Gain = 1
−1
RF = 100 W
RF = 50 W
−2
RF = 0 W
−3
−4
−5
2
1
VCC = +15 V,
RL = 1 kW,
Gain = 1,
RF = 0 W
VO = 0.1 V(PP)
VO = 0.2 V(PP)
0
−1
−2
−3
VO = 0.4 V(PP)
VO = 0.8 V(PP)
VO = 1.6 V(PP)
−4
−5
−6
−7
100 k
5
3
RF = 200 W
Output Amplitude (Large Signal) − dB
1
60
10
50
−40
2
Gain = −1
RF = 430 Ω
70
1M
10 M
100 M
500 M
−6
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
f − Frequency − Hz
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
1
Output Amplitude − dB
0
VCC = ±15 V,
RL = 150 W,
3
RF = 200 W
VO(PP) = 200 mV,
Gain = 1
−1
Output Amplitude (Large Signal) − dB
2
FREQUENCY RESPONSE WITH
VARYING OUTPUT VOLTAGE SWING
RF = 100 W
RF = 50 W
−2
RF = 0 W
−3
−4
−5
2
1
VCC = +15 V,
RL = 150 W,
Gain = 1,
RF = 0 W
VO = 0.1 V(PP)
0
−1
−2
VO = 0.2 V(PP)
−3
VO = 0.4 V(PP)
−4
VO = 0.8 V(PP)
−6
−5
−7
100 k
−6
100 k
VO = 1.6 V(PP)
1M
10 M
100 M
500 M
1M
10 M
100 M
500 M
f − Frequency − Hz
f − Frequency − Hz
Figure 28.
Figure 29.
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
FREQUENCY RESPONSE WITH
VARYING OUTPUT VOLTAGE SWING
3
RL = 1 kW,
VO(PP) = 200 mV
Gain = 1
RF = 200 W
RF = 100 W
RF = 50 W
RF = 0 W
Output Amplitude (Large Signal) − dB
VCC = ±5 V,
2
1
VCC = 5 V,
RL = 1 kW,
Gain = 1,
RF = 0 W
VO = 0.1 V(PP)
0
−1
VO = 0.2 V(PP)
−2
VO = 0.4 V(PP)
−3
VO = 0.8 V(PP)
−4
−5
VO = 1.6 V(PP)
−6
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 30.
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Figure 31.
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SLOS224G – JULY 1999 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
FREQUENCY RESPONSE WITH
VARYING OUTPUT VOLTAGE SWING
3
VCC = ±5 V,
RF = 200 W
Output Amplitude (Large Signal) − dB
RL = 150 W,
VO(PP) = 200 mV
Gain = 1
RF = 100 W
RF = 50 W
RF = 0 W
2
1
VCC = 5 V,
RL = 150 W,
Gain = 1,
RF = 0 W
VO = 0.1 V(PP)
0
−1
VO = 0.2 V(PP)
−2
VO = 0.4 V(PP)
−3
VO = 0.8 V(PP)
−4
VO = 1.6 V(PP)
−5
−6
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 32.
Figure 33.
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
8
R F = 1 kW
RF = 300 W
RF = 100 W
VCC = ±15 V
Gain = 2
RL = 150 W
VO(PP) = 0.4 V
Output Amplitude − dB
7
RF = 1 kΩ
6
5
RF = 300 Ω
RF = 100 Ω
4
3
2
1
0
VCC = ± 5 V
Gain = 2
RL = 150 Ω
VO(PP) = 0.4 V
−1
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
SMALL SIGNAL FREQUENCY RESPONSE
WITH VARYING FEEDBACK RESISTANCE
2
2
1
RF = 1 kΩ
0
−1
Output Amplitude − dB
Output Amplitude − dB
1
RF = 360 Ω
RF = 100 Ω
−2
−3
−4
−5
−6
VCC = ± 15 V
Gain = −1
RL = 150 Ω
VO(PP) = 0.4 V
−7
100 k
1M
0
−1
RF = 100 Ω
−3
−4
−6
100 M
RF = 360 Ω
−2
−5
10 M
RF = 1 kΩ
VCC = ± 5 V
Gain = −1
RL = 150 Ω
VO(PP) = 0.4 V
−7
100 k
500 M
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 36.
Figure 37.
100 M
500 M
SMALL SIGNAL
FREQUENCY RESPONSE
16
VCC = ± 15 V
Output Amplitude − dB
14
12
10
VCC = ± 5 V
8
6
4
Gain = 5
RF = 3.9 kΩ
RL = 150 Ω
VO(PP) = 0.4 V
2
0
100 k
1M
10 M
100 M
500 M
f − Frequency − Hz
Figure 38.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
3
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL= 150 Ω
−3
−6
0
VO − Output Voltage Level − dBv
VO − Output Voltage Level − dBV
0
3
VI = 0.5 V RMS
VI = 0.25 V RMS
−9
−12
VI = 125 mV RMS
−15
−18
VI = 62.5 mV RMS
−3
−6
VI = 0.25 V RMS
−9
−12
VI = 125 mV RMS
−15
VI = 62.5 mV RMS
−18
−21
−21
−24
100 k
1M
100 M
10 M
−24
100 k
500 M
1M
f − Frequency − Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
−6
VO − Output Voltage Level − dBV
VO − Output Voltage Level − dBV
−3
VCC = ± 15 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
VI = 0.25 V RMS
−15
18
VI = 125 mV RMS
−21
−24
VI = 62.5 mV RMS
−27
−30
100 k
100 M
500 M
f − Frequency − Hz
Figure 40.
−9
−12
10 M
Figure 39.
−3
−6
VCC = 5 V
Gain = 2
RF = 300 W
RL = 150 W
VI = 0.5 V RMS
VCC = ± 5 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
VI = 0.5 V RMS
−9
−12
VI = 0.25 V RMS
−15
18
VI = 125 mV RMS
−21
−24
VI = 62.5 mV RMS
−27
1M
100 M
10 M
500 M
−30
100 k
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 41.
Figure 42.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.2°
0.25°
Gain = 2
RF = 680 Ω
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
Gain = 2
RF = 680 Ω
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
VCC = ± 5 V
0.2°
VCC = ± 5 V
0.1°
Differential Phase
Differential Phase
0.15°
VCC = ± 15 V
0.15°
VCC = ± 15 V
0.1°
0.05°
0.05°
0°
0°
1
2
3
Number of 150-Ω Loads
4
1
Figure 43.
Figure 44.
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.025°
4
0.03
Gain = 2
RF = 680 Ω
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
0.02°
Gain = 2
RF = 680 Ω
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.025
Differential Gain − %
Differential Gain − %
2
3
Number of 150-Ω Loads
VCC = ± 5 V
VCC = ± 15 V
0.015°
VCC = ± 5 V
0.02
VCC = ± 15 V
0.15
0.01°
0.01
1
3
2
Number of 150-Ω Loads
4
3
2
Number of 150-Ω Loads
1
Figure 45.
20
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4
Figure 46.
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TYPICAL CHARACTERISTICS (continued)
1-V STEP RESPONSE
1-V STEP RESPONSE
0.6
0.6
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 4
0.4
VO − Output Voltage − V
VO − Output Voltage − V
0.4
VCC = ± 5 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
See Figure 4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
t - Time - 200 ns/div
t - Time - 200 ns/div
Figure 47.
Figure 48.
4-V STEP RESPONSE
20-V STEP RESPONSE
2.5
15
2
10
VO − Output Voltage − V
VO − Output Voltage − V
1.5
1
0.5
0
−0.5
−1
−1.5
−2
VCC = ± 5 V
Gain = −1
RF = 430 Ω
RL = 150 Ω
See Figure 5
5
RL = 1 kΩ
VCC = ± 15 V
Gain = 2
RF = 330 Ω
See Figure 4
Offset For Clarity
0
−5
RL = 150 Ω
−10
−2.5
−15
t - Time - 200 ns/div
Figure 49.
t - Time - 200 ns/div
Figure 50.
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APPLICATION INFORMATION
THEORY OF OPERATION
The THS403x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high-performance amplifier that has wide bandwidth, high slew rate,
fast settling time, and low distortion. A simplified schematic is shown in Figure 51.
(7) VCC +
(6) OUT
IN − (2)
IN + (3)
(4) VCC −
NULL (1)
NULL (8)
Figure 51. THS4031 Simplified Schematic
22
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NOISE CALCULATIONS AND NOISE FIGURE
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS403x, shown in Figure 52, includes all of the noise sources as follows:
• en = Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN−
RG
Figure 52. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
Where:
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
(1)
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no + e
ni
A
V
ǒ
+ e ni 1 )
Ǔ
RF
(Noninverting Case)
RG
(2)
As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This advantage
can greatly simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, refer to the application note, Noise Analysis for High-Speed Op Amps
(SBOA066).
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Product Folder Link(s): THS4031 THS4032
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THS4031
THS4032
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OPTIMIZING FREQUENCY RESPONSE
Internal frequency compensation of the THS403x was selected to provide very wide bandwidth performance and
still maintain a very low noise floor. In order to meet these performance requirements, the THS403x must have a
minimum gain of 2 (–1). Because everything is referred to the noninverting terminal of an operational amplifier,
the noise gain in a G = –1 configuration is the same as a G = 2 configuration.
One of the keys to maintaining a smooth frequency response, and hence, a stable pulse response, is to pay
particular attention to the inverting terminal. Any stray capacitance at this node causes peaking in the frequency
response (see Figure 53 and Figure 54). Two things can be done to help minimize this effect. The first is to
simply remove any ground planes under the inverting terminal of the amplifier, including the trace that connects
to this terminal. Additionally, the length of this trace should be minimized. The capacitance at this node causes a
lag in the voltage being fed back due to the charging and discharging of the stray capacitance. If this lag
becomes too long, the amplifier will not be able to correctly keep the noninverting terminal voltage at the same
potential as the inverting terminal's voltage. Peaking and possible oscillations will then occur if this happens.
OUTPUT AMPLITUDE
vs
FREQUENCY
9
Output Amplitude − dB
8
7
4
VCC = ± 15 V
Gain = 2
RF = 300 Ω
RL = 150 Ω
VO(PP) = 0.4 V
Ci− = 10 pF
3
2
Output Amplitude − dB
10
OUTPUT AMPLITUDE
vs
FREQUENCY
6
No Ci−
(Stray C Only)
5
4
3
2
300 Ω
Ci−
300 Ω
_
+
VI
1M
Ci−= 10 pF
1
0
No Ci−
(Stray C Only)
−1
−2
−3
−4
150 Ω
50 Ω
1
0
100 k
VO
VCC = ± 15 V
Gain = −1
RF = 360 Ω
RL = 150 Ω
VO(PP) = 0.4 V
360 Ω
360 Ω
_
VI
Ci−
56 Ω
VO
+
150 Ω
−5
10 M
100 M
500 M
−6
100 k
1M
f − Frequency − Hz
10 M
100 M
500 M
f − Frequency − Hz
Figure 53.
Figure 54.
The second precaution to help maintain a smooth frequency response is to keep the feedback resistor (Rf) and
the gain resistor (Rg) values fairly low. These two resistors are effectively in parallel when looking at the ac
small-signal response. But, as can be seen in Figure 26 through Figure 37, a value too low starts to reduce the
bandwidth of the amplifier. Table 1 shows some recommended feedback resistors to be used with the THS403x.
Table 1. Recommended Feedback Resistors
24
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GAIN
Rf for VCC = ±15 V and ±5 V
1
50 Ω
2
300 Ω
–1
360 Ω
5
3.3 kΩ (low stray-c PCB only)
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Product Folder Link(s): THS4031 THS4032
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THS4032
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SLOS224G – JULY 1999 – REVISED MARCH 2010
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS403x has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the phase margin of the device leading to high-frequency ringing or oscillations. Therefore,
for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 55. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
360 Ω
360 Ω
Input
_
20 Ω
Output
THS403x
+
CLOAD
Figure 55. Driving a Capacitive Load
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THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
OFFSET NULLING
The THS403x has very low input offset voltage for a high speed amplifier. However, if additional correction is
required, the designer can make use of an offset nulling function provided on the THS4031. By placing a
potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply, the input offset
can be adjusted. This is shown in Figure 56.
VCC+
0.1 mF
3
7
+
THS4031
2
_
4
8
1 10 k Ω
0.1 mF
VCC −
Figure 56. Offset Nulling Schematic
OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 57. Output Offset Voltage Model
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SLOS224G – JULY 1999 – REVISED MARCH 2010
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer (see
Figure 58).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
R
1)
R
F
G
Ǔǒ
–3dB
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 58. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Otherwise, phase shift of the amplifier can occur.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2–
Q
)
Figure 59. Two-Pole Low-Pass Sallen-Key Filter
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THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
CIRCUIT-LAYOUT CONSIDERATIONS
In order to achieve the levels of high-frequency performance of the THS403x, it is essential that proper
printed-circuit board (PCB) high-frequency design techniques be followed. A general set of guidelines is given
below. In addition, a THS403x evaluation board is available to use as a guide for layout or for evaluating the
device performance.
• Ground planes: It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling: Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inch between the device power terminals and the ceramic capacitors.
• Sockets: Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance
in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the
printed-circuit board is the best implementation.
• Short trace runs/compact part placements: Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
• Surface-mount passive components: Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The THS403x is available in a thermally-enhanced DGN package, which is a member of the PowerPAD family of
packages. This package is constructed using a downset leadframe upon which the die is mounted [see
Figure 60(a) and Figure 60(b)]. This arrangement results in the leadframe being exposed as a thermal pad on
the underside of the package [see Figure 60(c)]. Because this thermal pad has direct thermal contact with the
die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal
pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 60. Views of Thermally-Enhanced DGN Package
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SLOS224G – JULY 1999 – REVISED MARCH 2010
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 61. PowerPAD™ PCB Etch and Via Pattern
1. Prepare the PCB with a top-side etch pattern as shown in Figure 61. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,3302 mm) in diameter.
They are kept small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS403xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS403xDGN package should connect to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area, which
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and to all the IC terminals.
8. With these preparatory steps in place, the THS403xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
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THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
The actual thermal performance achieved with the THS403xDGN in its PowerPAD™ package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches
(7,62 cm × 7,62 cm), then the expected thermal coefficient, qJA, is about 58.4°C/W. For comparison, the
non-PowerPAD™ version of the THS403x IC (SOIC) is shown. For a given qJA, the maximum power dissipation
is shown in Figure 62 and is calculated by the following formula:
ǒ
T
P
D
Where:
PD
TMAX
TA
θJA
+
–T
MAX A
q
JA
Ǔ
= Maximum power dissipation of THS403x IC (watts)
= Absolute maximum operating junction temperature (125°C)
= Free-ambient air temperature (°C)
= θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
(3)
MAXIMUM POWER DISSIPATION
vs
AMBIENT TEMPERATURE
Maximum Power Dissipation - W
3
2.5
2
DGN Package
TJ = 130 ºC
qJA = 58.4 ºC/W 2 oz.
Trace and Copper Pad
With Solder
DGN Package
SOIC Package
qJA = 158.4 ºC/W 2 oz.
High-K Test PCB
Trace and Copper Pad
qJA = 98 ºC/W
Without Solder
1.5
1
0.5
0
-40
SOIC Package
High-K Test PCB
qJA = 166.7 ºC/W
-20
0
20
40
60
80
TA - Free Air Temperature - °C
100
Results are with no air flow and PCB size = 3”× 3” (7,62 cm x 7,62 cm)
Figure 62. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments technical brief, PowerPAD™ Thermally-Enhanced Package (SLMA002). This document
can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
The next thing to be considered is package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents. Figure 63 to Figure 66 shows this effect, along with
the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, heat is generally not a
problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited in the
amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are
mounted on the PCB. The PowerPAD™ devices are extremely useful for heat dissipation. But, the device should
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SLOS224G – JULY 1999 – REVISED MARCH 2010
always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD™. The SOIC
package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper
area is placed around the device, qJA decreases and the heat dissipation capability increases. The currents and
voltages shown in these graphs are for the total package. For the dual amplifier package (THS4032), the sum of
the RMS output currents and voltages should be used to choose the proper package.
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
SO-8
qJA = 121 °C/W
High-K Test PCB
180
Maximum Output
Current Limit Line
|Iout| - Maximum RMS Output Current - mA
|Iout| Maximum RMS Output Current - mA
200
160
140
Package With
qJA <= 120 °C/W
120
100
SO-8
qJA = 167 °C/W
Low-K Test PCB
80
60
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
40
VCC = ±5 V
TJ = 130 °C
TA = 50 °C
20
0
TJ = 130 °C
TA = 50 °C
DGN Package
qJA = 58.4 °C/W
Maximum Output
Current Limit Line
100
SO-8 Package
qJA = 167 °C/W
Low-K Test PCB
SO-8 Package
qJA = 98 °C/W
High-K Test PCB
10
0
1
2
3
4
9
3
6
12
|Vout| - RMS Output Voltage - V
0
5
|Vout| - RMS Output Voltage - V
Figure 63.
15
Figure 64.
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
Package With
qJA <= 60 °C/W
180
|Iout| - Maximum RMS Output Current - mA
200
|Iout| - Maximum RMS Output Current - mA
VCC = ±15 V
Maximum Output
Current Limit Line
160
140
DGN Package
qJA = 58.4 °C/W
120
Safe
Operating
Area
100
80
THS4032
VCC = ±5 V
60
40
SO-8 Package
qJA = 167 °C/W
Low-K Test PCB
20
0
SO-8 Package
qJA = 98 °C/W
High-K Test PCB
Both Channels
TJ = 130 °C
TA = 50 °C
Both Channels
TJ = 130 °C
TA = 50° C
1
2
3
4
|Vout| - RMS Output Voltage - V
THS4032
VCC = ±15 V
DGN Package
qJA = 58.4 °C/W
100
10
SO-8 Package
qJA = 98 °C/W
High-K Test PCB
SO-8 Package
qJA = 167 °C/W
Low-K Test PCB
1
0
0
Maximum Output
Current Limits Line
5
Figure 65.
Safe
Operating
Area
3
6
9
12
|Vout| - RMS Output Voltage - V
15
Figure 66.
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THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
www.ti.com
EVALUATION BOARD
An evaluation board is available for the THS4031 (literature number SLOP203) and THS4032 (literature number
SLOP135). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 67. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, refer to the THS4031 EVM User's Guide (SLOU038) or the THS4032 EVM User's Guide (SLOU039).
To order the evaluation board, contact your local TI sales office or distributor.
VCC+
+
C3
0.1 µF
R4
301 Ω
IN +
C2
6.8 µF
NULL
R5
49.9 Ω
+
R3
49.9 Ω
OUT
THS4031
_
NULL
R2
301 Ω
+
C4
0.1 µF
C1
6.8 µF
IN −
R4
49.9 Ω
VCC −
Figure 67. THS4031 Evaluation Board
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THS4032
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SLOS224G – JULY 1999 – REVISED MARCH 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (September, 2008) to Revision G
Page
•
Changed units for input voltage noise parameter (+25°C specifications) from nA/√Hz to nV√Hz ....................................... 4
•
Changed units for input voltage noise parameter (full range of TA specifications) from nA/√Hz to nV√Hz .......................... 6
Changes from Revision E (June, 2007) to Revision F
Page
•
Deleted bullet point for Stable in Gain of 2 (–1) or greater ................................................................................................... 1
•
Editorial changes to paragraph format ................................................................................................................................ 28
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33
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9959501Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629959501Q2A
THS4031MFKB
5962-9959501QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9959501QPA
THS4031M
THS4031CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
THS4031CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
THS4031CDGN
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ACM
THS4031CDGNG4
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACM
THS4031CDGNR
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ACM
THS4031CDGNRG4
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACM
THS4031CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
THS4031CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
4031C
THS4031ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031IDGN
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ACN
THS4031IDGNG4
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACN
THS4031IDGNR
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ACN
THS4031IDGNRG4
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACN
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4031IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
4031I
THS4031MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629959501Q2A
THS4031MFKB
THS4031MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
THS4031MJG
THS4031MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9959501QPA
THS4031M
THS4032CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032C
THS4032CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032C
THS4032CDGN
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ABD
THS4032CDGNG4
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ABD
THS4032CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032C
THS4032CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032C
THS4032ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032I
THS4032IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032I
THS4032IDGN
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ABG
THS4032IDGNG4
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ABG
THS4032IDGNR
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
ABG
THS4032IDGNRG4
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ABG
THS4032IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4032I
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Oct-2013
Status
(1)
THS4032IDRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
4032I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4031, THS4031M, THS4032 :
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
• Catalog: THS4031
• Enhanced Product: THS4032-EP
• Military: THS4031M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS4031CDGNR
Package Package Pins
Type Drawing
MSOPPower
PAD
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4031CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THS4031IDGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4031IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THS4032CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THS4032IDGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4032IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4031CDGNR
MSOP-PowerPAD
DGN
8
2500
358.0
335.0
35.0
THS4031CDR
SOIC
D
8
2500
367.0
367.0
35.0
THS4031IDGNR
MSOP-PowerPAD
DGN
8
2500
358.0
335.0
35.0
THS4031IDR
SOIC
D
8
2500
367.0
367.0
35.0
THS4032CDR
SOIC
D
8
2500
367.0
367.0
35.0
THS4032IDGNR
MSOP-PowerPAD
DGN
8
2500
358.0
335.0
35.0
THS4032IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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