RFD10P03L, RFD10P03LSM,
RFP10P03L
S E M I C O N D U C T O R
10A, 30V, 0.200Ω, Logic Level
P-Channel Power MOSFET
May 1997
Features
Description
• 10A, 30V
These products are P-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
• rDS(ON) = 0.200Ω
• Temperature Compensating PSPICE Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Symbol
Ordering Information
PART NUMBER
PACKAGE
D
BRAND
RFD10P03L
TO-251AA
10P03L
RFD10P03LSM
TO-252AA
10P03L
RFP10P03L
TO-220AB
F10P03L
G
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Formerly developmental type TA49205.
Packaging
JEDEC TO-220AB
JEDEC TO-251AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
3515.1
RFD10P03L, RFD10P03LSM, RFP10P03L
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20KΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Single Pulse Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Lead Temperature for Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(0.063in (1.6mm) from case for 10s)
RFD10P03L, RFD10P03LSM,
RFP10P03L
-30
-30
±10
UNITS
V
V
V
10
See Figure 5
Refer to UIS Curve
65
0.43
-55 to 175
300
A
W
W/oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
-30
-
-
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance
(Note 1)
rDS(ON)
-1
-
-2
V
VDS = -30V,
TC = 25oC
-
-
-1
µA
VGS = 0V
TC = 150oC
-
-
-50
µA
VGS = ±10V
-
-
±100
nA
ID = 10A, VGS = -5V
-
-
0.200
Ω
0.220
Ω
ID = 10A, VGS = -4.5V
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
-
-
100
ns
-
15
-
ns
tr
-
50
-
ns
td(OFF)
-
35
-
ns
tf
-
20
-
ns
tOFF
-
-
80
ns
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 10A
RL = 1.5Ω, RGS = 5Ω,
VGS = -5V
Total Gate Charge
Qg(TOT)
VGS = 0 to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0 to -5V
Threshold Gate Charge
Qg(TH)
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance, Junction to Case
RθJC
Thermal Resistance, Junction to Ambient
RθJA
VDD = -24V,
ID ≅ 10A,
RL = 2.4Ω
-
25
30
nC
-
13
16
nC
VGS = 0 to -1V
-
1.2
1.5
nC
VDS = -25V, VGS = 0V
f = 1MHz
-
1035
-
pF
-
340
-
pF
-
35
-
pF
RFD10P03L, RFD10P03LSM
-
-
2.30
oC/W
-
-
100
oC/W
80
oC/W
RFP10P03L
Source to Drain Diode Specifications
PARAMETER
Source to Drain Forward Voltage
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = -10A
-
-
-1.5
V
ISD = -10A, dISD/dt = -100A/µs
-
-
75
ns
NOTE:
1. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
2
RFD10P03L, RFD10P03LSM, RFP10P03L
1.2
-12
1.0
-10
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves Unless Otherwise Specified
0.8
0.6
0.4
-8
-6
-4
-2
0.2
0
25
0.0
0
25
150
50
75
100
125
TC , CASE TEMPERATURE (oC)
175
50
75
100
150
125
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
ZθJC, NORMALIZED THERMAL IMPEDANCE
2.0
1.0
0.5
0.2
PDM
0.1
0.1
0.05
0.02
0.01
t1
t2
SINGLE PULSE
0.01
10-5
NOTES: DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC+ TC
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
101
100
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100
-100
IDM , PEAK CURRENT CAPABILITY (A)
ID , DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
-10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-1
-1
10ms
VDSS MAX = -30V
100ms
DC
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
VGS = -10V
VGS = -5V
-10
-5
10-5
-100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
175 – T C
I = I 25 ------------------------
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
3
101
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
-50
-25
IAS , AVALANCHE CURRENT (A)
STARTING TJ = 25oC
PULSE DURATION = 250µs,
TC = 25oC
ID, DRAIN CURRENT (A)
-10
STARTING TJ = 150oC
VGS = -10V
IF R ≠ 0
tAV = (L/R) ln [(IAS*R)/(1.3 RATED BVDSS - VDD) + 1]
-10
VGS =-3.5V
-5
VGS = -3V
0.1
1
tAV , TIME IN AVALANCHE (ms)
0
10
0
400
25oC
175oC
-10
-5
0
-1.5
-3.0
-4.5
ON RESISTANCE (mΩ)
-55oC
-15
0
300
ID = -5A
ID = -2.5A
200
100
0
-2.0
-6.0
-4.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-10.0
1.2
1.5
1.0
0.5
0
-8.0
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
VGS = -5V, ID = -10.0A
-40
-6.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
0.0
-80
TC = 25oC
ID = -20A
ID = -10A
VGS, GATE TO SOURCE VOLTAGE (V)
2.0
-5.0
-4.0
FIGURE 7. SATURATION CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE
-20
-3.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
-2.0
-1.0
NOTE: Refer to Application Notes AN9321 and AN9322.
-25
VGS = -4V
-15
If R = 0
tAV = (L) (IAS)/(1.3 RATED BVDSS - VDD)
-1
0.01
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS = -5V
-20
40
80
120
160
ID =- 250uA
1.1
1.0
0.9
0.8
-80
200
TJ , JUNCTION TEMPERATURE (oC)
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
4
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
150
1.2
VDD = -15V, ID = -10A, RL= 1.50Ω
VGS = VDS, ID = -250µA
SWITCHING TIME (ns)
NORMALIZED GATE
THRESHOLD VOLTAGE
125
1.0
0.8
tr
100
td(OFF)
75
tf
50
0.6
td(ON)
25
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
0
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1200
-5.00
-3.75
-22.5
RL = 3.0Ω
IG(REF) = -0.25mA
-15
-7.5
-2.50
0.75 BVDSS
0.75 BVDSS
0.50 BVDSS
0.50 BVDSS
0.25 BVDSS
0.25 BVDSS
-1.25
VGS = -5V
20
IG(REF)
IG(ACT)
t, TIME ( µs)
80
CISS
800
600
400
COSS
200
CRSS
0.00
0
50
VGS = 0V, f = 1MHz
1000
C, CAPACITANCE (pF)
VDD = BVDSS
VDD =BVDSS
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
-30
0
0
IG(REF)
0
IG(ACT)
NOTE: Refer to Application Notes AN7254 and AN7260.
-5
-10
-15
-20
VDS , DRAIN TO SOURCE VOLTAGE (V)
-25
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
5
RFD10P03L, RFD10P03LSM, RFP10P03L
Test Circuits and Waveforms
VDS
tAV
L
0
VARY tP TO OBTAIN
-
RG
REQUIRED PEAK IAS
+
VDD
DUT
0V
tP
VGS
VDD
IAS
IAS
0.01Ω
VDS
tP
BVDSS
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
tf
tr
0
RL
-
DUT
VGS
VDS
VDD
RG
+
10%
10%
90%
90%
VGS
0
10%
50%
50%
PULSE WIDTH
90%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
RL
VDS
Qg(TH)
0
VGS= -1V
VGS
-
VGS= -5V
-VGS
VDD
Qg(-5)
+
DUT
VGS= -10V
VDD
IG(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
6
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Electrical Model
.SUBCKT RFD10P03L 2 1 3
REV 22 Aug 96
CA 12 8 1.29e-9
CB 15 14 9.90e-10
CIN 6 8 1.01e-9
DRAIN
2
5
+
8
6
10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
RLDRAIN
RSLC1
51
+
RSLC2
5
51
EBREAK 5 11 17 18 -36.49
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EBREAK
ESLC
+
17
18
-
-
50
DPLCAP
LGATE
IT 8 17 1
LDRAIN
ESG
-
LDRAIN 2 5 1e-9
LGATE 1 9 3.40e-9
LSOURCE 3 7 3.22e-9
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
RDRAIN
9
-
20
21
16
MWEAK
6
18 +
22
DBODY
11
MMED
DBREAK
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
MMED 16 6 8 8 MmedMOD
MSTRO 16 6 8 8 MstroMOD
MWEAK 16 21 8 8 MweakMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 68.25e-3
RGATE 9 20 2.54
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RSourceMOD 25.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
-
14
+
+
EGS
19
-
IT
VBAT
5
8
EDS
-
+
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))}
.MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8)
.MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6)
.MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50)
.MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54)
.MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7)
.MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RSCLMOD RES (TC1=2e-3 TC2=0)
.MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6)
.MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40)
ENDS
For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by
William J. Hepp and C. Frank Wheatley.
7
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Thermal Model
REV 29 Aug 96
7
JUNCTION
RFP10P03L
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.45
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
RTHERM6 2 1 0.50
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
RFD10P03L, RFD10P03LSM
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.11
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
RTHERM6 2 1 0.50
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
8
CASE
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
E
ØP
A1
Q
H1
TERM. 4
D
45o
E1
D1
L1
b1
L
b
c
MIN
MAX
MIN
MAX
NOTES
A
0.170
0.180
4.32
4.57
-
A1
0.048
0.052
1.22
1.32
-
b
0.030
0.034
0.77
0.86
3, 4
b1
0.045
0.055
1.15
1.39
2, 3
c
0.014
0.019
0.36
0.48
2, 3, 4
D
0.590
0.610
14.99
15.49
-
D1
-
0.160
E
0.395
0.410
E1
-
0.030
e
60o
1
2
e1
3
e
J1
e1
LEAD NO. 1
- GATE
LEAD NO. 2
- DRAIN
LEAD NO. 3
- SOURCE
TERM. 4
- DRAIN
MILLIMETERS
SYMBOL
10.04
-
0.100 TYP
0.200 BSC
H1
0.235
0.255
J1
0.100
0.110
L
0.530
0.550
4.06
-
10.41
-
0.76
-
2.54 TYP
5
5.08 BSC
5
5.97
6.47
-
2.54
2.79
6
13.47
13.97
-
L1
0.130
0.150
3.31
3.81
2
ØP
0.149
0.153
3.79
3.88
-
Q
0.102
0.112
2.60
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 1 dated 1-93.
9
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
E
b2
H1
INCHES
A
MIN
MAX
MIN
MAX
TERM. 4
A
0.086
0.094
2.19
2.38
-
SEATING
PLANE
A1
0.018
0.022
0.46
0.55
3, 4
A1
D
b1
L1
L
c
b
1
2
3
J1
e
e1
LEAD NO. 1
- GATE
LEAD NO. 2
- DRAIN
LEAD NO. 3
- SOURCE
TERM. 4
- DRAIN
MILLIMETERS
SYMBOL
NOTES
b
0.028
0.032
0.72
0.81
3, 4
b1
0.033
0.040
0.84
1.01
3
b2
0.205
0.215
5.21
5.46
3, 4
c
0.018
0.022
0.46
0.55
3, 4
D
0.270
0.290
6.86
7.36
-
E
0.250
0.265
6.35
6.73
-
e
0.090 TYP
2.28 TYP
5
e1
0.180 BSC
4.57 BSC
5
H1
0.035
0.045
0.89
1.14
-
J1
0.040
0.045
1.02
1.14
6
L
0.355
0.375
9.02
9.52
-
L1
0.075
0.090
1.91
2.28
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-251AA outline dated 9-88.
2. Solder finish uncontrolled in this area.
3. Dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 10-95.
10
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
INCHES
A
E
A1
b2
H1
SEATING
PLANE
D
L2
1
L
3
b1
b
e
e1
b3
L3
0.094
2.19
2.38
-
0.018
0.022
0.46
0.55
4, 5
b
0.028
0.032
0.72
0.81
4, 5
b1
0.033
0.040
0.84
1.01
4
b2
0.205
0.215
5.21
5.46
4, 5
b3
0.190
-
4.83
-
2
0.46
0.55
4, 5
6.86
7.36
-
c
E
0.250
0.265
6.35
6.73
J1
e
e1
0.090 TYP
0.180 BSC
-
2.28 TYP
7
4.57 BSC
7
H1
0.035
0.045
0.89
1.14
-
J1
0.040
0.045
1.02
1.14
-
L
0.100
0.115
2.54
2.92
-
L1
0.020
-
0.51
-
4, 6
L2
0.025
0.040
0.64
1.01
3
L3
0.170
-
4.32
-
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L3 and b3 dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 6 dated 10-96.
0.090 (2.3)
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
- DRAIN
0.086
0.022
0.063 (1.6)
TERM. 4
A
A1
0.290
0.090 (2.3)
- SOURCE
NOTES
0.018
0.118 (3.0)
- GATE
MAX
0.270
BACK VIEW
LEAD NO. 3
MIN
c
0.070 (1.8)
LEAD NO. 1
MAX
D
0.265 (6.7)
0.063 (1.6)
MIN
L1
0.265
(6.7)
TERM. 4
MILLIMETERS
SYMBOL
11
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-252AA
16mm TAPE AND REEL
22.4mm
4.0mm
1.5mm
DIA. HOLE
2.0mm
13mm
1.75mm
C
L
16mm
330mm
50mm
8.0mm
16.4mm
USER DIRECTION OF FEED
COVER TAPE
GENERAL INFORMATION
1. USE "9A" SUFFIX ON PART NUMBER.
2. 2500 PIECES PER REEL.
3. ORDER IN MULTIPLES OF FULL REELS ONLY.
4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
Revision 6 dated 10-96
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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12
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