TQP3M9007 ¼W High Linearity LNA Gain Block Applications • • • • Repeaters Mobile Infrastructure LTE / WCDMA / CDMA / EDGE General Purpose Wireless Product Features • • • • • • • • • • SOT-89 Package Functional Block Diagram GND 100-4000 MHz 13 dB Gain @ 1.9 GHz 1.3 dB Noise Figure @ 1.9 GHz +41 dBm Output IP3 +23.6 dBm P1dB 50 Ohm Cascadable Gain Block Unconditionally Stable High Input Power Capability +5V Single Supply, 125 mA Current SOT-89 Package 4 1 2 3 RF IN GND RF OUT General Description Pin Configuration The TQP3M9007 is a high linearity low noise gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 13 dB gain, +41 dBm OIP3, and 1.3 dB Noise Figure while drawing 125 mA current. The device is housed in a leadfree/green/RoHS-compliant industry-standard SOT89 package. Pin # Symbol 1 3 2, 4 RF IN RF OUT GND The TQP3M9007 has the benefit of having high linearity while also providing very low noise across a broad range of frequencies. This allows the device to be used in both receive and transmit chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. The TQP3M9007 covers the 0.1 - 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. Ordering Information Part No. Description TQP3M9007 TQP3M9007-PCB High Linearity LNA Gain Block 0.5-4 GHz Evaluation Board Standard T/R size =1000 pieces on a 7” reel. Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 1 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Specifications Absolute Maximum Ratings Recommended Operating Conditions Parameter Rating Parameter Storage Temperature -55 to 150 oC RF Input Power,CW,50 Ω,T=25ºC +20 dBm Device Voltage,Vdd +7 V Vdd Tcase Tj (for>106 hours MTTF) Min Typ 3 -40 5 Max Units 5.25 +85 190 V o C o C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Operation of this device outside the parameter ranges given above may cause permanent damage. Electrical Specifications Test conditions unless otherwise noted: +25ºC, +5V supply, 50 Ω system. Parameter Conditions Operational Frequency Range Min Typical 100 Test Frequency Max Units 4000 MHz 1900 Gain 11.5 13 MHz 14.5 dB Input Return Loss 18 dB Output Return Loss 13 dB Output P1dB +23.6 dBm +41 dBm Noise Figure 1.3 dB Supply Voltage, Vdd +5 V Current, Idd 125 Thermal Resistance (jnc to case) θjc 52 Output IP3 See Note 1. +37 150 mA o C/W Notes: 1. OIP3 is measured with two tones at an output power of 4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2:1 rule gives relative value with respect to fundamental tone. Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 2 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Device Characterization Data S11 S22 1.0 0.8 0 2. 0. 4 De-embedded S-parameter Vcc = 5V 3. 0. 4 Gain and Max Stable Gain 0 3. 0 0 4. 0.2 25 0 4. 5.0 5.0 0.2 30 Swp Max 6GHz 6 0. 2. 0 6 0. 0.8 1.0 Swp Max 6GHz 10.0 5.0 4.0 3.0 2.0 1.0 0.8 0.6 0.4 0.2 10.0 0 10.0 5.0 4.0 3.0 2.0 1.0 0.8 0.6 0.4 0.2 0 20 -10.0 -4 .0 -5. 0 .0 .4 .4 -0 2.0 2.5 3.0 3.5 4.0 -2 .0 -2 Swp Min 0.01GHz -1.0 1.5 Frequency (GHz) -0.8 1.0 -0 .6 0.5 -1.0 0.0 -0.8 5 -0 .6 .0 -0 -3 Gain (dB) 2 -0. -3 .0 2 -0. 10 -4 .0 -5. 0 15 -10.0 Gain (dB) 10.0 Swp Min 0.01GHz S-Parameter Data Vdd = +5 V, Icq = 125 mA, T = +25°C, unmatched 50 ohm system, calibrated to device leads Freq (MHz) 50 100 200 400 800 1000 1200 1500 1900 2000 2200 2500 2600 3000 3500 4000 S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) -9.21 -9.18 -9.58 -11.09 -13.55 -14.69 -15.31 -16.32 -16.36 -16.44 -16.55 -16.78 -16.83 -17.62 -18.79 -20.11 -171.69 178.66 168.58 155.91 148.37 147.37 148.14 152.38 155.45 154.43 154.33 153.75 154.69 157.51 154.34 176.37 21.92 21.72 21.39 20.71 18.58 17.47 16.33 14.85 13.11 12.73 11.98 10.97 10.59 9.53 8.24 7.01 165.87 164.31 154.89 134.86 99.19 84.06 70.48 52.18 30.26 25.52 15.20 0.51 -4.70 -24.26 -48.07 -72.56 -28.66 -28.54 -28.25 -27.05 -24.58 -23.58 -22.59 -21.45 -19.96 -19.77 -19.13 -18.24 -18.14 -17.17 -16.19 -15.53 7.52 8.08 11.48 16.59 17.74 14.87 12.31 6.08 -2.85 -5.72 -12.30 -20.16 -23.60 -36.43 -53.90 -72.99 -10.26 -10.62 -10.93 -11.61 -12.39 -13.43 -13.72 -14.84 -15.21 -15.43 -16.18 -16.76 -16.24 -16.21 -14.74 -11.54 -177.68 166.81 145.14 112.74 63.78 40.99 23.70 -3.77 -32.08 -42.20 -54.41 -84.02 -91.43 -128.42 -165.72 154.74 Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 3 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Application Circuit Configuration J3 GND C3 C1 Q1 C6 C2 Notes: 1. See PC Board Layout, under Application Information section, for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. B1 (0 Ω jumper) may be replaced with copper trace in the target application layout. 4. All components are of 0603 size unless stated on the schematic. 5. C6 and L2 value are critical for linearity performance. Bill of Material: TQP3M9007-PCB Reference Desg. Value Q1 Description Manufacturer Part Number High Linearity LNA Gain Block TriQuint TQP3M9007 C2 100 pF Cap, Chip, 0603, 50V, NPO, 5% various C6 27 pF Cap, Chip, 0603, 50V, NPO, 5% various C1 0.1 uF Cap, Chip, 0603, 16V, X7R, 10% various L2 56 nH Ind, Chip, 0603, 5% various C3 4.7 uF Cap, Chip, 0603, 6.3V, X5R, 20% various B1 0Ω Res, Chip, 0603, 1/16W, 5% D1 Do Not Place Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. various various - 4 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Typical Performance TQP3M9007-PCB Test conditions unless otherwise noted: +25ºC, +5V, 125 mA, 50 Ω system. The data shown below is measured on TQP3M9007-PCB Frequency MHz 500 900 1900 2100 2600 Gain Input Return Loss Output Return Loss Output P1dB OIP3 [1] dB dB dB dBm 20 11.5 10.5 +22.9 18 14 13 +23.3 13 18 13 +23.5 12 17.5 12 +23.8 10 15.5 10.5 +24.0 dBm +39.3 +40.2 +41.1 +42.2 +42.2 dB 1.4 1.2 1.3 1.4 1.8 Noise Figure [2] Notes: 1. OIP3 measured with two tones at an output power of +4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2. Noise figure data shown in the table above is measured on evaluation board and corrected for the board loss of about 0.13 dB @ 1.9 GHz. Performance Plots Performance plots data is measured using TQP3M9007-PCB. Noise figure plot has been corrected for evaluation board loss of 0.13 dB @ 1.9 GHz. Gain vs. Frequency 24 +85°C +25°C −40°C 18 16 14 12 10 Vcc = 5V -5 Output Return Loss (dB) Input Return Loss (dB) 20 +85°C +25°C −40°C -10 -15 -20 8 6 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 1.0 1.5 2.5 3.0 -15 -20 4.0 0.0 0.5 1.0 1.5 1.0 2.5 3.0 3.5 4.0 OIP3 vs. Output Power/Tone 50 Freq. = 900 MHz 1MHz Tone Spacing Vcc = 5V 40 35 Freq. = 1900 MHz 1 MHz Tone Spacing Vcc = 5V +85°C +25°C −30 C −40°C 45 OIP3 (dBm) 1.5 2.0 Frequency (GHz) +85°C +25°C −30 C −40°C 45 OIP3 (dBm) 2.0 3.5 OIP3 vs. Output Power/Tone 50 +85°C +25°C −40°C 2.5 -10 Frequency (GHz) Noise Figure vs. Frequency 3.0 NF (dB) 2.0 Vcc = 5 V 3.5 +85°C +25°C −40°C -5 -25 0.0 Frequency (GHz) 4.0 Output Return Loss vs. Frequency 0 Vcc = 5V Vcc = 5V 22 Gain (dB) Input Return Loss vs. Frequency 0 40 35 0.5 0.0 30 0.5 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. 30 0 2 4 6 8 Output Power (dBm) - 5 of 9 - 10 12 0 2 4 6 8 10 12 Output Power/Tone (dBm) Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block OIP3 vs. Frequency 50 P1dB vs. Temperature 25 Vcc = 5V 1 MHz Tone Spacing Temp. = 25oC ACLR1 (dBc) P1dB (dBm) 40 24 Single Carrier 1+64DPCH WCDMA, PAR 10.2dB @ 0.01% probability Vcc = 5V -35 1900 MHz 900 MHz 45 OIP3 (dBm) ACLR vs. Output Power -30 Vcc = 5V 23 35 -40 -45 -50 -55 30 22 0.5 1.0 1.5 2.0 2.5 -60 -40 -20 0 Frequency (GHz) 40 60 10 80 900 MHz 1900 MHz 35 5 10 15 20 20 15 25 5 20 25 30 10 18 1900 MHz 900 MHz P1dB (dBm) OIP3 (dBm) 20 16 P1dB vs. Vdd 30 40 0 14 Pout/tone = 4dBm Tone spacing = 1MHz 1900MHz 900MHz 15 12 Output Power (dBm) OIP3 vs. Vdd 45 25 Output Power (dBm) 20 Temperature (°C) Power Compression Curve 30 900 MHz 1900 MHz 10 3 4 5 6 7 Vdd (Volts) Input Power (dBm) 3 4 5 6 7 Vdd (Volts) Idd vs Vdd 130 125 Idd (mA) 120 115 110 105 100 95 3.0 4.0 5.0 6.0 7.0 Vdd (Volts) Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 6 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Pin Description GND 4 1 2 3 RF IN GND RF OUT Pin Symbol Description 1 RF Input Input, matched to 50 ohms. External DC Block is required. 3 Vdd / RFout 2, 4 GND Paddle Output, matched to 50 ohms, External DC Block is required and supply voltage. Backside Paddle. Multiple vias should be employed to minimize inductance and thermal resistance; see page 7 for mounting configuration. Applications Information PC Board Layout Top RF layer is .014” NELCO N4000-13, єr = 3.9, 4 total layers (0.062” thick) for mechanical rigidity. Metal layers are 1-oz copper. 50 ohm Microstrip line details: width = .029”, spacing = .035” The pad pattern shown has been developed and tested for optimized assembly at TriQuint Semiconductor. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. For further technical information, Refer to www.TriQuint.com Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 7 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Mechanical Information Package Information and Dimensions Markings: Part number: 3M9007 Assembly code: ‘Y’ is last digit of part manufacture year. ‘XXX’ is lot code. 3M9007 YXXX PCB Mounting Pattern All dimensions are in millimeters (inches). Angles are in degrees. Notes: 1. Ground / thermal vias are critical for the proper performance of this device. Vias should use a .35mm (#80 / .0135”) diameter drill and have a final plated thru diameter of .25 mm (.010”). 2. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance. 3. RF trace width depends upon the PC board material and construction. 4. Use 1 oz. Copper minimum. Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 8 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9007 ¼W High Linearity LNA Gain Block Product Compliance Information Solderability ESD Information Compatible with both lead-free (maximum 260°C reflow temperature) and lead (maximum 245°C reflow temperature) soldering processes. ESD Rating: Value: Test: Standard: Class 1A Passes ≥ 250 V to < 500 V Human Body Model (HBM) JEDEC Standard JESD22-A114 ESD Rating: Value: Test: Standard: Class IV Passes ≥ 1000 V Charged Device Model (CDM) JEDEC Standard JESD22-C101 This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: • Lead Free • Halogen Free (Chlorine, Bromine) • Antimony Free • TBBP-A (C15H12Br402) Free • PFOS Free • SVHC Free MSL Rating Moisture Sensitivity Level 3 at 260°C per JEDEC standard IPC/JEDEC J-STD-020. Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: Fax: +1.503.615.9000 +1.503.615.8902 For technical questions and application information: Email: [email protected] Important Notice The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Data Sheet: Rev D 12/27/11 © 2011 TriQuint Semiconductor, Inc. - 9 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network®