N September 1996 ADVANCE INFORMATION NDS8963 Dual N-Channel Enhancement Mode Field Effect Transistor General Description Features SO-8 N-Channel enhancement mode power field effect transistors are produced using National's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. 2.5A, 30V. RDS(ON) = 0.16Ω @ VGS = 10V RDS(ON) = 0.25Ω @ VGS = 4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. _______________________________________________________________________________________________ Absolute Maximum Ratings 5 4 6 3 7 2 8 1 TA = 25°C unless otherwise note Symbol Parameter NDS8963 Units VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage ±20 V ID Drain Current - Continuous 2.5 A PD - Pulsed 7.5 Power Dissipation for Dual Operation 2 Power Dissipation for Single Operation TJ,TSTG (Note 1a) (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case 40 °C/W (Note 1) NDS8963 Rev. A ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 o TJ = 55 C V 1 µA 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA 3 V 0.16 Ω ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 2.5 A ID(on) On-State Drain Current 1 VGS = 4.5 V, ID = 2 A 0.25 VGS = 10 V, VDS = 5 V 7.5 VGS = 4.5 V, VDS = 5 V 3 A DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 1.3 A 1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. P D (t) = T J −T A R θJA (t) = T J −T A R θJC +R θCA (t) = I 2D (t) × R DS(ON)@T J Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8963 Rev. A