N CLC5622 Dual, High Output, Video Amplifier General Description Features The National CLC5622 has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (3.0mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear-phase response up to one half of the -3dB frequency. ■ ■ ■ ■ ■ ■ ■ ■ The CLC5622 offers 0.1dB gain flatness to 30MHz and differential gain and phase errors of 0.05% and 0.03°. These features are ideal for professional and consumer video applications. ■ 130mA output current 0.05%, 0.03° differential gain, phase 3.0mA/ch supply current 160MHz bandwidth (Av = +2) -90/-97dBc HD2/HD3 (1MHz) 18ns settling to 0.05% 370V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V or ±5V supplies Applications ■ The CLC5622 offers superior dynamic performance with a 160MHz small-signal bandwidth, 370V/µs slew rate and 4.4ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high-speed performance make the CLC5622 well suited for many battery-powered personal communication/computing systems. ■ ■ ■ ■ ■ ■ ■ The ability to drive low-impedance, highly capacitive loads, makes the CLC5622 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5622 will drive a 100Ω load with only -95/-95dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -72/ -77dBc second/third harmonic distortion. CLC5622 Dual, High Output, Video Amplifier June 1999 Video line driver ADSL/HDSL driver Coaxial cable driver UTP differential line driver Transformer/coil driver High capacitive load driver Portable/battery-powered applications Differential A/D driver Maximum Output Voltage vs. RL 10 Output Voltage (Vpp) 9 The CLC5622 can also be used for driving differential-input stepup transformers for applications such as Asynchronous Digital Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber Lines (HDSL). 8 VCC = ±5V 7 6 5 4 3 Vs = +5V 2 When driving the input of high-resolution A/D converters, the CLC5622 provides excellent -90/-97dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. 1 10 100 Typical Application Pinout Differential Line Driver with Load Impedance Conversion DIP & SOIC Rf2 Rg2 Vo1 Vd/2 Vin + Rt1 1/2 CLC5622 1/2 CLC5622 Rf1 Rg1 -Vd/2 + Rt2 © 1999 National Semiconductor Corporation Printed in the U.S.A. 1000 RL (Ω) Rm/2 Req 1:n RL UTP Rm/2 Vinv1 Io Zo + Vo - Vnon-inv1 -VCC +VCC Vo2 Vinv2 Vnon-inv2 http://www.national.com +5V Electrical Characteristics (A v PARAMETERS Ambient Temperature = +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) CONDITIONS CLC5622IN/IM TYP +25°C MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C UNITS FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 0.5Vpp Vo = 2.0Vpp -0.1dB bandwidth Vo = 0.5Vpp gain peaking <200MHz, Vo = 0.5Vpp gain rolloff <30MHz, Vo = 0.5Vpp linear phase deviation <30MHz, Vo = 0.5Vpp differential gain NTSC, RL = 150Ω to -1V differential phase NTSC, RL = 150Ω to -1V 130 95 30 0 0.1 0.15 0.03 0.07 100 80 25 0.5 0.4 0.3 – – 90 77 20 0.9 0.6 0.4 – – 85 75 20 1.3 0.6 0.4 – – MHz MHz MHz dB dB deg % deg TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% overshoot slew rate 4.5 17 11 280 6.0 25 15 195 6.4 40 18 165 6.8 60 18 150 ns ns % V/µs -79 -80 -66 -85 -83 -65 -76 -78 -60 -82 -81 -62 -73 -75 -58 -79 -78 -60 -73 -75 -58 -79 -78 -60 dBc dBc dBc dBc dBc dBc 3.4 6.3 8.7 -72 4.4 8.2 11.3 – 4.9 9.0 12.4 – 4.9 9.0 12.4 – nV/√Hz pA/√Hz pA/√Hz dB 1 8 6 40 6 25 48 47 3.0 4 – 18 – 14 – 45 45 3.4 6 – 22 – 16 – 43 43 3.6 6 – 24 – 17 – 43 43 3.6 mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA 0.36 1.8 4.2 0.8 4.0 1.0 4.1 0.9 100 70 0.26 2.75 4.1 0.9 3.9 1.1 4.0 1.0 80 105 0.23 2.75 4.1 0.9 3.9 1.1 4.0 1.0 65 105 0.23 2.75 4.0 1.0 3.8 1.2 3.9 1.1 40 140 MΩ pF V V V V V V mA mΩ 2V step 1V step 2V step 2V step DISTORTION AND NOISE RESPONSE 2Vpp, 1MHz 2nd harmonic distortion 2Vpp, 1MHz; RL = 1kΩ 2Vpp, 5MHz 3rd harmonic distortion 2Vpp, 1MHz 2Vpp, 1MHz; RL = 1kΩ 2Vpp, 5MHz equivalent input noise voltage (eni) >1MHz non-inverting current (ibn) >1MHz inverting current (ibi) >1MHz crosstalk (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current per channel DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC NOTES A A A A B Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings Notes A) J-level: spec is 100% tested at +25°C. B) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) Reliability Information Transistor Count MTBF (based on limited test data) http://www.national.com 98 300Mhr 2 +14V 140mA VEE to VCC +150°C -65°C to +150°C +300°C 1000V ±5V Electrical Characteristics (A v PARAMETERS Ambient Temperature = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC5622IN/IM TYP +25°C GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C UNITS FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.0Vpp Vo = 4.0Vpp -0.1dB bandwidth Vo = 1.0Vpp gain peaking <200MHz, Vo = 1.0Vpp gain rolloff <30MHz, Vo = 1.0Vpp linear phase deviation <30MHz, Vo = 1.0Vpp differential gain NTSC, RL=150Ω differential phase NTSC, RL=150Ω 160 75 30 0 0.1 0.15 0.05 0.03 135 60 25 0.5 0.2 0.3 0.1 0.06 120 57 20 0.9 0.3 0.4 – – 115 55 20 1.3 0.3 0.4 – – MHz MHz MHz dB dB deg % deg TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% overshoot slew rate 4.4 18 19 370 5.8 25 21 280 6.2 40 23 260 6.8 60 24 240 ns ns % V/µs -95 -90 -74 -95 -97 -73 -88 -88 -66 -91 -93 -64 -85 -85 -64 -88 -90 -62 -85 -85 -64 -88 -90 -62 dBc dBc dBc dBc dBc dBc 3.4 6.3 8.7 -72 4.4 8.2 11.3 – 4.9 9.0 12.4 – 4.9 9.0 12.4 – nV/√Hz pA/√Hz pA/√Hz dB 1 10 8 40 9 30 48 48 3.2 6 – 18 – 24 – 45 46 3.8 7 – 23 – 28 – 43 44 4.0 8 – 25 – 28 – 43 44 4.0 mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA 0.48 1.45 ±4.2 ±3.8 ±4.0 130 60 0.34 2.15 ±4.1 ±3.6 ±3.8 100 90 0.31 2.15 ±4.1 ±3.6 ±3.8 80 90 0.31 2.15 ±4.0 ±3.5 ±3.7 50 120 MΩ pF V V V mA mΩ 2V step 2V step 2V step 2V step DISTORTION AND NOISE RESPONSE 2Vpp, 1MHz 2nd harmonic distortion 2Vpp, 1MHz; RL = 1kΩ 2Vpp, 5MHz 3rd harmonic distortion 2Vpp, 1MHz 2Vpp, 1MHz; RL = 1kΩ 2Vpp, 5MHz equivalent input noise voltage (eni) >1MHz non-inverting current (ibn) >1MHz inverting current (ibi) >1MHz crosstalk (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current (per channel) DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC Notes Model CLC5622IN CLC5622IM CLC5622IMX Package Thermal Resistance Plastic (IN) Surface Mount (IM) B Ordering Information B) The short circuit current can exceed the maximum safe output current. Package NOTES θJC θJA 65°C/W 50°C/W 130°C/W 145°C/W 3 Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C Description 8-pin PDIP 8-pin SOIC 8-pin SOIC tape and reel http://www.national.com +5V Typical Performance (A = +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) v 0 -90 -180 Av = +5 Rf = 402Ω -270 Av = +10 Rf = 200Ω -360 -450 1M 10M 100M Av = -1 Rf = 1kΩ Gain Av = -2 Rf = 649Ω Phase Vo = 0.5Vpp 180 135 90 Av = -5 Rf = 402Ω 45 Av = -10 Rf = 200Ω RL = 1kΩ RL = 100Ω Magnitude (1dB/div) Av = +1 Rf = 1.2kΩ Phase Vo = 0.5Vpp Gain Phase 0 -180 -270 0 10M Frequency (Hz) -360 -450 100M 1M 10M Frequency (Hz) 100M Frequency (Hz) Gain Flatness & Linear Phase Frequency Response vs. Vo -90 RL = 25Ω -45 1M Phase (deg) Av = +2 Rf = 649Ω Frequency Response vs. RL Phase (deg) Vo = 0.5Vpp Gain Normalized Magnitude (1dB/div) Inverting Frequency Response Phase (deg) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response Open Loop Transimpedance Gain, Z(s) 0.3 120 220 Vo = 2Vpp Gain 0.1 Phase 0 Magnitude (dBΩ) Vo = 1Vpp 100 0.2 Phase (deg) Magnitude (1dB/div) Vo = 0.1Vpp -0.1 1M 10M 10 0 100M 20 180 Phase 80 140 60 100 40 60 20 30 10k 100k Frequency (MHz) Frequency (Hz) 2nd & 3rd Harmonic Distortion 3.6 60 20 100M 10M Frequency (Hz) Equivalent Input Noise PSRR & CMRR 1M 15 -60 CMRR 40 30 20 10 0 3.5 Inverting Current 10.8pA/√Hz 3.4 3.3 Non-Inverting Current 7.6pA/√Hz 7 3.2 Voltage 3.1nV/√Hz 3.1 3.0 1k 10k 100k 1M 10M 3 10k 100M 100k 1M -100 10M 1M 2nd & 3rd Harmonic Distortion, RL = 1kΩ 2nd, 10MHz -60 -65 -70 -70 2nd, 10MHz -80 2nd, 1MHz 0.5 1 1.5 2 2.5 0 Output Impedance vs. Frequency 1 1.5 2 2.5 IBI, IBN, VIO vs. Temperature -1.5 Offset Voltage VIO (mV) 40 30 20 10 4 IBI 1.0 0.5 3 2 VIO 0 1 IBN -0.5 0 -1 0 1k 10k 100k 1M Frequency (Hz) 4 10M 100M -1 -60 -20 20 60 Temperature (°C) 100 140 IBI, IBN (µA) Output Impedance (Ω) 0.5 Output Amplitude (Vpp) Large Signal Output Voltage (0.5V/div) 3rd, 1MHz Output Amplitude (Vpp) 50 http://www.national.com 2nd, 1MHz -120 0 Large & Small Signal Pulse Response Time (10ns/div) -90 -110 -100 2.5 Output Amplitude (Vpp) Small Signal 2nd, 10MHz -80 -100 3rd, 1MHz 3rd, 1MHz 2 3rd, 10MHz -70 -90 2nd, 1MHz 1.5 -60 Distortion (dBc) Distortion (dBc) -55 1 10M Frequency (Hz) 3rd, 10MHz 0.5 -90 -60 3rd, 10MHz 0 2nd RL = 100Ω -50 -45 -80 -80 3rd RL = 1kΩ -50 -75 2nd RL = 1kΩ 2nd & 3rd Harmonic Distortion, RL = 100Ω 2nd & 3rd Harmonic Distortion, RL = 25Ω -40 -50 -70 Frequency (Hz) Frequency (Hz) Distortion (dBc) 11 3rd RL = 100Ω Distortion (dBc) Noise Voltage (nV/√Hz) 50 Noise Current (pA/√Hz) PSRR & CMRR (dB) Vo = 2Vpp PSRR Phase (deg) Magnitude (0.1dB/div) Gain ±5V Typical Performance (A = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) v Av = +1 Rf = 1.2kΩ 0 -45 -90 Av = +5 Rf = 402Ω -135 Av = +10 Rf = 200Ω -180 -225 1M 10M 100M Av = -2 Rf = 649Ω Gain Av = -1 Rf = 1.2kΩ Phase 180 135 90 Av = -5 Rf = 500Ω 45 Av = -10 Rf = 500Ω Gain RL = 100Ω Phase 0 -90 -180 RL = 25Ω -270 -360 0 -450 -45 1M 10M Frequency (Hz) 1M 100M 10M 100M Frequency (Hz) Frequency (Hz) Frequency Response vs. Vo RL = 1kΩ Vo = 1.0Vpp Magnitude (1dB/div) Normalized Magnitude (1dB/div) Gain Vo = 1.0Vpp Phase (deg) Av = +2 Rf = 649Ω Phase (deg) Vo = 1.0Vpp Phase Frequency Response vs. RL Inverting Frequency Response Phase (deg) Normalized Magnitude (1dB/div) Frequency Response Gain Flatness & Linear Phase Small Signal Pulse Response 0.3 Vo = 5Vpp Vo = 2Vpp 0.2 Gain 0.1 Phase Av = +2 Amplitude (200mV/div) Magnitude (0.1dB/div) Vo = 1Vpp Phase (deg) Magnitude (1dB/div) Vo = 0.1Vpp 0 Av = -2 -0.1 10M 0 100M 10 5 Frequency (Hz) 15 20 25 Time (10ns/div) 30 Frequency (MHz) Differential Gain & Phase Large Signal Pulse Response 2nd & 3rd Harmonic Distortion 0.1 0.01 0 Gain Pos Sync Gain (%) -0.01 -0.2 -0.02 Phase Neg Sync -0.3 -0.03 Gain Neg Sync -0.4 -0.04 Phase Pos Sync -0.5 -0.06 1 2 3 -70 2nd RL = 1kΩ -80 2nd RL = 100Ω -90 -0.05 -0.6 Time (10ns/div) 3rd RL = 100Ω -60 -0.1 Av = -2 Vo = 2Vpp 0 Phase (deg) Amplitude (0.5V/div) Av = +2 -50 Distortion (dBc) 1M 3rd RL = 1kΩ -100 4 1M 10M Number of 150 Ω Loads 2nd & 3rd Harmonic Distortion, RL = 25Ω Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 100Ω -40 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 -60 3rd, 10MHz 2nd, 10MHz -70 2nd, 1MHz -80 -70 2nd, 10MHz -80 1 2 3 4 5 -90 0.5 1 1.5 2 2.5 0.1 0 -0.05 -0.1 0.1 0.05 0 -0.05 -0.1 -0.2 -0.2 10000 3 4 5 IBI, IBN, VOS vs. Temperature -0.15 -0.15 2 10 4 IBI 3 2 6 2 VOS 1 -2 IBN 0 1µ 10µ 100µ 1m Time (s) 5 10m 100m IBI, IBN (µA) 0.05 1 Output Amplitude (Vpp) Offset Voltage VOS(mV) 0.15 Vo (% Output Step) 0.15 1000 3rd, 1MHz 0 Long Term Settling Time 0.2 Time (ns) 2nd, 1MHz Output Amplitude (Vpp) Short Term Settling Time 100 2nd, 10MHz -80 -120 0 0.2 10 -70 -110 Output Amplitude (Vpp) 1 3rd, 10MHz 3rd, 1MHz -100 0 -60 -100 2nd, 1MHz -90 3rd, 1MHz -90 Vo (% Output Step) Distortion (dBc) 3rd, 10MHz -60 Distortion (dBc) Distortion (dBc) -50 -6 -100 -50 0 50 100 150 Temperature (°C) http://www.national.com ±5V Typical Channel Matching Performance (A Channel Matching v = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) Input Referred Crosstalk Pulse Crosstalk -20 Vo = 1Vpp Active Channel Amplitude (0.2V/div) Channel 1 Magnitude (dB) Magnitude (0.5dB/div) Channel 2 -40 -50 -60 -70 Inactive Output Channel Inactive Channel Amplitude (20mV/div) Active Output Channel -30 -80 -90 1M 10M 100M 10M 1M Frequency (Hz) Time (10ns/div) 100M Frequency (Hz) CLC5622 OPERATION The CLC5622 is a current feedback amplifier built in an advanced complementary bipolar process. The CLC5622 operates from a single 5V supply or dual ±5V supplies. Operating from a single supply, the CLC5622 has the following features: ■ ■ ■ Vo = Vin Av Rf 1+ Z(jω ) Equation 1 where: ■ Provides 100mA of output current while consuming 15mW of power Offers low -80/-83dB 2nd and 3rd harmonic distortion Provides BW > 80MHz and 1MHz distortion < -75dBc at Vo = 2Vpp ■ ■ ■ The CLC5622 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC5622’s open loop transimpedance gain Z( jω ) is the loop gain Rf The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: Current Feedback Amplifiers Some of the key features of current feedback technology are: ■ Independence of AC bandwidth and voltage gain ■ Inherently stable at unity gain ■ Adjustable frequency response with feedback resistor ■ High slew rate ■ Fast settling ■ ■ ■ ■ ■ Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Refer to the Feedback Resistor Selection section for more details on selecting a feedback resistor value. CLC5622 DESIGN INFORMATION Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5622 is typically +0.8V to http://www.national.com 6 VCC DC Coupled Single Supply Operation Figures 1 and 2 show the recommended non-inverting and inverting configurations for input signals that remain above 0.8V DC. 6.8µF + VCC 2 VCC Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. Vin 6.8µF 3 1/2 CLC5622 2 Rt Vcm - 4 RL low frequency cutoff = Vcm R Vo = A v = 1+ f Vin Rg Vin Vcm 2 1/2 CLC5622 - 4 1 Vo Rf 1 2πR gC c Dual Supply Operation The CLC5622 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6. VCC 6.8µF VCC + 6.8µF + + 8 0.1µF 1/2 CLC5622 - Rg 4 Vo 1 Vin RL Rf 3 Rt 2 + Rt 8 - 1 Vo Rf 4 0.1µF Rg R Vo = Av = − f Vin Rg 0.1µF 1/2 CLC5622 Vcm Vcm 0.1µF Figure 4: AC Coupled Inverting Configuration Figure 1: Non-Inverting Configuration Rb 2 8 R Vo = Vin − f + 2.5 Rg Vo 1 Rf Vcm 3 Rg + R Rg Note: Rb, provides DC bias for non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. 3 0.1µF 8 + Cc Vin + R Select Rt to yield desired Rin = Rt || Rg R Vo = A v = 1+ f Vin Rg + 6.8µF VEE Figure 2: Inverting Configuration Figure 5: Dual Supply Non-Inverting Configuration AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + Rb 3 VCC 2 6.8µF + Vin R Cc 3 VCC 2 R Vo = Vin 1 + f + 2.5 R g low frequency cutoff = R 2 + 8 4 1 - 4 0.1µF 1 Rf 0.1µF Vo Vo Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt || Rg. + R Vo = Av = − f Vin Rg Rf Rg C 1 R , where: Rin = 2πRinC c 2 Rg 8 1/2 CLC5622 Rt 0.1µF 1/2 CLC5622 - Vin + 6.8µF VEE Figure 6: Dual Supply Inverting Configuration R >> R source Figure 3: AC Coupled Non-Inverting Configuration 7 http://www.national.com Figure 8 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Feedback Resistor Selection The feedback resistor, Rf, affects the loop gain and frequency response of a current feedback amplifier. Optimum performance of the CLC5622, at a gain of +2V/V, is achieved with Rf equal to 750Ω. The frequency response plots in the Typical Performance sections illustrate the recommended Rf for several gains. These recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be adjusted to optimize the frequency response. ■ ■ Non-inverting gain applications: ■ ■ ■ Decrease Rf to peak frequency response and extend bandwidth Increase Rf to roll off frequency response and compress bandwidth R1 V2 +- ■ ■ Magnitude (1dB/div) R7 Rf Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. Power Dissipation Follow these steps to determine the power consumption of the CLC5622: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po CL = 10pF Rs = 68.1Ω CL = 100pF Rs = 17.4Ω CL = 1000pF Rs = 6.7Ω Rs The maximum power that the DIP and SOIC packages can dissipate at a given temperature is illustrated in Figure 9. The power derating curve for any CLC5622 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA where 1k 1k 100M Frequency (Hz) Figure 7: Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. http://www.national.com Vo The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Vo = 1Vpp 10M - Z0 R6 Inverting gain applications: Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5622 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 7, gives the recommended series resistance value for optimum flatness at various capacitive loads. 1M Rg 1/2 CLC5622 Figure 8: Transmission Line Matching Load Termination The CLC5622 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. CL Z0 C6 + R5 ■ 1k R3 R2 R4 Unity Gain Operation The recommended Rf for unity gain (+1V/V) operation is 1.2kΩ. Rg is left open. Parasitic capacitance at the inverting node may require a slight increase in Rf to maintain a flat frequency response. - Z0 V1 +- As a rule of thumb, if the recommended Rf is doubled, then the bandwidth will be cut in half. + Connect Rg directly to ground. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) 8 1.0 ■ IM Power (W) 0.8 IN ■ 0.6 ■ The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. 0.4 0.2 0 -40 -20 0 Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations 20 40 60 80 100 120 140 160 180 Ambient Temperature (°C) Figure 9: Power Derating Curves Application Circuits Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC5622 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. Single Supply Cable Driver The typical application shown below shows one of the CLC5622 amplifiers driving 10m of 75Ω coaxial cable. The CLC5622 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: ■ ■ ■ ■ ■ 6.8µF + Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Vin ■ ■ 5kΩ 3 5kΩ 2 + 8 0.1µF 1/2 CLC5622 - 4 75Ω 1 1kΩ 10m of 75Ω Coaxial Cable 0.1µF Vo 75Ω 1kΩ 0.1µF Figure 10: Single Supply Cable Driver Vin = 10MHz, 0.5Vpp Evaluation Board Information A data sheet is available for the CLC730038/ CLC730036 evaluation boards. The evaluation board data sheet provides: ■ 0.1µF 100mV/div ■ +5V Evaluation board schematics Evaluation board layouts General information about the boards 20ns/div Figure 11: Response After 10m of Cable The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Single Supply Lowpass Filter Figures 12 and 13 illustrate a lowpass filter and design equations. The circuit operates from a single supply of +5V. The voltage divider biases the non-inverting input to 2.5V. And the input is AC coupled to prevent the need for level shifting the input signal at the source. Use the design equations to determine R1, R2, C1, and C2 based on the desired Q and corner frequency. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: 9 http://www.national.com Differential Line Driver With Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 15, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5622’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5622. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. +5V 0.1µF 5kΩ Vin 0.1µF R1 R2 3 + 158Ω 158Ω 5kΩ C2 100pF 8 1/2 CLC5622 2 - 4 C1 0.1µF 1 Rf Vo 100Ω 1kΩ 1.698kΩ Rg 0.1µF Figure 12: Lowpass Filter Topology Rf2 Rg2 Vd/2 Vin R Gain = K = 1 + f Rg + 1/2 CLC5622 Rt1 1/2 CLC5622 Rf1 Corner frequency = ω c = 1 R1R 2C1C2 Rg1 -Vd/2 Rm/2 Io 1:n Zo Req + RL UTP + Vo - Rm/2 Rt2 1 Q= R 2C 2 + R1C1 Figure 15: Differential Line Driver wtih Load Impedance Conversion R1C2 R1C1 + (1− K) R 2C1 R 2C 2 For R1 = R 2 = R and C1 = C2 = C 1 RC Vd R R = 2 ⋅ 1 + f1 = 2 ⋅ f2 Vin R R g1 g2 1 (3 − K) Make the best use of the CLC5622’s output drive capability as follows: ωc = Q= Set up the CLC5622 as a difference amplifier: Rm + Req = Figure 13: Design Equations This example illustrates a lowpass filter with Q = 0.707 and corner frequency fc = 10MHz. A Q of 0.707 was chosen to achieve a maximally flat, Butterworth response. Figure 14 indicates the filter response. 2 ⋅ Vmax Imax where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Magnitude (dB) Match the line’s characteristic impedance: 3 0 -3 -6 -9 -12 RL = Z o Rm = Req n= -15 -18 -21 -24 Select the transformer so that it loads the line with a value very near Zo over frequency range. The output impedance of the CLC5622 also affects the match. With an ideal transformer we obtain: -27 -30 1M 10M 100M Frequency (Hz) Figure 14: Lowpass Response http://www.national.com RL Req Return Loss = −20 ⋅ log10 10 n2 ⋅ Z o(5622) ( jω ) ,dB Zo where Zo(5622)(jω) is the output impedance of the CLC5622 and |Zo(5622)(jω)| << Rm. The receiver output voltages are: VoutA(B) ≈ VinA(B) ⋅ A + The load voltage and current will fall in the ranges: Vo ≤ n ⋅ Vmax Io ≤ Imax n VinB(A) Z o(5622) (jω ) R ⋅ 1 − f2 + 2 Rm1 R g2 where A is the attenuation of the cable, Zo(5622)(jω) is the output impedance of the CLC5622 (see the Closed-Loop Output Resistance plot), and | Zo(5622)(jω) | << Rm1. The CLC5622’s high output drive current and low distortion make it a good choice for this application. We selected the component values as follows: Rf1 = 1.2kΩ, the recommended value for CLC5622 at unity gain ■ Rm1 = Zo = 50Ω, the characteristic impedance of the transmission line ■ Rf2 = Rg2 = 750Ω ≥ Rm1, the recommended value for the CLC5622 at Av = 2 ■ Full Duplex Cable Driver The circuit shown in Figure 16 below, operates as a full duplex cable driver which allows simultaneous transmission and reception of signals on one transmission line. The circuit on either side of the transmission line uses are CLC5622 as a cable driver, and the second CLC5622 as a receiver. VoA is an attenuated version of VinA, while VoB is an attenuated version of VinB. ■ R t2 = (R f2 || R g2 ) – Rm1 = 25Ω 2 These values give excellent isolation from the other input: VinA Rt1 + Rm1 1/2 CLC5622 Z0 Rm1 + 1/2 CLC5622 - - VinB VoA(B) Rt1 VinB(A) Rf1 Rg2 Rf2 1/2 CLC5622 + Rf1 Rg2 - VoB The CLC5622 provides large output current drive, while consuming little supply current, at the nominal bias point. It also produces low distortion with large signal swings and heavy loads. These features make the CLC5622 an excellent choice for driving transmission lines. Rf2 - Rt2 Rt2 ≈ −38dB, f = 5.0MHz 1/2 CLC5622 VoA + Figure 16: Full Duplex Cable Driver Rm1 is used to match the transmission line. Rf2 and Rg2 set the DC gain of the CLC5622, which is used in a difference mode. Rt2 provides good CMRR and DC offset. The transmitting CLC5622’s are shown in a unity gain configuration because they consume the least power of any gain, for a given load. For proper operation we need Rf2 = Rg2. 11 http://www.national.com CLC5622 Dual, High Output, Video Amplifier Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12