CYPRESS CY7B995AXC

RoboClock®, CY7B995
2.5/3.3V 200-MHz High-Speed
Multi-Phase PLL Clock Buffer
Features
Description
■
2.5V or 3.3V operation
■
Split output bank power supplies
■
Output frequency range: 6 MHz to 200 MHz
The CY7B995 RoboClock® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of high
performance computer and communication systems.
■
45 ps typical cycle-cycle jitter
■
± 2% max output duty cycle
■
Selectable output drive strength
■
Selectable positive or negative edge synchronization
■
Eight LVTTL outputs driving 50 Ω terminated lines
■
LVCMOS/LVTTL over-voltage tolerant reference input
■
Selectable phase-locked loop (PLL) frequency range and lock
indicator
■
Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
■
(1-6, 8, 10, 12) x multiply and (1/2,1/4)x divide ratios
■
Spread-Spectrum compatible
■
Power down mode
■
Selectable reference divider
■
Industrial temperature range: –40°C to +85°C
■
44-pin TQFP package
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Any one of the outputs can be connected to
feedback to achieve different reference frequency multiplication,
and divide ratios and zero input-output delay.
The device also features split output bank power supplies, which
enable the user to run two banks (1Qn and 2Qn) at a power
supply level, different from that of the other two banks (3Qn and
4Qn). The three-level PE/HD pin also controls the synchronization of the output signals to either the rising, or the falling edge
of the reference clock and selects the drive strength of the output
buffers. The high drive option (PE/HD = MID) increases the
output current from ± 12 mA to ± 24 mA.
Logic Block Diagram
TEST PE/HD
PD#/DIV
FS VDDQ1
3
3
3
/R
REF
3
LOCK
PLL
FB
/N
3
3
DS1:0
3
1F1:0
3
1Q0
Phase
Select
1Q1
2Q0
3
2F1:0
3
3
3F1:0
3
Phase
Select
2Q1
3Q0
Phase
Select
and /K
3Q1
VDDQ3
3
4F1:0
3
4Q0
Phase
Select
and /M
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07337 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 27, 2007
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RoboClock®, CY7B995
Pinouts
1F1
VSS
TES
T
2F1
2F0
FS
VDD
REF
3F0
3F1
4F0
Figure 1. Pin Diagram - 44 Pin TQFP Package Top view
44 43 42 41 40 39 38 37 36 35 34
4F1 1
sOE# 2
PD#/DIV 3
PE/HD 4
VDDQ4 5
VDDQ4 6
4Q1 7
4Q0 8
VSS 9
VSS 10
VSS 11
32 DS1
31 DS0
30 LOCK
29 VDDQ1
CY7B995
28 VDDQ1
27 1Q0
26 1Q1
25 VSS
24 VSS
23 VSS
2Q1
2Q0
VSS
VDD
VDDQ1
VDDQ3
FB
3Q0
VDDQ3
3Q1
VSS
12 13 14 15 16 17 18 19 20 21 22
Document #: 38-07337 Rev. *D
33 1F0
Page 2 of 13
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RoboClock®, CY7B995
Table 1. Pin Definitions - 44 Pin TQFP Package
Pin
Name
IO[1]
Type
Description
39
REF
I
LVTTL/LVCMOS
Reference Clock Input.
17
FB
I
LVTTL
Feedback Input.
37
TEST
I
3-Level
When MID or HIGH, disables PLL[3]. REF goes to all outputs. Set LOW
for normal operation.
2
sOE#
I, PD LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
4
PE/HD
I, PU 3-Level
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength. When LOW/HIGH, the outputs are synchronized with the
negative/positive edge of the reference clock respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. See Table 10 on page 5.
34, 33, 36, 35, nF[1:0]
43, 42, 1, 44
I
3-Level
Selects Frequency and Phase of the Outputs. See Table 4, Table 5,
Table 6, Table 8, and Table 9 on page 4.
41
FS
I
3-Level
Selects VCO Operating Frequency Range. See Table 7 on page 4.
26,27,20,21,
13,14,7,8
nQ[1:0]
O
LVTTL
Four banks of two outputs. See Table 6 on page 4 for frequency
settings.
32, 31
DS[1:0]
I
3-Level
Selects Feedback Divider. See Table 3 on page 4.
3
PD#/DIV
30
LOCK
5,6
VDDQ4[2] PWR Power
Power supply for Bank 4 Output Buffers. See Table 11 on page 5 for
supply level constraints.
15,16
VDDQ3 [2] PWR Power
Power supply for Bank 3 Output Buffers. See Table 11 on page 5 for
supply level constraints.
19,28,29
VDDQ1[2]
PWR Power
Power supply for Bank 1 and Bank 2 Output Buffers. See Table 11 on
page 5 for supply level constraints.
18,40
VDD[2]
PWR Power
Power supply for the Internal Circuitry. See Table 11 on page 5 for
supply level constraints.
PWR Power
Ground
9-12, 22-25, 38 VSS
I, PU 3-Level
O
LVTTL
Power down and Reference Divider Control. When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See Table 2
for settings.
PLL Lock Indication Signal. HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
Device Configuration
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 3 on page 4, and the reference input divider is controlled
by the 3-level PD#/DIV pin as indicated in Table 2.
Table 2. Reference Divider Settings
PD#/DIV
R–Reference Divider
H
1
M
2
L[4]
N/A
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic is cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. When PD#/DIV = LOW, the device enters power down mode.
Document #: 38-07337 Rev. *D
Page 3 of 13
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RoboClock®, CY7B995
Table 3. Feedback Divider Settings
Input
DS[1:0] N-Feedback
Divider
Configuration
Permitted Output Divider
Connected to FB
LL
2
1 or 2
LM
3
1
LH
4
1,2 or 4
ML
5
1 or 2
MM
1
1,2 or 4
MH
6
1 or 2
HL
8
1 or 2
HM
10
1
HH
12
1
4Qn
Output Frequency
1Q[0:1] and
2Q[0:1][6]
3Q[0:1]
4Q[0:1]
(N / R) x M x (N / R) x (M / (N / R) x FREF
FREF
K) x FREF
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that corresponds to each FS level is given in Table 7.
Table 7. Frequency Range Select
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in Table 4 and
Table 5, respectively.
Table 4. Output Divider Settings – Bank 3
FS
PLL Frequency Range
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
Selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the tU value is: tU = 1 / (fNOM x MF)
3F[1:0]
K - Bank3 Output Divider
LL
2
where MF is a multiplication factor which is determined by the FS
setting as indicated in Table 8.
HH
4
Table 8. MF Calculation
Other[5]
1
Table 5. Output Divider Settings – Bank 4
4F[1:0]
M- Bank4 Output Divider
LL
2
Other[5]
1
Table 6. Output Frequency Settings.
Configuration
FB Input
Connected to
1Qn or 2Qn
Output Frequency
1Q[0:1] and
2Q[0:1][6]
3Q[0:1]
FS
MF
fNOM at which tU is 1.0 ns (MHz)
L
32
31.25
M
16
62.5
H
8
125
Table 9. Output Skew Settings
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in Table 6.
3Qn
FB Input
Connected to
4Q[0:1]
(N / R) x FREF (N / R) x (1 / (N / R) x (1 /
K) x FREF
M) x FREF
(N / R) x K x (N / R) x FREF (N / R) x (K /
FREF
M) x FREF
nF[1:0]
Skew
(1Q[0:1],2Q[0:1])
Skew
(3Q[0:1])
Skew
(4Q[0:1])
LL[7]
–4tU
Divide By 2
Divide By 2
LM
–3tU
–6tU
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
+1tU
+2tU
+2tU
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide By 4
Inverted[8]
Notes
5. These states are used to program the phase of the respective banks. See Table 8 and Table 9.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See Table 7.
Document #: 38-07337 Rev. *D
Page 4 of 13
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RoboClock®, CY7B995
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 10 on page 5. Refer to the AC Timing Definitions section
for a description of input-to-output and output-to-output phase
relationships.
Table 11. Power Supply Constraints
Table 10. PE/HD Settings
VDD
VDDQ1[10]
VDDQ3[10]
VDDQ4[10]
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
2.5V
Governing Agencies
PE/HD
Synchronization
Output Drive Strength[9]
L
Negative
Low Drive
M
Positive
High Drive
The following agencies provide specifications that apply to the
CY7B995. The agency name and relevant specification is listed
below.
H
Positive
Low Drive
Table 12. Governing Agencies and Specifications
Agency Name
The CY7B995 features split power supply buses for Banks 1 and
2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V
and 2.5V output signals from one device. The core power supply
(VDD) must be set at a level that is equal to or higher than any of
the output power supplies.
Specification
JEDEC
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jiter Specs)
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1
(Therma Theta JC)
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
2.25
2.75
V
2.97
3.63
V
VSS – 0.3
–
V
VDD + 0.3
V
5.5
V
VDD
Operating Voltage
Functional @ 2.5V ± 5%
VDD
Operating Voltage
Functional @ 3.3V ± 10%
VIN(MIN)
Input Voltage
Relative to VSS
VIN(MAX)
Input Voltage
Relative to VDD
–
VREF(MAX)
Reference Input Voltage
VDD = 3.3V
VREF(MAX)
Reference Input Voltage
VDD = 2.5V
4.6
V
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
–
155
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
42
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
74
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
–
V
UL-94
Flammability Rating
@1/8 in.
MSL
Moisture Sensitivity Level
FIT
Failure in Time
2000
V–0
1
Manufacturing Testing
10
ppm
Notes
7. LL disables outputs if TEST = MID and sOE# = HIGH.
8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
9. Please refer to “DC Parameters” section for IOH/IOL specifications.
10. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
Document #: 38-07337 Rev. *D
Page 5 of 13
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RoboClock®, CY7B995
.
DC Specifications at 2.5V
Parameter
Description
Condition
VDD
2.5 Operating Voltage
2.5V ± 5%
VIL
Input LOW Voltage
REF, FB, and sOE# Inputs
VIH
Input HIGH Voltage
VIHH
[11]
Input HIGH Voltage
3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV,
PE/HD). (These pins are normally wired to VDD, GND, or
unconnected)
VIMM[11]
Input MID Voltage
VILL[11]
Input LOW Voltage
IIL
Input Leakage Current
I3
3-Level Input DC Current HIGH, VIN = VDD
VIN = VDD/GND,VDD = Max; (REF and FB Inputs)
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
Min
Max
Unit
2.375
2.625
V
–
0.7
V
1.7
–
V
VDD –
–0.4
–
V
VDD/2
– 0.2
VDD/2
+ 0.2
V
–
0.4
V
–5
5
μA
–
200
μA
–50
50
μA
–200
–
μA
IPU
Input Pull-Up Current
VIN = VSS, VDD = Max
–25
–
μA
IPD
Input Pull-Down Current
VIN = VDD, VDD = Max, (sOE#)
–
100
μA
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 20 mA (PE/HD = MID),(nQ[0:1])
–
0.4
V
IOL = 2 mA (LOCK)
VOH
Output HIGH Voltage
0.4
V
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
2.0
–
V
IOH = –20 mA (PE/HD = MID),(nQ[0:1])
2.0
–
V
IOH = –2 mA (LOCK)
2.0
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW,
Outputs Not Loaded
IDDPD
Power down Current
PD#/DIV, sOE# = LOW
Test,nF[1:0],DS[1:0] = HIGH; VDD = Max
IDD
Dynamic Supply Current
At 100 MHz
CIN
Input Pin Capacitance
Document #: 38-07337 Rev. *D
V
–
2
mA
10(typ.)
25
μA
150
mA
4
pF
Page 6 of 13
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RoboClock®, CY7B995
DC Specifications at 3.3V
Parameter
Description
Condition
VDD
3.3 Operating Voltage
3.3V ± 10%
VIL
Input LOW Voltage
REF, FB and sOE# Inputs
VIH
Input HIGH Voltage
VIHH[11]
Input HIGH Voltage
VIMM[11]
Input MID Voltage
VILL[11]
Input LOW Voltage
IIL
Input Leakage Current
VIN = VDD/GND,VDD = Max
(REF and FB inputs)
I3
3-Level Input DC Current
HIGH, VIN = VDD
Min
Max
2.97
3.63
V
–
0.8
V
2.0
–
3-Level Inputs
VDD–
–
(TEST, FS, nF[1:0], DS[1:0],PD#/DIV, PE/HD); (These pins –0.6
are normally wired to VDD,GND or unconected
VDD/2 – VDD/2 +
0.3
0.3
3-Level Inputs,
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
MID, VIN = VDD/2
LOW, VIN = VSS
Unit
V
V
V
–
0.6
V
–5
5
μA
–
200
μA
–50
50
μA
–200
–
μA
IPU
Input Pull Up Current
VIN = VSS, VDD = Max
–25
–
μA
IPD
Input Pull Down Current
VIN = VDD, VDD = Max, (sOE#)
–
100
μA
VOL
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 24 mA (PE/HD = MID),(nQ[0:1])
–
0.4
V
IOL = 2 mA (LOCK)
VOH
Output HIGH Voltage
0.4
V
2.4
–
V
IOH = –24 mA (PE/HD = MID),(nQ[0:1])
2.4
–
IOH = –2 mA (LOCK)
2.4
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID,
REF = LOW, sOE# = LOW,
Outputs Not Loaded
IDDPD
Power Down Current
PD#/DIV, sOE# = LOW, Test,nF[1:0],DS[1:0] = HIGH,
VDD = Max
IDD
Dynamic Supply Current
At 100 MHz
CIN
Input Pin Capacitance
V
V
–
2
mA
10(typ.)
25
μA
230
mA
4
pF
AC Input Specifications
Parameter
Description
Condition
Min
Max
Unit
TR,TF
Input Rise/Fall Time
0.8V – 2.0V
–
10
ns/V
TPWC
Input Clock Pulse
HIGH or LOW
2
–
ns
TDCIN
Input Duty Cycle
FREF
Reference Input
Frequency[12]
Document #: 38-07337 Rev. *D
10
90
%
FS = LOW
2
50
MHz
FS = MID
4
100
FS = HIGH
8
200
Page 7 of 13
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RoboClock®, CY7B995
Switching Characteristics
Parameter
Description
Condition
Min
FOR
Output frequency range
VCOLR
VCO Lock Range
VCOLBW
VCO Loop Bandwidth
0.25
tSKEWPR
Matched-Pair Skew[13]
Skew between the earliest and the latest output
transitions within the same bank.
–
tSKEW0
Output-Output Skew[13]
Skew between the earliest and the latest output
transitions among all outputs at 0tU.
–
tSKEW1
Skew between the earliest and the latest output
transitions among all outputs for which the same
phase delay has been selected.
tSKEW2
tSKEW3
tSKEW4
Output-Output Skew[13]
tSKEW5
Type
Max
Unit
6
–
200
MHz
200
–
400
MHz
–
3.5
MHz
–
100
ps
–
200
ps
–
–
200
ps
Skew between the nominal output rising edge to the
inverted output falling edge.
–
–
500
ps
Skew between non-inverted outputs running at
different frequencies.
–
–
500
ps
Skew between nominal to inverted outputs running at
different frequencies.
–
–
500
ps
Skew between nominal outputs at different power
supply levels.
–
–
650
ps
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ, VDD, temp,
air flow, frequency, etc.).
–
–
750
ps
–250
–
+250
ps
52
%
tPART
Part-Part Skew
tPD0
Ref to FB Propagation
Delay[14]
tODCV
Output Duty Cycle
Fout < 100 MHz, Measured at VDD/2.
48
–
Fout > 100 MHz, Measured at VDD/2.
45
–
55
tPWH
Output High Time
Deviation from 50%
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD
= 2.5V.
–
–
1.5
ns
tPWL
Output Low Time
Deviation from 50%
Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD
= 2.5V.
–
–
2.0
ns
tR/tF
Output Rise/Fall Time
Measured at 0.8V–2.0V for VDD = 3.3V and
0.7V–1.7V for VDD = 2.5V.
0.15
–
1.5
ns
tLOCK
PLL Lock Time[15,16]
–
–
0.5
ms
tCCJ
Cycle-Cycle Jitter
Divide by one output frequency, FS = L, FB = divide
by any.
–
45
100
ps
Divide by one output frequency, FS = M/H, FB = divide
by any.
–
55
150
ps
Notes
11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
12. IF PD#/DIV is in HIGH level (R-reference divider = 1). Reference Input Frequency = FREF. IF PD#/DIV is in MID level (R-reference divider = 2). Reference Input
Frequency = FREFx2.
13. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
14. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V–2.0V.
15. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
16. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document #: 38-07337 Rev. *D
Page 8 of 13
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RoboClock®, CY7B995
AC Timing Definitions
Figure 2. Timing Definition
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEW0,1
tSKEWPR
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
DIVIDE BY 2 OUTPUT
tSKEW1,3,4
tSKEW1,3,4
DIVIDE BY 4 OUTPUT
With PE HIGH (LOW), the REF rising (falling) edges are aligned
to the FB rising (falling) edges. Also, when PE is HIGH (LOW),
all divided outputs’ rising (falling) edges are aligned to the rising
(falling) edges of the undivided, non-inverted outputs.
Regardless of PE setting, divide-by-4 outputs’, rising edges align
to the divide-by-2 outputs’ rising edges.
Document #: 38-07337 Rev. *D
In cases where a non-divided output is connected to the FB input
pin, the divided output rising edges can be either 0 or 180
degrees phase aligned to the REF input rising edges (as set
randomly at power-up). If the divided outputs are required as
rising-edge (falling-edge) aligned to the REF input’s rising
(falling) edge, set the PE pin HIGH (LOW) and connect the
lowest frequency divided output to the FB input pin. This setup
provides a consistent input-output and output-output phase
relationship.
Page 9 of 13
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RoboClock®, CY7B995
AC Test Loads and Waveforms
Figure 3. For Lock Output and all other Outputs
VDDQ
150Ω
O u tp u t
20pF
O u tp u t
150Ω
F o r L o ck O u tp u t
20pF
F o r A ll O th e r O u tp u ts
Figure 4. 3.3V LVTTL and 2.5V LVTTL Output Waveforms
tORISE
tPWH
2.0V
tORISE
tOFALL
tOFALL
tPWH
1.7V
VTH =1.25V
VTH =1.5V
tPWL
tPWL
0.7V
0.8V
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 5. 3.3V LVTTL and 2.5V LVTTL Input Test Waveforms
≤ 1ns
3.0V
2.0V
VTH =1.5V
0.8V
0V
3.3V LVTTL INPUT TEST WAVEFORM
Document #: 38-07337 Rev. *D
≤ 1ns
≤ 1ns
≤ 1ns
2.5V
1.7V
VTH =1.25V
0.7V
0V
2.5V LVTTL INPUT TEST WAVEFORM
Page 10 of 13
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RoboClock®, CY7B995
Ordering Information
Part Number
Package Type
Product Flow
Status
CY7B995AC
44 TQFP
Commercial, 0° to 70°C
Obsolete
CY7B995ACT
44 TQFP – Tape and Reel
Commercial, 0° to 70°C
Obsolete
CY7B995AI
44 TQFP
Industrial, –40° to 85°C
Not for new design
CY7B995AIT
44 TQFP – Tape and Reel
Industrial, –40° to 85°C
Obsolete
CY7B995AXC
44 TQFP
Commercial, 0° to 70°C
Active
CY7B995AXCT
44 TQFP – Tape and Reel
Commercial, 0° to 70°C
Active
CY7B995AXI
44 TQFP
Industrial, –40° to 85°C
Active
CY7B995AXIT
44 TQFP – Tape and Reel
Industrial, –40° to 85°C
Active
Pb-free
Document #: 38-07337 Rev. *D
Page 11 of 13
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RoboClock®, CY7B995
Package Drawing and Dimension
Figure 6. 44-Pb Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB
51-85155*A
Document #: 38-07337 Rev. *D
Page 12 of 13
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RoboClock®, CY7B995
Document History Page
Document Title: CY7B995 Roboclock® 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer
Document Number: 38-07337
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
122626
01/10/03
RGL
New Data Sheet
*A
205743
See ECN
RGL
Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin
29 from VDD to VDDQ1
Added pin 1 indicator in the Pin Configuration Drawing
*B
362760
See ECN
RGL
Added description on the AC Timing Waveforms
Added typical value for cycle-to-cycle jitter
*C
389237
See ECN
RGL
Added Lead-free devices
*D
1562063
See ECN
PYG/AESA Added Status column to Ordering Information table
© Cypress Semiconductor Corporation, 2003-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07337 Rev. *D
Revised September 27, 2007
Page 13 of 13
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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