1CYM9287 CYM9288/CYM9289 512K/1M x 72 Flowthrough NoBL SRAM Module Features • Operates at 66 MHz • Uses 256K/512K x 18 high performance Flowthrough NoBL synchronous SRAMs • 3.3V data inputs/outputs epoxy laminate board with pins. The modules are designed to be incorporated into large memory arrays. Modules are configured as either one or two banks, where each bank has separate chip select controls. Separate clocks are provided for every pair of SRAMs. Functional Description Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. The CYM9288/9289 are high-performance synchronous Flowthrough NoBL memory modules organized as 512K/1M by 72 bits. These modules are constructed from 256K/512K x 18 NoBL SRAM’s in plastic surface mount packages on an All components on the cache modules are surface mounted on a multi-layer epoxy laminate (FR-4) substrate. The contact pins are plated with 200 micro-inches (minimum) of 90/10 tin/lead over 50 micro-inches of nickel. (4) 256K/512K x 18 SRAM’S Logic Block Diagram - CYM9288/9289 A[17:0] BWE[7:0] A17:0 ADV/LD OE D[15:0] DP[1:0] OE ADV/LD OE CE0 CS CE[0:1] D[63:0] DP[7:0] WE BW[1] WE BANK 0 CLK CLK[0:3] A17:0 (4) 256K/512K x 18 SRAM’S CLK[0] CLK[1] CLK[2] CLK[3] MODE MODE BW[0] D[15:0] DP[1:0] ADV/LD OE CE1 OE CS Cypress Semiconductor Corporation WE • 3901 North First Street • BANK 1 CLK San Jose CLK[3] BW[1] NC NC BANK 0 & 1 GND GND BANK 0 & 1 CLK[0] CLK[1] CLK[2] 9288 9289 PD0 MODE BW[0] PD1 • 9288/9289 CA 95134 • 408-943-2600 May 7, 2001 CYM9288/CYM9289 Selection Guide NoBL Synchronous Module Part Number CYM9288-60 CYM9288-66 CYM9289-60 CYM9289-66 Cache Size 512 K x 72 512 K x 72 1M x 72 1M x 72 SRAMs Used 8 of 256K x 18 8 of 256K x 18 8 of 512K x 18 8 of 512K x 18 System Clock (MHz) 60 66 60 66 Data tCDV 12 ns 10.5 ns 12 ns 10.5 ns 2 CYM9288/CYM9289 Pin Configuration Dual Read-Out ZIP Top View GND D63 D62 Vcc3 D60 D58 GND D56 D55 GND D53 D51 GND D49 DP5 Vcc3 D46 D44 GND D42 D40 GND D39 D37 GND D35 D33 GND CLK3 GND DP3 D30 Vcc3 D28 D26 GND D24 D23 GND D21 D19 GND D17 DP1 V cc3 D14 D12 GND D10 D8 GND D7 D5 GND D3 D1 PD0 MODE A18 A20 A16 A14 GND A12 A10 GND A8 A6 Vcc3 A4 A2 A0 GND CLK1 GND BWE7 BWE5 GND BWE3 BWE1 GND WE CE1 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 GND DP7 D61 GND D59 D57 GND DP6 D54 Vcc3 D52 D50 GND D48 D47 GND D45 D43 GND D41 DP4 Vcc3 D38 D36 GND D34 D32 GND CLK2 GND D31 D29 GND D27 D25 GND DP2 D22 Vcc3 D20 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 75 77 78 79 80 81 82 83 84 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 D18 GND D16 D15 GND D13 D11 GND D9 DP0 Vcc3 D6 D4 GND D2 D0 PD1 A19 A17 GND A15 A13 Vcc3 A11 A9 GND A7 A5 GND A3 A1 ADV/LD GND CLK0 GND BWE6 BWE4 GND BWE2 BWE0 Vcc3 OE CE0 GND 1 2 3 4 5 6 7 8 9 10 11 3 9288/9289 CYM9288/CYM9289 Pin Definitions Signal Description VCC3 3.3V supply GND Ground A[20:0] Addresses from processor OE Output Enable WE Write Enable BWE[7:0] Byte Write Enables CS[1:0] Chip Select for the two banks PD0–PD1 Presence Detect output pins D[63:0] Data lines from processor DP[7:0] Data Parity lines from processor CLK[0:3] Clock lines to the module ADV/LD Advance Load Signal from processor Mode Mode pin for Burst Selection NC Signal not connected on module RSVD Reserved Presence Detect Pins CYM9288 - 512K x 72 CYM9289 - 1M x 72 PD1 PD0 NC NC GND GND 4 CYM9288/CYM9289 Maximum Ratings DC Input Voltage –0.5V to +4.6V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature –55°C to +125°C Output Current into Outputs (LOW)20 mA Operating Range Ambient Temperature with Power Applied 0°C to +70°C Range Supply Voltage to Ground Potential –0.5V to +4.5V Commercial Ambient Temperature VCC 0°C to +70°C 3.3V ± 5% DC Voltage Applied to Outputs in High Z State –0.5V to +4.6V Electrical Characteristics Over the Operating Range Parameter Description Test Condition Min. Max. Unit 2.2 VCC + 0.3 V –0.3 0.8 V VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VCC = Min. IOH = −4 mA VCC = Min. IOL = 8 mA 0.4 V ICC (9288) ICC (9289) VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 2400 mA VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 2400 mA 2.4 V Capacitance[1] Parameter CA Description Address Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V CI Control Input Capacitance CO CCLK Max. 48 Unit pF TA = 25°C, f = 1 MHz, VCC = 3.3V 48 pF Input/Output Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 16 pF Clock Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 12 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. ................................................................. AC Test Loads and Waveforms R=317Ω 3.3V OUTPUT OUTPUT Z0 =50Ω RL =50Ω ALL INPUT PULSES 3.0V 5 pF R=351Ω GND VL = 1.5V (a) INCLUDING JIG AND SCOPE (b) 5 CYM9288/CYM9289 Switching Characteristics Over the Operating Range[2] 60 Parameter Description Min. 66 Max. Min. Max. Unit Clock tCYC Clock Cycle Time 16.6 15.0 FMAX Maximum Operating Frequency tCH Clock HIGH 6.0 5.0 ns tCL Clock LOW 6.0 5.0 ns 60 ns 66 MHz Output Times tCDV Data Output Valid After CLK Rise 12 10.5 ns tEOV OE LOW to Output Valid[3, 5] 6 6 ns tDOH Data Output Hold After CLK Rise Clock to High-Z[3, 4, 5] tCLZ Clock to Low-Z[3, 4, 5] tEOHZ OE HIGH to Output High-Z[3, 4, 5] tCHZ tEOLZ OE LOW to Output 1.5 1.5 5.0 3.0 5.0 2.0 6.0 Low-Z[3, 4, 5] ns ns ns 6.0 ns 0 0 ns Setup Times tAS Address Set-Up Before CLK Rise 2.5 2.0 ns tDS Data Input Set-Up Before CLK Rise 2.5 2.0 ns tWES WE, BWE[7:0] Set-Up Before CLK Rise 2.5 2.0 ns tALS ADV/LD Set-Up Before CLK Rise 2.5 2.0 ns tCES Chip Selects Set-Up 2.5 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tWEH WE, BWE[7:0] Hold After CLK Rise 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 ns tCEH Chip Selects Hold After CLK Rise 0.5 0.5 ns Hold Times Notes: 2. 3. 4. 5. AC test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loading shown in part (a) of AC Test Load for 3.3V devices and (c) for 2.5V devices. . tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. This parameter is sampled and not 100% tested. 6 CYM9288/CYM9289 Switching Waveforms DESELECT DESELECT Ignore Read Read Write Read DESELECT Read Read Write Read/Write/Deselect Timing CLK[0:3] tCENH tCENS tCH tCL tCENH tCENS tCYC CEN tAS ADDRESS WA2 RA1 RA3 WA5 RA4 RA6 RA7 tAH WE & BWE[7:0] tWS tWH tCES tCEH CE[0:1] tCLZ tDOH DataIn/Out Q11a Out tDOH tCHZ tCHZ D2 In Q4 Out Q31a Out D5 In Q6 Out Q7 Out Device tCDV originally deselected WE is the combination of WE & BWEx to define a write cycle (see Write Cycle Description table). RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = UNDEFINED = DON’T CARE 7 CYM9288/CYM9289 Switching Waveforms (continued) Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Sequences Burst Read Burst Read Burst Read Begin Read Read/Write/Deselect Timing CLK[0:3] tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWS tWH tWS tWH BWE[7:0] tCES tCEH CE[1:0] tCLZ DataIn/Out tCHZ tDOH Q11a Out Q1+1 Out Q1+2 Out Q1+3 Out D2 In tCDV t DeviceCDV originally deselected tCLZ tDH D2+1 In D2+2 In D2+3 In Q3 Out Q1+1 Out tDS The combination of WE & BWE[7:0] define a write cycle. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWE[7:0] input signals. Burst order determined by the state of the Mode input. CEN held LOW. OE held LOW. = UNDEFINED = DON’T CARE 8 CYM9288/CYM9289 Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/O’s tEOLZ Ordering Information Speed (MHz) Ordering Code 60 CYM9288APZ-60C 66 CYM9288APZ-66C 60 CYM9289BPZ-60C 66 CYM9289BPZ-66C Package Name PZ12 Package Type 168-Pin Quad-Row ZIP Description Flowthrough NoBL 512K x 72 Operating Range Commercial Flowthrough NoBL 512K x 72 PZ12 168-Pin Quad-Row ZIP Flowthrough NoBL 1M x 72 Flowthrough NoBL 1M x 72 Document #: 38-M-00092-** 9 Commercial CYM9288/CYM9289 Package Diagrams PZ12: 168 Pin Quad Row ZIP Module © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.