ETC EDI88130LP85CI

EDI88128C
128KX8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8.
n Access Times of 70, 85, 100ns
n Available with Single Chip Selects (EDI88128) or Dual
Chip Selects (EDI88130)
n 2V Data Retention (LP Versions)
n CS and OE Functions for Bus Control
n TTL Compatible Inputs and Outputs
n Fully Static, No Clocks
n Organized as 128Kx8
n Industrial, Military and Commercial Temperature Ranges
n Thru-hole and Surface Mount Packages JEDEC Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
n Single +5V (±10%) Supply Operation
The device is also available as EDI88130C with an additional
chip select line (CS2) which will automatically power down
the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in memory
banking where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional
input-output lines to provide simultaneous access to all
bits in a word. An automatic power down feature permits
the on-chip circuitry to enter a very low standby mode and
be brought back into operation at a speed equal to the
address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a
2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIG. 1
P
IN
C
T
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P D
ONFIGURATION
IN
ESCRIPTION
32 DIP
32 SOJ
I/O0-7
Data Inputs/Outputs
A0-16
Address Inputs
V
WE
Write Enable
OP
IEW
32 VCC
31 A15
30 NC/CS2*
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
CS1, CS2
Chip Selects
OE
Output Enable
VCC
Power (+5V ±10%)
VSS
Ground
NC
Not Connected
B
LOCK
D
IAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
March 2002 Rev. 16
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
A
BSOLUTE
M
AXIMUM
R
T
ATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
Unit
OE
-0.5 to 7.0
V
X
X
X
H
L
X
A (Ambient)
Commercial
0 to +70
°C
Industrial
-40 to +85
°C
Military
-55 to +125
°C
Storage Temperature, Plastic
-65 to +150
°C
1
W
Output Current
20
mA
Junction Temperature, TJ
175
°C
Power Dissipation
1
2
CS
CS
H
X
X
L
L
L
X
L
L
H
H
H
R
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
T
ABLE
WE
Mode
Output
Power
X
X
X
H
H
L
Standby
Standby
Output Deselect
Output Deselect
Read
Write
High Z
High Z
High Z
High Z
Data Out
Data In
Icc 2 , Icc 3
Icc 2 , Icc 3
Icc1
Icc1
Icc1
Icc1
ECOMMENDED
Parameter
RUTH
O
PERATING
C
ONDITIONS
Symbol
Min
Typ
Max
Supply Voltage
VCC
4.5
5.0
5.5
Unit
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
—
Vcc +0.5
V
Input Low Voltage
VIL
-0.3
—
+0.8
V
C
(TA = +25°C)
APACITANCE
Parameter
Symbol
Condition
Max
Unit
Address Lines
CI
VIN = Vcc or Vss, f = 1.0MHz
12
pF
Input/Output Lines
CO
VOUT = Vcc or Vss, f = 1.0MHz
14
pF
These parameters are sampled, not 100% tested.
DC C
(VCC = 5V, T A = -55°C
HARACTERISTICS
Parameter
Symbol
TO
+125°C)
Conditions
Units
Min
Typ
Max
Input Leakage Current
I LI
VIN = 0V to VCC
-5
—
+5
µA
Output Leakage Current
I LO
VI/O = 0V to VCC, CS1 ³ VIH and/or CS2 £ VIL
-10
—
+10
µA
Operating Power Supply Current
I CC1
WE, CS 1 = VIL, II/O = 0mA, Min Cycle
CS2 = VIH
I CC2
CS 1 ³ VIH and/or CS2 £ VIL, VIN ³ VIH or £ VIL
Full Standby Power Supply Current
Output Low Voltage
I CC3
VOL
CS 1 ³ VCC -0.2V and/or CS2 £ Vcc +0.2V
VIN ³ Vcc -0.2V or VIN £ 0.2V
IOL = 2.1mA
Output High Voltage
VOH
IOH = -1.0mA
Standby (TTL) Power Supply Current
NOTE: DC test conditions : V IL = 0.3V, V IH = Vcc -0.3V
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
(70-85ns)
—
120
mA
(100ns)
—
110
mA
—
C
LP
10
mA
—
—
—
1
—
—
5
1
0.4
mA
mA
V
2.4
—
—
V
EDI88128C
AC C
–R
C
(VCC = 5.0V, VSS = 0V, TA = -55°C
HARACTERISTICS
Symbol
EAD
YCLE
TO
+125°C)
70ns
85ns
Parameter
JEDEC
Alt.
Min
Max
Read Cycle Time
tAVAV
tRC
70
Address Access Time
tAVQV
tAA
70
Chip Select Access Time
tELQV
tSHQV
tACS
tACS
70
70
Chip Select to Output in Low Z (1)
tELQX
tSHQX
tCLZ
tCLZ
3
3
Chip Disable to Output in High Z (1)
tEHQZ
tSLQZ
tCHZ
tCHZ
0
0
OutputHoldfromAddressChange
tAVQX
tOH
3
OutputEnabletoOutputValid
tGLQV
tOE
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
0
Output Disable to Output in High Z (1)
tGHQZ
tOHZ
0
Min
100ns
Max
Max
Units
85
100
ns
85
85
100
100
ns
ns
85
100
3
3
30
30
0
0
30
30
0
0
0
ns
ns
30
30
ns
ns
3
30
0
30
ns
3
3
3
25
Min
ns
50
ns
0
30
0
ns
30
ns
1. This parameter is guaranteed by design but not tested.
AC T
EST
Figure 1
C
ONDITIONS
Figure 2
Vcc
480Ω
Q
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Vcc
480Ω
VSS to 3.0V
5ns
1.5V
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
255Ω
30pF
255Ω
5pF
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
AC C
–W
C
(VCC = 5.0V, VSS = 0V, TA = -55°C
HARACTERISTICS
Symbol
RITE
YCLE
TO
+125°C)
70ns
85ns
Max
JEDEC
Alt.
Min
Write Cycle Time
tAVAV
tWC
70
85
100
ns
Chip Select to End of Write
t ELWH
t ELEH
tSHWH
t SHSL
tCW
tCW
tCW
tCW
60
60
60
60
75
75
75
75
85
85
85
85
ns
ns
ns
ns
Address Setup Time
tAVWL
t AVEL
tAVSH
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write
t AVWH
tAW
60
75
85
ns
Write Pulse Width
t WLWH
t WLEH
t WLSL
tWP
tWP
tWP
35
35
35
70
70
70
80
80
80
ns
ns
ns
Write Recovery Time
tWHAX
tEHAX
tSLAX
tWR
tWR
tWR
5
5
5
5
5
5
5
5
5
ns
ns
ns
Data Hold Time
tWHDX
tEHDX
tSLDX
tDH
tDH
tDH
0
0
0
0
0
0
0
0
0
ns
ns
ns
0
Max
40
Units
tWLQZ
tWHZ
0
t DVWH
t DVEH
t DVSL
tDW
tDW
tDW
35
35
35
40
40
40
40
40
40
ns
ns
ns
Output Active from End of Write (1)
tWHQX
t WLZ
5
5
5
ns
4
35
Min
Write to Output in High Z (1)
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
0
Max
Data to Write Time
1. This parameter is guaranteed by design but not tested.
30
Min
100ns
Parameter
ns
EDI88128C
F .2T
IG
IMING
W
AVEFORM
-R
C
EAD
YCLE
tAVAV
ADDRESS
tAVQV
CS1
tAVAV
ADDRESS
tELQV
tELQX
tEHQZ
tSHQV
tSHQX
tSLQZ
CS2
ADDRESS 1
ADDRESS 2
OE
tAVQX
tAVQV
DATA I/O
DATA 1
tGLQV
tGLQX
DATA 2
READ CYCLE 2 (WE HIGH)
READ CYCLE 1 (WE HIGH; OE, CS LOW)
F .3W
IG
RITE
C
YCLE
tGHQZ
DATA I/O
1
tAVAV
ADDRESS
tAVWL
tAVWH
tWLWH
tWHAX
WE
CS1
tELWH
CS2
tSHWH
tWHQX
tWHDX
tDVWH
DATA IN
DATA VALID
tWLQZ
HIGH Z
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
F .4W
IG
RITE
C
YCLE
2
W
RITE
YCLE
3
WS32K32-XHX
tAVAV
tAVAV
ADDRESS
ADDRESS
tAVEL
tEHAX
tWLEH
tAVSH
tSLAX
tWLSL
WE
WE
tSHSL
tELEH
CS1
CS1
CS2
CS2
tDVEH
DATA IN
C
tDVSL
tEHDX
DATA IN
DATA VALID
tSLDX
DATA VALID
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
D
ATA
R
ETENTION
C
(EDI88128LP & EDI88130LP ONLY)
(TA = -55°C
+125°C)
HARACTERISTICS
TO
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
VDD
VDD = 2.0V
2
–
–
V
Data Retention Quiescent Current
I CCDR
CS 1 ³ VDD -0.2V
–
–
400
µA
Chip Disable to Data Retention Time (1)
T CDR
VIN ³ VDD -0.2V
0
–
–
ns
T AVAV *
–
–
ns
Operation Recovery Time (1)
TR
or VIN £ 0.2V
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
F .5D
IG
ATA
R
ETENTION
- CS1 C
ONTROLLED
Data Retention Mode
4.5V
Vcc
VDD
WS32K32-XHX
4.5V
tCDR
tR
CS1
CS1 VDD -0.2V
DATA RETENTION, CS1 CONTROLLED
F .6D
IG
ATA
R
ETENTION
- CS2 C
ONTROLLED
Data Retention Mode
4.5V
Vcc
VDD
WS32K32-XHX
4.5V
tCDR
tR
CS2 ≤ 0.2V
CS2
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6
EDI88128C
P
ACKAGE
9: 32 PIN SIDEBRAZED CERAMIC D IP (600 MILS WIDE )
1.616
1.584
0.200
0.125
0.061
0.017
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.100
TYP
0.020
0.016
0.155
0.115
0.600
NOM
15 x 0.100 = 1.500
ALL Dimensions ARE in inches
P
ACKAGE
140: 32 LEAD CERAMIC SOJ
0.010
0.006
0.019
0.015
0.840
0.820
0.444
0.430
0.379
0.050
TYP
0.155
0.106
ALL Dimensions ARE in inches
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
O
RDERING
I
NFORMATION
EDI 8 8 128 C X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
8 130 = Dual Chip Select
TECHNOLOGY:
C = CMOS Standard Power
LP = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
N = 32 lead Ceramic SOJ (Package 140)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8