AGILENT HDMP-0482

Agilent HDMP-0482
Octal Cell Port Bypass Circuit
with CDR and Data Valid Detection
Data Sheet
Features
• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd Gigabit Ethernet
(GE) operation
Description
The HDMP-0482 is an Octal Cell
Port Bypass Circuit (PBC) with
Clock and Data Recovery (CDR)
and data valid detection capability included. This device minimizes part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped
while other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplexers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk bypassed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0482’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx± differential outputs goes to
the HDMP-0482’s FM_NODE[n]±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the “disk in
loop” mode. HDMP-0482’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0482 may also be used
as eight 1:1 buffers, one with a
CDR and seven without. For
example, an HDMP-0482 may be
placed in front of a CMOS ASIC
to clean the jitter of the outgoing
signal (CDR path) and to better
read the incoming signal (nonCDR path). In addition, the
HDMP-0482 may be configured as
four 2:1 multiplexers or as four
1:2 buffers.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions
be taken in the handling and assembly of this component to prevent damage and/or
degradation which may be induced by electrostatic discharge (ESD).
• Octal cell PBC/CDR in one package
• CDR location determined by choice
of cable input/output
• Amplitude valid detection on
FM_NODE[7] input
• Data valid detection on
FM_NODE[0] input
– Run length violation detection
– Comma detection
– Configurable for both singleframe and multi-frame detection
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 1.09 W typical power at Vcc=3.3V
• 64 Pin, 14 mm, low cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
HDMP-0482
1
2
3
For configurations where the CDR
is before slot A, a Data Valid
(FM_NODE[0]_DV) pin indicates
whether the incoming data on
FM_NODE[0]± is valid Fibre
Channel data. In addition, an
Amplitude Valid (FM_NODE[7]AV)
pin shows the status of the signal
at FM_NODE[7].
before entering the hard disk at
slot A. To obtain a CDR function
after slot G, BYPASS[1]- must be
floating and hard disk slots A to
G must be connected to PBC cells
2,3,4,5,6,7 and 0, respectively.
Table 1 shows all possible
connections.
4
5
6
7
0
BYPASS1
BYPASS2
BYPASS3
BYPASS4
BYPASS5
BYPASS6
BYPASS7
AV
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FM_NODE(7)_AV
The HDMP-0482 design allows for
CDR placement at any location
with respect to the hard disk
slots. For example, if the BYPASS[0]- pin is floating and hard
disk slots A to G are connected to
PBC cells 1 to 7, respectively, the
CDR function will be performed
0
CDR
1
FM_NODE[0]_DV
DV
MODE_VDD
BYPASS0
FSEL
REFCLK
RFCM
MODE_VDD
BYPASS0
Figure 1. Block Diagram of HDMP-0482.
HDMP-0482 Block Diagram
CDR
The Clock and Data Recovery
(CDR) block is responsible for
frequency and phase locking onto
the incoming serial data stream
and resampling the incoming
data based on the recovered
clock. An automatic locking
feature allows the CDR to lock
onto the input data stream
without external training controls. It does this by continually
frequency locking onto the
106.25 MHz reference clock
(REFCLK) and then phase
locking onto the input data
stream. Once bit locked, the CDR
generates a high-speed sampling
clock. This clock is used to
2
sample or repeat the incoming
data to produce the CDR output.
The CDR jitter specifications
listed in this data sheet assume
an input that has been 8B/10B
encoded.
DV Output
The Data Valid (DV) block detects
if the incoming data on
FM_NODE[0]± is valid Fibre
Channel data. The DV checks for
sufficient K28.5+ characters (per
Fibre Channel framing rules) and
for run length violations (per 8B/
10B encoding) on the data
coming out of the CDR. The
FM_NODE[0]_DV output is
pulled low if a run length viola-
tion (RLV) occurs, or if there are
no commas detected (NCD) in a
sufficient time. It is pulled high if
no errors are found. A RLV error
is defined as any consecutive
sequence of 1s or 0s greater than
five in the serial data bit stream.
A NCD error indicates the
absence of a seven-bit pattern
(0011111) present in the positive
disparity comma (K28.5+)
character. A K28.5+ character
should occur at the beginning of
every Fibre Channel frame of
2148 bytes (or 21480 serial bits),
as well as many times within and
between frames. If this seven-bit
pattern is not found within a 215
bit (~31 µs) interval, an NCD
error is generated.
When the DV is configured in
single-frame mode (FSEL low),
any RLV and NCD errors stored
during this 215 bit interval cause
FM_NODE[0]_DV to be pulled
low on the next subsequent
interval. FM_NODE[0]_DV
remains low until after an entire
215 bit interval in which no RLVs
occur and at least one comma is
detected. At that time,
FM_NODE[0]_DV is pulled high.
A multi-frame mode (FSEL high)
configuration of the DV is also
available. When in multi-frame
mode, the FM_NODE[0]_DV
output is only pulled low when
four consecutive 215 bit intervals
of bad data have been transmitted. Once low, FM_NODE[0]_DV
does not go high again until four
consecutive 215 bit intervals of
good data are transmitted.
AV Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[7]± is valid by examining the differential amplitude
of that input. The incoming data
is considered valid, and
FM_NODE[7]_AV is driven high,
as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[7]_AV
is driven low as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the amplitude of the input signal is between 100– 400 mV (differential
peak-to-peak), FM_NODE[7]_AV
is unpredictable. The
FM_NODE[7]_AV output is
latched in with an internally
generated 215 bit clock. Similar to
the DV function, the AV can be
configured for single-frame or
multi-frame operation.
3
BLL Output
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0482 are of
equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace. Unused outputs should not
be left unconnected. Ideally,
unused outputs should have their
differential pins shorted together
with a short PCB trace. If transmission lines are connected to
the output pins, the lines should
be differentially terminated with
an appropriate resistor. The value
of the termination resistor should
match the PCB trace differential
impedance.
EQU Input
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs.
BYPASS[N]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0482. All BYPASS pins are
LVTTL and contain internal pullup circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1kΩ resistor. Otherwise, the BYPASS[n]- inputs
should be left to float. In this
case, the internal pull-up circuitry will force them high.
REFCLK Input
The LVTTL REFCLK input
provides a reference oscillator
for frequency acquisition of the
CDR. The REFCLK frequency
should be within ±100 ppm of
one-tenth or one-twentieth of the
incoming data rate in baud
(106.25 MHz ±100 ppm, or
53.125 MHz ±100 ppm for FC-AL
running at 1.0625 GBd).
RFCM Input
The LVTTL RFCM input configures the CDR to accept a
REFCLK at either one-tenth or
one-twentieth of the incoming
data rate in baud. The RFCM
input has internal pull-up
circuitry, so the user should
connect the pin to GND through
a 1kΩ resistor for a REFCLK at
one-twentieth the incoming data
rate. For a REFCLK at one-tenth
the incoming data rate, let RFCM
float high.
MODE_VDD Input
The active high valid data detect
mode pin selects data checking of
the FM_NODE [0] +/- inputs.
When high, MODE_VDD overides
BYPASS [0] and forces the
incoming data into the CDR for
error checking. When low, the
chip can be configured for CDR
anywhere capability. Refer to
Figures 2 & 3 for high and low
MODE_VDD configuration.
2
3
4
5
6
7
0
BYPASS1
BYPASS2
BYPASS3
BYPASS4
BYPASS5
BYPASS6
BYPASS7
AV
1
1
1
1
1
1
1
0
0
0
0
0
0
0
FM_NODE(7)_AV
1
0
CDR
1
DV
FM_NODE[0]_DV
BYPASS0
Figure 2. Block Diagram of HDMP-0482, MODE_VDD is HIGH.
2
3
4
5
6
7
0
BYPASS2
BYPASS3
BYPASS4
BYPASS5
BYPASS6
BYPASS7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
BYPASS0
BYPASS1
AV
CDR
FM_NODE[0]_DV
DV
Figure 3. Block Diagram of HDMP-0482, MODE_VDD is LOW.
4
FM_NODE(7)_AV
1
Table 1. Pin Connection Diagram to Achieve Desired CDR Location.
Hard Disk
ABCDEFG
ABCDEFG
ABCDEFG
ABCDEFG
Connection to PBC Cell
1234567
01234567
01234567
01234
CDR Position (x)
xA B C D E F G
AxB C D E F G
A BxC D E F G
A B CxD E F G
Cell Connection to Cable
0
7
6
5
Hard Disk
ABCDEFG
ABCDEFG
ABCDEFG
ABCDEFG
Connection to PBC Cell
5670123
4567012
3456701
2345670
CDR Position (x)
A B C DxE F G
A B C D ExF G
A B C D E FxG
A B C D E F Gx
Cell Connection to Cable
4
3
2
1
BYPASS[7]REFCLK
RFCM
FM_NODE[0]_DV
VCC
GND
MODE_VDD
VCCA
GND
CPLL1
CPLL0
FSEL
BYPASS[0]FM_NODE[7]_AV
FM_NODE[0]FM_NODE[0]+
BYPASS[5]-
FM_NODE[5]-
FM_NODE[5]+
GND
FM_NODE[6]-
FM_NODE[6]+
BYPASS[6]-
TO_NODE[6]-
TO_NODE[6]+
VCCHS
TO_NODE[7]-
TO_NODE[7]+
GND
FM_NODE[7]-
FM_NODE[7]+
VCC
x denotes CDR position with respect to hard disks.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Agilent
HDMP-0482
nnnn-nnn Rz.zz
S YYWW
VCCHS
TO_NODE[5]+
TO_NODE[5]VCCHS
TO_NODE[4]+
TO_NODE[4]BYPASS[4]FM_NODE[4]+
FM_NODE[4]GND
FM_NODE[3]+
FM_NODE[3]BYPASS[3]TO_NODE[3]+
TO_NODE[3]VCCHS
TO_NODE[2]+
TO_NODE[2]-
BYPASS[2]-
FM_NODE[2]+
FM_NODE[2]-
VCC
FM_NODE[1]+
FM_NODE[1]-
BYPASS[1]-
TO_NODE[1]+
TO_NODE[1]-
VCCHS
TO_NODE[0]+
TO_NODE[0]-
GND
VCC
Figure 4. HDMP-0482 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code
(YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
Table 2. I/O Type Definitions.
I/O Type
Definition
I-LVTTL
LVTTL Input
O-LVTTL
LVTTL Output
HS_OUT
High Speed Output, LVPECL Compatible
HS_IN
High Speed Input
C
External circuit node
S
Power supply or ground
5
Table 3. Pin Definitions for HDMP-0482.
Pin Name
Pin
Pin Type
Pin Description
TO_NODE[0]+
TO_NODE[0]TO_NODE[1]+
TO_NODE[1]TO_NODE[2]+
TO_NODE[2]TO_NODE[3]+
TO_NODE[3]TO_NODE[4]+
TO_NODE[4]TO_NODE[5]+
TO_NODE[5]TO_NODE[6]+
TO_NODE[6]TO_NODE[7]+
TO_NODE[7]-
20
19
23
22
32
31
35
34
44
43
47
46
57
56
60
59
HS_OUT
Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
FM_NODE[0]+
FM_NODE[0]FM_NODE[1]+
FM_NODE[1]FM_NODE[2]+
FM_NODE[2]FM_NODE[3]+
FM_NODE[3]FM_NODE[4]+
FM_NODE[4]FM_NODE[5]+
FM_NODE[5]FM_NODE[6]+
FM_NODE[6]FM_NODE[7]+
FM_NODE[7]-
16
15
26
25
29
28
38
37
41
40
51
50
54
53
63
62
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
BYPASS[0]BYPASS[1]BYPASS[2]BYPASS[3]BYPASS[4]BYPASS[5]BYPASS[6]BYPASS[7]-
13
24
30
36
42
49
55
1
I-LVTTL
Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND through a1kΩ resistor.
For “disk in loop” mode, float HIGH.
REFCLK
2
I-LVTTL
Reference Clock: A user-supplied clock reference used for frequency acquisition in
the Clock and Data Recovery (CDR) circuit.
CPLL1
CPLL0
10
11
C
Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit
must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1 µF.
FM_NODE[7]_AV
14
O-LVTTL
Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[7]± inputs.
If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1
If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable
If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-),
FM_NODE[7]_AV = 0
FM_NODE[0]_DV
4
O-LVTTL
Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0]± inputs when HIGH. Indicates
either run length violation error or no comma detected when LOW.
RFCM
3
I-LVTTL
Reference Clock Mode: To configure a one-twentieth-rate reference clock, connect RFCM to
GND through a 1kΩ resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH.
MODE_VDD
7
I_LVTTL
Valid Data Detect Mode: To allow data valid detection, float MODE_VDD HIGH. To configure chip for
“CDR anywhere” capability, connect MODE_VDD to GND through a 1kΩ resistor.
FSEL
12
I_LVTTL
Frame Select: To configure single-frame operation of the data valid and amplitude valid
detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame)
operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.
Table 3 is continued on next page.
6
Table 3, continued. Pin Definitions for HDMP-0482.
Pin Name
Pin
Pin Type
Pin Description
GND
6
9
18
39
52
61
S
Ground: Normally 0 volts. See Figure 11 for Recommended Power Supply Filtering.
VCCA
8
S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the Clock and Data
Recovery (CDR) circuit. See Figure 11 for Recommended Power Supply Filtering.
VCCHS[0,1]
VCCHS[2,3]
VCCHS[4]
VCCHS[5]
VCCHS[6,7]
21
33
45
48
58
S
S
S
S
S
High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]). See Figure 11 for
Recommended Power Supply Filtering.
VCC
5
17
27
64
S
S
S
S
Logic Power Supply: Normally 3.3 volts. Used for internal logic. See Figure 11 for Recommended Power
Supply Filtering.
HDMP-0482 Absolute Maximum Ratings
Ta=25° C, except as specified. Operation in excess of any of these conditions may result in permanent
damage to this device. Ta refers to the ambient temperature for the board upon which the parametric
measurements were taken.
Symbol
Parameters
Min.
Max.
Units
VCC
Supply Voltage
-0.7
4.0
V
VIN, LVTTL
LVTTL Input Voltage
-0.7
4.0
V
VIN, HS_IN
HS_IN Input Voltage
1.3
VCC
V
IO, LVTTL
LVTTL Output Voltage
±13
mA
Tstg
Storage Temperature
-65
+150
°C
Tj
Junction Temperature
0
+125
°C
HDMP-0482 Guaranteed Operating Rates, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Serial Clock Rate
FC (MBd)
Min.
Max.
Serial Clock Rate
GE (MBd)
Min.
Max.
1,040
1,240
1,080
1,260
HDMP-0482 CDR Reference Clock Requirements, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameter
f
Nominal Frequency (Fibre Channel)
106.25
MHz
f
Nominal Frequency (Gigabit Ethernet)
125
MHz
Ftol
Frequency Tolerance
-100
100
ppm
Symm
Symmetry (duty cycle)
40
60
%
7
Min.
Typ.
Max.
Units
HDMP-0482 DC Electrical Specifications, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Min.
VIH,LVTTL
LVTTL Input High Voltage Range
VIL,LVTTL
Typ.
Max.
Units
2.0
4.0
V
LVTTL Input Low Voltage Range
0
0.8
V
VOH,LVTTL
LVTTL Output High Voltage Range, IOH = -400 µA
2.2
3.45
V
VOL,LVTTL
LVTTL Output Low Voltage Level, IOL = 1 mA
0
0.6
V
IIH,LVTTL
Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V
.003
40
µA
IIL,LVTTL
Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V
300
600
µA
ICC
Total Supply Current, Ta = 25°C
330
400
mA
Typ.
Max.
Units
HDMP-0482 AC Electrical Specifications, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Min.
tloop
Total Loop Latency from FM_NODE[0] to TO_NODE[0]
2.8
4.2
ns
tcell
Per Cell Latency from FM_NODE[7] to TO_NODE[0]
0.5
0.8
ns
tr,LVTTLin
Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V
2
ns
tf,LVTTLin
Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V
2
ns
trs,HS_OUT
HS_OUT Single-Ended Rise Time, 20%-80%
200
350
ps
tfs,HS_OUT
HS_OUT Single-Ended Rise Time, 20%-80%
200
350
ps
trd,HS_OUT
HS_OUT Differential Rise Time, 20%-80%
200
350
ps
tfd,HS_OUT
HS_OUT Differential Rise Time, 20%-80%
200
350
ps
VIP,HS_IN
HS_IN Input Peak to Peak Required Differential Voltage Range
400
1200
2000
mV
VOP,HS_OUT
HS_OUT Output Pk-Pk Diff. Voltage Range (Z0 = 75Ω, Fig. 9)
1100
1400
2000
mV
HDMP-0482 Power Dissipation, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Unit
Typ.
Max.
PD
Power Dissipation
mW
1090
1380
Max.
HDMP-0482 Output Jitter Characteristics, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Unit
Typ.
RJ
Random Jitter at TO_NODE pins (1 sigma rms)
ps
5
DJ
Deterministic Jitter at TO_NODE pins (pk-pk)
ps
24
Please refer to Figures 6 and 7 for jitter measurement setup information.
HDMP-0482 Locking Characteristics, Ta = 0°C to +70°C, VCC = 3.15V to 3.45V
Parameter
Unit
Max.
Bit Sync Time (phase lock)
bits
2500
Frequency Lock at Powerup
µs
500
8
Figure 5. Eye Diagram of TO_NODE[1]± High Speed Differential Output.
Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0]±.
HDMP-0482
2
HP70841B
Pattern Generator
+/- FM_NODE[0]
+/- Data
BYPASS[0]BYPASS[1:4]-
Bias Tee
K28.7
N/C
1 KΩ
REFCLK
Clock
+/- TO_NODE[0]
1.4V
1062.5 MHz
2
106.25 MHz
HP 70311A
Clock Source
1/10
Ch 1/2
HP 83480A
Digital
Trigger
Communication
Analyzer
106.25 MHz
Figure 6. Setup for Measurement of Random Jitter.
HDMP-0482
2
HP70841B
Pattern Generator
+/- FM_NODE[0]
+/- Data
BYPASS[0]BYPASS[1:4]-
Bias Tee
+K28.5
-K28.5
1 KΩ
REFCLK
Clock
+/- TO_NODE[0]
1.4V
1062.5 MHz
106.25 MHz
HP 70311A
Clock Source
Ch 1/2
HP 83480A
Digital
Trigger
1/10
Communication
53.125 MHz
Analyzer
Figure 7. Setup for Measurement of Deterministic Jitter.
9
2
1/10
106.25 MHz
N/C
O-LVTTL
I-LVTTL
Vcc
Vcc
Vcc
Vbb
1.4V
GND
ESD
Protection
ESD
Protection
GND
GND
Figure 8. O_LVTTL and I_LVTTL Simplified Circuit Schematic.
HS_OUT
HS_IN
VCCHS
VCC
+
–
VCC
VCC
+
–
75 Ohms
ZO = 75Ω
TO_NODE[n]+
FM_NODE[n]+
0.01 µF
2 * ZO = 150Ω
ZO = 75Ω
FM_NODE[n]-
TO_NODE[n]-
ESD
Protection
0.01 µF
GND
GND
GND
ESD
Protection
GND
Figure 9. HS_OUT and HS_IN Simplified Circuit Schematic.
Note: FM_NODE[n] inputs should never be connected to ground as permanent damage to the device may result.
10
Package Information
HDMP-0482 Thermal Characteristics, TC = 0°C to 85°C, VCC = 3.15V to 3.45V
Symbol
Parameter
Unit
Typ.
Max.
θ jc
Thermal Resistance, Junction to Case
°C/W
9.5
—
Note: Based on independent testing by Agilent. θja for these devices is 39.4°C/W for the HDMP-0482.
θja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual
junction temperature in a given application, use the following equation: Tj = TC + (θjc x PD), where TC
is the case temperature measured on the top center of the package, and PD is the power being
dissipated.
Item
Details
Package Material
Plastic
Lead Finish Material
85% Tin, 15% Lead
Lead Finish Thickness
300 – 800 micro-inches
Lead Skew
0.20 mm max.
Lead Coplanarity
(Seating Plane Method)
0.10 mm max.
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
HDMP-0482
41
8
40
9
TOP VIEW
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
E1
E
G
c
b
D1
L
e
D
A2
A
A1
Figure 10. HDMP-0482 Package Drawing.
Mechanical Dimensions of HDMP-0482
Dimensional Parameter
(in millmeters)
D1/E1
D/E
b
e
L
c
G
A2
A1
A
HDMP-0482
14.00
17.20
0.35
0.80
0.88
0.17
0.25
2.00
0.25
Max
2.35
Tolerance
±0.10
±0.25
±0.05
Basic
+0.15/
-0.10
Max
Gage
Plane
+0.10/
-0.05
11
Max
GND
VCC
GND
CPLL1
VCC
VCC
VCC
Figure 11. Recommended Power Supply Filtering. Capacitors = 0.1 µF, Resistor = 10Ω.
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Data subject to change.
Copyright © 2003 Agilent Technologies, Inc.
Obsoletes 5988-7140EN
June 16, 2003
5988-9758EN
VCC
VCC
HDMP-0482
GND
CPLL0
GND
VCC
GND
VCC
VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
VCC