HSP45106/883 TM Data Sheet May 1999 FN2815.3 16-Bit Numerically Controlled Oscillator Features The Intersil HSP45106/883 is a high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). The NCO16 simplifies applications requiring frequency and phase agility such as frequency-hopped modems, PSK modems, spread spectrum communications, and precision signal generators. As shown in the Block Diagram, the HSP45106/883 is divided into a Phase/Frequency Control Section (PFCS) and a Sine/Cosine Section. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The inputs to the Phase/Frequency Control Section consist of a microprocessor interface and individual control lines. The frequency resolution is 32 bits, which provides for resolution of better than 0.006Hz at 25.6MHz. User programmable center frequency and offset frequency registers give the user the capability to perform phase coherent switching between two sinusoids of different frequencies. Further, a programmable phase control register allows for phase control of better than 0.006o. In applications requiring up to 8 level PSK, three discrete inputs are provided to simplify implementation. • 25.6MHz Clock Rate • 32-Bit Center and Offset Frequency Control • 16-Bit Phase Control • 8 Level PSK Supported Through Three Pin Interface • Simultaneous 16-Bit Sine and Cosine Outputs • Output in Two’s Complement or Offset Binary • <0.006Hz Tuning Resolution at 25.6MHz • Serial or Parallel Outputs • Spurious Frequency Components < -90dBc • 16-Bit Microprocessor Compatible Control Interface Applications The output of the PFCS is a 32-bit phase argument which is input to the Sine/Cosine Section for conversion into sinusoidal amplitude. The outputs of the Sine/Cosine Section are two 16-bit quadrature signals. The spurious free dynamic range of this complex vector is greater than 90dBc. • Direct Digital Synthesis For added flexibility when using the NCO16 in conjunction with DAC’s, a choice of either parallel of serial outputs with either two’s complement or offset binary encoding is provided. In addition, a synchronization signal is available which signals serial word boundaries. Ordering Information • Quadrature Signal Generation • Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK) • Precision Signal Generation PART NUMBER TEMP. RANGE ( oC) HSP45106GM-25/883 -55 to 125 PACKAGE 85 Ld PGA PKG. NO. G85.A Block Diagram MICROPROCESSOR INTERFACE DISCRETE CONTROL SIGNALS SIN/COS ARGUMENT PHASE/ FREQUENCY CONTROL SECTION 32 SINE/ COSINE SECTION SINE 16 COSINE 16 CLOCK 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HSP45106/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output Voltage Applied . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . . 36.0 7.0 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Die Characteristics Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18,750 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUPS TEMPERATURE ( oC) MIN MAX UNITS Logical One Input Voltage VlH VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ +125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 55 ≤ TA ≤ +125 - 0.8 V Output HlGH Voltage VOH IOH = -400µA VCC = 4.5V (Note 2) 1, 2, 3 55 ≤ TA ≤ +125 2.6 - V Output LOW Voltage VOL IOL = +2.0mA VCC = 4.5V (Note 2) 1, 2, 3 55 ≤ TA ≤ +125 - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ +125 -10 +10 µA Output Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ +125 -10 +10 µA Clock lnput High VIHC VCC = 5.5V 1, 2, 3 55 ≤ TA ≤ +125 3.0 - V Clock Input Low V ILC VCC = 4.5V 1, 2, 3 55 ≤ TA ≤ +125 - 0.8 V Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.5V, (Note 5) 1, 2, 3 55 ≤ TA ≤ +125 - 500 µA Operating Power Supply Current ICCOP f = 25.6MHz VCC = 5.5V (Notes 3, 5) 1, 2, 3 55 ≤ TA ≤ +125 - 205 mA 7, 8 55 ≤ TA ≤ +125 - - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH ≥ 1.5V, VOL ≤ 1.5V, VIHC = 3.4V, and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF. 2 HSP45106/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS -25 (25.6MHz) PARAMETER SYMBOL NOTES GROUP A SUBGROUP TEMPERATURE ( oC) MIN MAX UNITS CLK Period t CP 9, 10, 11 -55 ≤ TA ≤ 125 39 - ns CLK High t CH 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns CLK Low tCL 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns WR Period tWP 9, 10, 11 -55 ≤ TA ≤ 125 39 - ns WR High tWH 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns WR Low tWL 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns Setup Time A(2:0), CS to WR Going High tAWS 9, 10, 11 -55 ≤ TA ≤ 125 13 - ns Hold Time A(2:0), CS from WR Going High tAWH 9, 10, 11 -55 ≤ TA ≤ 125 2 - ns Setup Time C(15:0) to WR Going High tCWS 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns Hold Time C(15:0) from WR Going High tCWH 9, 10, 11 -55 ≤ TA ≤ 125 1 - ns 9, 10, 11 -55 ≤ TA ≤ 125 16 - ns Setup Time WR High to CLK High tWC Setup Time MOD(2:0) to CLK Going High tMCS 9, 10, 11 -55 ≤ TA ≤ 125 15 - ns Hold Time MOD(2:0) from CLK Going High tMCH 9, 10, 11 -55 ≤ TA ≤ 125 1 - ns Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC to CLK Going High tECS 9, 10, 11 -55 ≤ TA ≤ 125 12 - ns Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC from CLK Going High tECH 9, 10, 11 -55 ≤ TA ≤ 125 1 - ns CLK to Output Delay SIN(15:0), COS(15:0), TICO tDO 9, 10, 11 -55 ≤ TA ≤ 125 - 18 ns CLK to Output Delay DACSTRB tDSO 9, 10, 11 -55 ≤ TA ≤ 125 2 18 ns 9, 10, 11 -55 ≤ TA ≤ 125 - 12 ns Output Enable Time tOE Note 8 Note 7 NOTES: 6. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are made at 1.5V for both a Logic “1” and 0”. CLK is driven at 4.0V and 0V and measured at 2.0V. Output load per test load circuit with switch closed and CL = 40pF. 7. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF. 8. If ENOFRCTL, ENCFRACTL, ENTICTL, or ENPHREG are active, care must be taken to not violate setup and hold times to these registers when writing data into the chip via the C(15:0) port. 3 HSP45106/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS -25 (25MHz) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE (oC) MIN MAX UNITS CIN VCC = Open, f = 1MHz, all measurements are referenced to device GND. 9 TA = 25 - 10 pF Output Capacitance COUT VCC = Open, f = 1MHz, all measurements are referenced to device GND. 9 TA = 25 - 10 pF Output Disable Delay tOEZ 9, 10 -55 ≤ TA ≤ 125 - 15 ns Output Rise Time tOR From 0.8V to 2.0V 9, 10 -55 ≤ TA ≤ 125 - 8 ns Output Fall Time tOF From 20.V to 0.8V 9, 10 -55 ≤ TA ≤ 125 - 8 ns Input Capacitance NOTES: 9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with switch closed and CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D 4 HSP45106/883 Burn-In Circuit HSP45106/833 (PGA) 11 10 9 8 7 6 5 4 3 2 1 L GND SIN0 SIN1 SIN3 SIN5 SIN4 SIN9 SIN12 SIN13 SIN14 DAC STRB L K FMT VCC CLK SIN2 VCC SIN8 SIN10 GND SIN15 OES COSO K J INIPAC PAR/ SEL SIN6 SIN7 SIN11 OEC COS1 J H ENP HAC PACI COS2 COS3 H G ENTI REG INITT AC INHOF R COS6 COS4 COS5 G F ENCF REG ENPO REG ENOF REG COS7 COS8 VCC F E CS GND WR D VCC TEST C MOD2 MOD0 B MOD1 A2 A1 A PMSEL A0 GND PIN NAME COS11 COS10 COS9 E GND COS12 D INDEX PIN COS15 COS13 C B C10 C9 C6 C15 C12 C13 VCC C4 C1 TICO COS14 C14 C11 C8 C7 C5 C3 C2 C0 BURN-IN SIGNAL PGA PIN A PIN “A1” PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL A1 C0 F7 B11 MOD1 F13 A2 C2 F7 C1 COS13 V CC /2 F9 ENOFREG F8 K2 OES F14 F10 ENPOREG F4 K3 SIN15 VCC /2 A3 C3 F7 C2 COS15 V CC /2 F11 ENCFREQ F7 K4 GND GND A4 C5 F8 C5 C6 F8 G1 COS5 VCC /2 K5 SIN10 VCC /2 VCC /2 A5 C7 F8 C6 C9 F10 G2 COS4 VCC /2 K6 SIN8 A6 C8 F10 C7 C10 F10 G3 COS6 VCC /2 K7 VCC VCC A7 C11 F10 C10 MOD0 F12 G9 INHOFR F11 K8 SIN2 VCC /2 A8 C14 F11 C11 MOD2 F14 G10 INITTAC F13 K9 CLK F0 A9 GND GND D1 COS12 V CC /2 G11 ENTIREG F12 K10 VCC VCC A10 A0 F8 D2 GND GND H1 COS3 VCC /2 K11 BINFMT F6 A11 PMSEL F14 D10 TEST F14 H2 COS2 VCC /2 L1 DACSTRB VCC /2 B1 COS14 VCC /2 D11 VCC VCC H10 PACI F11 L2 SIN14 VCC /2 B2 TICO VCC /2 E1 COS9 V CC /2 H11 ENPHAC F10 L3 SIN13 VCC /2 B3 C1 F7 E2 COS10 V CC /2 J1 COS1 VCC /2 L4 SIN12 VCC /2 B4 C4 F8 E3 COS11 V CC /2 J2 OEC F14 L5 SIN9 VCC /2 B5 VCC VCC E9 WR F4 J5 SIN11 VCC /2 L6 SIN4 VCC /2 B6 C13 F11 E10 GND GND J6 SIN7 VCC /2 L7 SIN5 VCC /2 B7 C12 F11 E11 CS F6 J7 SIN6 VCC /2 L8 SIN3 VCC /2 B8 C15 F11 F1 VCC VCC J10 PAR/SER F13 L9 SIN1 VCC /2 B9 A1 F7 F2 COS8 V CC /2 J11 INITPAC F12 L10 SIN0 VCC /2 B10 A2 F10 F3 COS7 V CC /2 K1 COS0 VCC /2 L11 GND GND NOTES: 11. V CC /2 (2.7V ±10%) used for outputs only. 12. 47kΩ (±20%) resistor connected to all pins except VCC and GND. 13. V CC = 5.5V ±0.5V. 14. 0.1µF (min) capacitor between VCC and GND per position. 15. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2...., F11 = F10/2, 40% - 60% Duty Cycle. 16. Input voltage limits: VIL = 0.8V max., VIH = 4.5V ±10%. 5 HSP45106/883 Die Characteristics DIE DIMENSIONS: GLASSIVATION: 251 mils x 240 mils x 19 ±1mils METALLIZATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: Type: Si-Al, or Si-Al-Cu Thickness: 8kÅ 0.8 x 105 A/cm 2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. 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