ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL fanout HiPerClockS™ buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8533-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 4 differential 3.3V LVPECL outputs ,&6 • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS8533-01 ideal for those applications demanding well defined performance and repeatability. • Output skew: 30ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 1.4ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT D CLK_EN VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VCC Q LE CLK nCLK PCLK nPCLK CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8533-01 Q3 nQ3 8533AG-01 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VEE Power Type 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input Pullup 6 PCLK Input 7 nPCLK Input 8, 9 nc Unused Description Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK Pulldown inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. No connect. 10, 13, 18 VCC Power Positive supply pins. Connect to 3.3V. 11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical Maximum Units CLK, nCLK 4 pF PCLK, nPCLK 4 pF CLK_EN, CLK_SEL 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8533AG-01 www.icst.com/products/hiperclocks.html 2 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Source Q0 thru Q3 nQ0 thru nQ3 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Disabled Enabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0 - nQ3 Q0 - Q3 FIGURE 1 - CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK or PCLK Outputs nCLK or nPCLK Q0 thru Q3 nQ0 thru nQ3 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 8, which discusses wiring the differential input to accept single ended levels. 8533AG-01 www.icst.com/products/hiperclocks.html 3 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (0lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units 2 3.765 V -0.3 TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum CLK_EN, CLK_SEL CLK_EN, CLK_SEL Typical 0.8 V CLK_EN VIN = VCC = 3.465V 5 µA CLK_SEL VIN = VCC = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units nCLK VCC = VIN = 3.465V 5 µA CLK VCC = VIN = 3.465V 150 µA nCLK VCC = 3.465V, VIN = 0V -150 CLK VCC = 3.465V, VIN = 0V -5 VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8533AG-01 Maximum www.icst.com/products/hiperclocks.html 4 µA µA 1.3 V VCC - 0.85 V REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions PCLK Minimum Typical Maximum Units 150 µA VCC = VIN = 3.465V nPCLK VCC = VIN = 3.465V PCLK VCC = 3.465V, VIN = 0V -5 5 µA µA nPCLK VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 1 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 3 VCC - 2.0 VCC - 1.7 V 0.85 V Maximum Units 650 MHz VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency Test Conditions Minimum Typical tPD Propagation Delay; NOTE 1 1.4 ns t sk(o) Output Skew; NOTE 2, 5 30 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 5 150 ps t jit(cc) Cycle to Cycle Jitter ; NOTE 4, 5 150 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 53 % ƒ≤ 650MHz 1.0 odc Output Duty Cycle 47 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8533AG-01 www.icst.com/products/hiperclocks.html 5 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION V CC SCOPE Qx LVPECL VCC = 2.0V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT VCC CLK, PCLK V Cross Points PP V CMR nCLK, nPCLK VEE FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8533AG-01 www.icst.com/products/hiperclocks.html 6 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND OUTPUT RISE AND F FALL TIME CLK, PCLK nCLK, nPCLK Q0 - Q3 nQ0 - nQ3 t PD FIGURE 6 - PROPAGATION DELAY CLK, PCLK, Qx nCLK, nPCLK, nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 8533AG-01 www.icst.com/products/hiperclocks.html 7 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC VCC CLK_IN R1 1K R1 1K + CLK_IN + V_REF - V_REF C1 0.1uF C1 0.1uF R2 1K R2 1K FIGURE 8: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8533AG-01 www.icst.com/products/hiperclocks.html 8 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8XXX. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8XXX is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.294W * 66.6°C/W = 89.6°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8533AG-01 www.icst.com/products/hiperclocks.html 9 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) L • For logic high, VOUT = V OH_MAX Using V CC_MAX • OH_MAX OL_MAX CC_MAX – 1.0V CC_MAX = 3.465, this results in V For logic low, VOUT = V Using V =V =V CC_MAX = 2.465V – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8533AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8533-01 is: 404 8533AG-01 www.icst.com/products/hiperclocks.html 11 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 8533AG-01 www.icst.com/products/hiperclocks.html 12 REV. B JULY 16, 2001 ICS8533-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8533AG-01 ICS8533AG-01 20 lead TSSOP 72 per tube 0°C to 70°C ICS8533AG-01T ICS8533AG-01 20 lead TSSOP on Tape and Reel 2500 0°C to70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8533AG-01 www.icst.com/products/hiperclocks.html 13 REV. B JULY 16, 2001