INTERSIL ISL28117FUBZ-T13

ISL28117, ISL28217
Features
The ISL28117 and ISL28217 are a family of very high
precision amplifiers featuring low noise vs power
consumption, low offset voltage, low IBIAS current and
low temperature drift making them the ideal choice for
applications requiring both high DC accuracy and AC
performance. The combination of precision, low noise,
and small footprint provides the user with outstanding
value and flexibility relative to similar competitive parts.
• Low Input Offset . . . . . . . . . . . . . . ±50µV, Max.
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL28117 single and ISL28217 dual are offered in an
8 Ld SOIC package. Both devices are offered in standard
pin configurations and operate over the extended
temperature range to -40°C to +125°C.
Applications*(see page 23)
• Superb Offset TC . . . . . . . . . . . . 0.6µV/°C, Max.
• Input Bias Current . . . . . . . . . . . . . . ±1nA, Max.
• Input Bias Current TC . . . . . . . . . . ±5pA/°C, Max.
• Low Current Consumption . . . . . . . . . . . . . 440µA
• Voltage Noise. . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide Supply Range. . . . . . . . . . . . . . 4.5V to 40V
• Operating Temperature Range . . -40°C to +125°C
• Small Package Offerings in Single and Dual
• Pb-Free (RoHS Compliant)
Related Literature*(see page 23)
• See AN1508 “ISL281X7SOICEVAL1Z Evaluation
Board User’s Guide”
• See AN1509 “ISL282X7SOICEVAL2Z Evaluation
Board User’s Guide”
• Precision Instruments
• Medical Instrumentation
• Spectral Analysis Equipment
• Active Filter Blocks
• Thermocouples and RTD Reference Buffers
• Data Acquisition
• Power Supply Control
Typical Application
VOS Temperature Coefficient
(VOSTC)
18
C1
V+
OUTPUT
R2
R1
1.84k
+
4.93k
3.3nF
C2
V-
NUMBER OF AMPLIFIERS
8.2nF
VIN
VS = ± 15V
16
14
12
10
8
6
4
2
Sallen-Key Low Pass Filter (10kHz)
0
-0.45
-0.30 -0.15
0
0.15
0.30
0.45
VOSTC (µV/°C)
April 13, 2010
FN6632.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28117, ISL28217
40V Precision Low Power Operational Amplifiers
ISL28117, ISL28217
Ordering Information
PART NUMBER
(Notes2, 3)
PART
MARKING
VOS (MAX)
(µV)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28117FBBZ
28117 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28117FBBZ-T7 (Note 1)
28117 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28117FBBZ-T13 (Note 1)
28117 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28117FBZ
28117 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28117FBZ-T7 (Note 1)
28117 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28117FBZ-T13 (Note 1)
28117 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28117FUBZ Coming Soon
8117Z
TBD (B Grade)
8 Ld MSOP
M8.118
ISL28117FUBZ-T13 (Note 1)
Coming Soon
8117Z
TBD (B Grade)
8 Ld MSOP
M8.118
ISL28117FUZ
8117Z -C
150 (C Grade)
8 Ld MSOP
M8.118
ISL28117FUZ-T13 (Note 1)
8117Z -C
150 (C Grade)
8 Ld MSOP
M8.118
ISL28217FBBZ
28217 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28217FBBZ-T7 (Note 1)
28217 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28217FBBZ-T13 (Note 1)
28217 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
ISL28217FBZ
28217 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28217FBZ-T7 (Note 1)
28217 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28217FBZ-T13 (Note 1)
28217 FBZ -C
100 (C Grade)
8 Ld SOIC
M8.15E
ISL28117SOICEVAL1Z
Evaluation Board
ISL28217SOICEVAL2Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217. For more information on
MSL please see techbrief TB363.
Pin Configurations
ISL28217
(8 LD SOIC)
TOP VIEW
ISL28117
(8 LD SOIC, MSOP)
TOP VIEW
8
NC
VOUT_A 1
7
V+
-IN_A 2
3
6
VOUT
+IN_A 3
4
5
NC
NC
1
-IN
2
+IN
V-
-+
2
V- 4
8 V+
7 VOUT_B
- +
+ -
6 -IN_B
5 +IN_B
April 13, 2010
FN6632.4
ISL28117, ISL28217
Pin Descriptions
ISL28117
(8 LD SOIC)
ISL28217
(8 LD SOIC)
PIN NAME
EQUIVALENT CIRCUIT
Circuit 1
Amplifier A non-inverting input
3
+IN
+IN_A
4
V-
Circuit 3
Negative power supply
5
+IN_B
Circuit 1
Amplifier B non-inverting input
6
-IN_B
Circuit 1
Amplifier B inverting input
7
VOUT_B
Circuit 2
Amplifier B output
8
V+
Circuit 3
Positive power supply
VOUT
VOUT_A
Circuit 2
Amplifier A output
1
-IN
-IN_A
Circuit 1
Amplifier A inverting input
2
NC
-
3
4
7
6
2
1, 5, 8
V+
IN-
500Ω
V+
500Ω
IN+
VCIRCUIT 2
3
No internal connection
V+
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
CIRCUIT 1
DESCRIPTION
VCIRCUIT 3
April 13, 2010
FN6632.4
ISL28117, ISL28217
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . ....42V
Maximum Differential Input Current . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . 42V
Min/Max Input Voltage . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . .±20mA
Output Short-Circuit Duration (1 output at a time). . . Indefinite
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . 4.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)
8 Ld SOIC ISL28117 . . . . . . . . . .
120
60
8 Ld SOIC ISL28217 . . . . . . . . . .
105
50
8 Ld MSOP ISL28117 . . . . . . . . . .
155
50
Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VS ± 15V, VCM = 0, VO = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
Input Offset Voltage, SOIC Package ISL28x17 B Grade
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-50
8
50
µV
110
µV
100
µV
190
µV
150
µV
250
µV
-110
ISL28x17 C Grade
-100
4
-190
TCVOS
Input Offset Voltage, MSOP
Package
ISL28117 C Grade
Input Offset Voltage Temperature
Coefficient; SOIC Package
ISL28x17 B Grade
-0.6
0.14
0.6
µV/C
ISL28x17 C Grade
-0.9
0.14
0.9
µV/C
ISL28117 C Grade
-1
0.14
1
µV/C
-1
0.08
1
nA
1.5
nA
Input Offset Voltage Temperature
Coefficient; MSOP Package
IB
-150
4
-250
Input Bias Current
-1.5
TCIB
IOS
Input Bias Current Temperature
Coefficient
Input Offset Current
-5
1
5
pA/C
-1.5
0.08
1.5
nA
1.85
nA
3
pA/C
13
V
-1.85
TCIOS
VCM
CMRR
Input Offset Current Temperature
Coefficient
-3
Input Voltage Range
Guaranteed by CMRR test
-13
Common-Mode Rejection Ratio
VCM = -13V to +13V
120
0.42
145
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±20V
120
dB
145
120
AVOL
Open-Loop Gain
4
VO = -13V to +13V, RL = 10kΩ to
ground
3,000
dB
dB
dB
18,000
V/mV
April 13, 2010
FN6632.4
ISL28117, ISL28217
Electrical Specifications VS ± 15V, VCM = 0, VO = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
PARAMETER
VOH
DESCRIPTION
Output Voltage High
CONDITIONS
RL = 10kΩ to ground
MIN
(Note 6)
TYP
13.5
13.7
MAX
(Note 6)
V
13.2
RL = 2kΩ to ground
13.3
V
13.55
V
13.1
VOL
Output Voltage Low
RL = 10kΩ to ground
IS
ISC
VSUPPLY
V
-13.7
RL = 2kΩ to ground
-13.55
Supply Current/Amplifier
0.44
Short-Circuit
-13.5
V
-13.2
V
-13.3
V
-13.1
V
0.53
mA
0.68
mA
43
Supply Voltage Range
Guaranteed by PSRR
UNIT
± 2.25
mA
± 20
V
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 1k, RL = 2kΩ
enVp-p
Voltage Noise VP-P
0.1Hz to 10Hz
en
Voltage Noise Density
en
1.5
MHz
0.25
µVP-P
f = 10Hz
10
nV/√Hz
Voltage Noise Density
f = 100Hz
8.2
nV/√Hz
en
Voltage Noise Density
f = 1kHz
8
nV/√Hz
en
Voltage Noise Density
f = 10kHz
8
nV/√Hz
in
Current Noise Density
f = 1kHz
0.1
pA/√Hz
Total Harmonic Distortion
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
0.0009
%
1kHz, G = 1, VO = 3.5VRMS,
RL = 10kΩ
0.0005
%
THD + N
TRANSIENT RESPONSE
SR
tr, tf,
Small Signal
ts
tOL
Slew Rate, VOUT 20% to 80%
AV = 11, RL = 2kΩ, VO = 4VP-P
0.5
V/µs
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kΩ to VCM
100
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P, RL = 10kΩ
to VCM
120
ns
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kΩ to
VCM
21
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kΩ to
VCM
24
µs
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kΩ to
VCM
13
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kΩ to
VCM
18
µs
Output Positive Overload Recovery
Time
AV = -100, VIN = 0.2VP-P, RL = 2kΩ to
VCM
5.6
µs
Output Negative Overload
Recovery Time
AV = -100, VIN = 0.2VP-P, RL = 2kΩ to
VCM
10.6
µs
5
April 13, 2010
FN6632.4
ISL28117, ISL28217
Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by
characterization.
PARAMETER
VOS
DESCRIPTION
Input Offset Voltage; SOIC Package
CONDITIONS
ISL28x17 B Grade
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
-50
4
50
µV
110
µV
100
µV
190
µV
150
µV
250
µV
-110
ISL28x17 C Grade
-100
8
-190
Input Offset Voltage; MSOP Package
ISL28117 C Grade
-150
8
-250
TCVOS
IB
Input Offset Voltage Temperature
Coefficient; SOIC Package
ISL28x17 B Grade
-0.6
0.14
0.6
µV/C
ISL28x17 C Grade
-0.9
0.14
0.9
µV/C
Input Offset Voltage Temperature
Coefficient; MSOP Package
ISL28117 C Grade
-1
0.14
1
µV/C
-1
0.18
1
nA
1.5
nA
Input Bias Current
-1.5
TCIB
Input Bias Current Temperature
Coefficient
IOS
Input Offset Current
-5
1
5
pA/C
-1.5
0.3
1.5
nA
1.85
nA
3
pA/C
3
V
-1.85
TCIOS
VCM
CMRR
Input Offset Current Temperature
Coefficient
-3
Input Voltage Range
-3
Common-Mode Rejection Ratio
VCM = -3V to +3V
120
0.42
145
dB
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
120
dB
145
dB
120
AVOL
Open-Loop Gain
VO = -3.0V to +3.0V
RL = 10kΩ to ground
VOH
Output Voltage High
RL = 10kΩ to ground
dB
3,000
18,000
V/mV
3.5
3.7
V
3.2
RL = 2kΩ to ground
3.3
V
3.55
V
3.1
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
Supply Current/Amplifier
V
-3.7
-3.55
0.44
Short-Circuit
-3.5
V
-3.2
V
-3.3
V
-3.1
V
0.53
mA
0.68
mA
43
mA
1.5
MHz
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
6
AV = 1k, RL = 2kΩ
April 13, 2010
FN6632.4
ISL28117, ISL28217
Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by
characterization. (Continued)
PARAMETER
enp-p
DESCRIPTION
MIN
(Note 6)
CONDITIONS
Voltage Noise
0.1Hz to 10Hz
en
Voltage Noise Density
en
TYP
MAX
(Note 6)
UNIT
0.25
µVP-P
f = 10Hz
12
nV/√Hz
Voltage Noise Density
f = 100Hz
8.6
nV/√Hz
en
Voltage Noise Density
f = 1kHz
8
nV/√Hz
en
Voltage Noise Density
f = 10kHz
8
nV/√Hz
in
Current Noise Density
f = 1kHz
0.1
pA/√Hz
Slew Rate, VOUT 20% to 80%
AV=11, RL = 2kΩ, VO = 4VP-P
0.5
V/µs
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kΩ to VCM
100
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kΩ to VCM
120
ns
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kΩ to VCM
12
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kΩ to VCM
19
µs
7
µs
5.8
µs
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
tOL
Output Positive Overload Recovery Time AV = -100, VIN = 0.2VP-P
RL = 2kΩ to VCM
Output Negative Overload Recovery
Time
AV = -100, VIN = 0.2VP-P
RL = 2kΩ to VCM
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified.
140
140
VS = ±15V
VS = ±5V
120
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
120
100
80
60
40
20
0
-50
-30
-10
10
VOS (µV)
30
FIGURE 1. VOS DISTRIBUTION for GRADE B
7
50
100
80
60
40
20
0
-50
-30
-10
10
VOS (µV)
30
50
FIGURE 2. VOS DISTRIBUTION FOR GRADE B
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
300
VS = ± 15V
250
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
300
200
150
100
50
0
-100
-60
-20
20
VOS (µV)
60
200
150
100
-60
-20
20
VOS (µV)
60
100
FIGURE 4. VOS DISTRIBUTION FOR GRADE C
18
VS = ± 15V
0
-50
VS = ± 15V
16
NUMBER OF AMPLIFIERS
50
VOS (µV)
50
0
-100
100
FIGURE 3. VOS DISTRIBUTION FOR GRADE C
100
VS = ± 5V
250
14
12
10
8
6
4
2
-100
-50
0
50
100
0
150
-0.45
FIGURE 5. VOS RANGE vs TEMPERATURE
100
0
0.15
0.30
0.45
FIGURE 6. TCVOS vs NUMBER OF AMPLIFIERS
16
VS = ± 5V
VS = ±5V
NUMBER OF AMPLIFIERS
14
50
VOS (µV)
-0.30 -0.15
VOSTC (µV/°C)
TEMPERATURE (°C)
0
-50
12
10
8
6
4
2
-100
-50
0
50
TEMPERATURE (°C)
100
FIGURE 7. VOS RANGE vs TEMPERATURE
8
150
0
-0.45
-0.30 -0.15
0
0.15
VOSTC (µV/°C)
0.30
0.45
FIGURE 8. TCVOS vs NUMBER OF AMPLIFIERS
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
500
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
70
VS = ± 15V
VS = ±15V
300
200
IB+ (pA)
60
NUMBER OF AMPLIFIERS
400
100
0
-100
-200
-300
50
40
30
20
10
-400
-500
-50
0
50
100
0
150
-3.5
-2.5
-1.5
TEMPERATURE (°C)
FIGURE 9. IB+ RANGE vs TEMPERATURE
500
NUMBER OF AMPLIFIERS
IB- (pA)
200
100
0
-100
-200
-300
-400
0
50
TEMPERATURE (°C)
100
30
20
10
-3.5
-2.5
-1.5
-0.5 0.5
1.5
IB-TC (pA/°C)
NUMBER OF AMPLIFIERS
100
0
-100
-200
-300
-400
0
50
100
TEMPERATURE (°C)
FIGURE 13. IB+ RANGE vs TEMPERATURE
9
2.5
3.5
VS = ±5V
70
200
IB+ (pA)
40
80
300
-500
-50
50
FIGURE 12. TCIB- vs NUMBER OF AMPLIFIERS
VS = ± 5V
400
VS = ±15V
60
0
150
FIGURE 11. IB- RANGE vs TEMPERATURE
500
3.5 MORE
70
300
-500
-50
2.5
FIGURE 10. TCIB+ vs NUMBER OF AMPLIFIERS
VS = ± 15V
400
-0.5 0.5
1.5
IB+TC (pA/°C)
150
60
50
40
30
20
10
0
-3.5
-2.5
-1.5
-0.5
0.5
1.5
IB+TC(pA/°C)
2.5
3.5
FIGURE 14. IBTC+ vs NUMBER OF AMPLIFIERS
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
500
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
300
200
100
0
-100
-200
-300
70
60
50
40
30
20
10
-400
-500
-50
VS = ±5V
80
NUMBER OF AMPLIFIERS
400
IB- (pA)
90
VS = ± 5V
0
50
100
0
150
-3.5
-2.5
-1.5
TEMPERATURE (°C)
FIGURE 15. IB- RANGE vs TEMPERATURE
500
IOS (pA)
200
100
0
-100
-200
-300
VS = ±15V
80
70
60
50
40
30
20
10
-400
0
50
100
0
150
-3.5
-2.5
-1.5
TEMPERATURE (°C)
500
1.5
100
2.5
3.5
VS = ±5V
NUMBER OF AMPLIFIERS
90
300
200
IOS (pA)
0.5
FIGURE 18. IOSTC vs NUMBER OF AMPLIFIERS
VS = ± 5V
400
-0.5
IOSTC (pA/°C)
FIGURE 17. IOS RANGE vs TEMPERATURE
100
0
-100
-200
-300
-400
-500
-50
3.5
90
NUMBER OF AMPLIFIERS
300
-500
-50
2.5
FIGURE 16. IBTC- vs NUMBER OF AMPLIFIERS
VS = ± 15V
400
-0.5 0.5
1.5
IB-TC(pA/°C)
80
70
60
50
40
30
20
10
0
50
100
TEMPERATURE (°C)
FIGURE 19. IOS RANGE vs TEMPERATURE
10
150
0
-3.5
-2.5
-1.5
-0.5
0.5
1.5
IOSTC (pA/°C)
2.5
3.5
FIGURE 20. IOSTC vs NUMBER OF AMPLIFIERS
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
0.70
14.4
±15V
VS = ±15V
RL = 10kΩ
14.2
14.0
±2.25V
VOH (V)
Is+ (mA)
0.60
0.50
13.8
13.6
0.40
13.4
0.30
-50
0
50
TEMPERATURE (°C)
100
13.2
-50
150
50
TEMPERATURE (°C)
100
150
FIGURE 22. +VOUT vs TEMPERATURE
FIGURE 21. SUPPLY CURRENT PER AMP vs
TEMPERATURE
-140
0
-130
VS = ±2.25V TO ±20V
VCM = ±13V
-145
CMRR (dB)
PSRR (dB)
-135
-150
-140
-145
-150
-155
-155
-50
0
50
100
TEMPERATURE (°C)
150
-160
-50
0
50
TEMPERATURE (°C)
60
60
ISC- @ ±15V
55
55
50
50
ISC- (mA)
ISC+ (mA)
ISC+ @ ±15V
45
40
45
40
35
35
30
30
0
50
100
TEMPERATURE (°C)
FIGURE 25. SHORT CIRCUIT CURRENT vs
TEMPERATURE
11
150
FIGURE 24. CMRR vs TEMPERATURE
FIGURE 23. PSRR vs TEMPERATURE
25
-50
100
150
25
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 26. SHORT CIRCUIT CURRENT vs
TEMPERATURE
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
100
20000
VO = ±13V
80
VS = ±15V
+125°C
VOS (µV)
AVOL (V/mV)
60
15000
40
+25°C
20
0
-40°C
-20
-40
10000
-50
0
50
100
TEMPERATURE (°C)
-60
-15
150
-5
0
5
10
15
VCM (V)
FIGURE 28. INPUT VOS vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
FIGURE 27. AVOL vs TEMPERATURE
-13.2
100
VS = ±15V
RL = 10kΩ
VS = +5V
80
-13.4
60
+125°C
-13.6
40
20
VOL (V)
VOS (µV)
-10
+25°C
0
-13.8
-14.0
-40°C
-20
-14.2
-40
-60
-5
-3
-1
1
3
-14.4
-50
5
0
VCM (V)
FIGURE 29. VOS vs INPUT COMMON MODE VOLTAGE,
VS = ±5V
14.4
-13.2
VS = +15V
RL = 2kΩ
-13.4
14.0
-13.6
VOL (V)
VOH (V)
150
FIGURE 30. VOUT vs TEMPERATURE
VS = +15V
RL = 2kΩ
14.2
50
100
TEMPERATURE (°C)
13.8
-13.8
13.6
-14.0
13.4
-14.2
13.2
-50
0
50
100
TEMPERATURE (°C)
FIGURE 31. VOUT vs TEMPERATURE
12
150
-14.4
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 32. VOUT vs TEMPERATURE
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV)
250
200
150
100
50
0
-50
-100
-150 V+ = 36.4V
-200 Rg = 10, Rf = 100k
-250
AV = 10,000
0
1
2
3
4
5
6
7
8
9
VS = ±18.2V
AV = 1
10
1
10
1
10
100
FIGURE 33. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
OPEN LOOP GAIN (dB)/PHASE (°)
INPUT NOISE CURRENT (pA/√Hz)
VS = ±18.2V
AV = 1
10
100
1k
10k
100k
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
FIGURE 35. INPUT NOISE CURRENT SPECTRAL DENSITY
PHASE
GAIN
1
10
100
1k
10k 100k
1M 10M 100M
FIGURE 36. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL = 10kΩ, CL = 10pF
220
VS = ±2.5V
200
180
PHASE
GAIN
VS = ±5V
160
CMRR (dB)
OPEN LOOP GAIN (dB)/PHASE (°)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
10k
FIGURE 34. INPUT NOISE VOLTAGE SPECTRAL DENSITY
1
0.1
1
1k
FREQUENCY (Hz)
TIME (s)
140
120
VS = ±15V
100
80
60
40
20
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 37. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL = 10kΩ, CL = 100pF
13
0
1m
RL = INF
CL = 10pF
SIMULATION
10m 100m
1
10 100
1k 10k 100k
FREQUENCY (Hz)
1M
10M 100M
FIGURE 38. CMRR vs FREQUENCY, VS = ±2.25, ±5V,
±15V
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
120
70
110
60
100
PSRR+ AND PSRR- VS = ±2.25V
90
GAIN (dB)
PSRR (dB)
70
RL = INF
50
CL = 4pF
40
AV = +1
30
VCM = 1VP-P
20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
AV = 10
Rg = 10k, Rf = 100k
AV = 1
Rg = OPEN, Rf = 0
10k
1k
100
RL = 10k
1
0
0
-2
-1
GAIN (dB)
Rf = Rg = 10k
-4
Rf = Rg = 1k
-6
Rf = Rg = 100
-8 VS = ±20V
RL = 10k
-10
CL = 4pF
-12
AV = +2
-14 VOUT = 50mVP-P
-16
10
100
-3
-6
-7
10k
100k
1M
RL = 1k
-4
-5
1k
RL = 4.99k
-2
VS = ±20V
AV = +1
100
2
VS = ±2.5V
RL = 10k
10M
CL = 0.01µF
CL = 47pF
-2
CL = 100pF
CL = 270pF
-4
CL = 4pF
CL = 470pF
CL = 1000pF
10k
1k
100k
1M
FREQUENCY (Hz)
FIGURE 43. GAIN vs FREQUENCY vs CL
14
10M
GAIN (dB)
-1
0
100
1M
VS = ±5V
0
4
-8
10
100k
VS = ±2.25V
1
AV = +1
VOUT = 50mVP-P
-6
10k
FIGURE 42. GAIN vs FREQUENCY vs RL
12
GAIN (dB)
1k
FREQUENCY (Hz)
FIGURE 41. FREQUENCY RESPONSE vs FEEDBACK
RESISTANCE Rf/Rg
2
RL = 100
VOUT = 50mVP-P
-8
10
10M
RL = 499
CL = 4pF
FREQUENCY (Hz)
6
10M
2
Rf = Rg = 100k
2
8
1M
FIGURE 40. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
4
10
100k
FREQUENCY (Hz)
FIGURE 39. PSRR vs FREQUENCY, VS = ±5V, ±15V
NORMALIZED GAIN (dB)
20
-10
10
10M
VS = ±20V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
30
0
PSRR+ AND PSRR- VS = ±15V
10
40
10
10
-10
Rg = 1k, Rf = 100k
50
80
60
Rg = 100, Rf = 100k
AV = 1000
VS = ±15V
-2
-3
VS = ±20V
-4
-5 CL = 4pF
RL = 10k
-6
AV = +1
-7 V
OUT = 50mVP-P
-810
100
10k
1k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 44. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
April 13, 2010
FN6632.4
ISL28117, ISL28217
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
180
2.4
160
2.0
1.6
LARGE SIGNAL (V)
120
80
60
40
20
VS = ±15V
RL-Driver Ch. = Open
RL-Receiving Ch. = 10k
CL = 4pF
AV = +1
100
1k
10k
100k
FREQUENCY (Hz)
1M
CL = 4pF
AV = +1
VOUT = 4VP-P
-1.2
10
20
30
80
90
100
14
INPUT
0
12
10
-0.04
INPUT (V)
VS = ±15V
30
RL = 10k
CL = 4pF
AV = +1
VOUT = 50mVP-P
20
10
OUTPUT @ VS = ±15V
-0.08
-0.16
-0.24
0
5
10
15
20
25
TIME (µs)
30
35
40
-0.28
0
10
20
30
2
70
VS = ±15V
RL = 10k
0
60
AV = 1
VOUT = 50mVP-P
0.04
0
-2
-4
-6
-8
INPUT
OUTPUT @ VS = ±15V
-0.04
10
20
30
40
50
60
70
80
90
50
40
30
20
-10
10
-12
100
0
TIME (µs)
FIGURE 49. NEGATIVE OUTPUT OVERLOAD RESPONSE
TIME, VS = ±5V, ±15V
15
70
80
90
-2
100
O
V
ER
SH
O
O
T
0.08
0
40 50 60
TIME (µs)
O
V
ER
SH
O
O
T
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
2
+
0.20
OVERSHOOT (%)
80
OUTPUT (V)
4
0.12
4
OUTPUT @ VS= ±5V
0.24
0.16
6
FIGURE 48. POSITIVE OUTPUT OVERLOAD RESPONSE
TIME, VS = ±5V, ±15V
FIGURE 47. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
OUTPUT @ VS = ±5V
8
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-0.12
-0.20
0
0
70
0.04
40
-0.08
40 50 60
TIME (µs)
FIGURE 46. LARGE SIGNAL TRANSIENT RESPONSE vs
RL VS = ±5V, ±15V
50
SMALL SIGNAL (mV)
VS = ±5V, RL = 2k, 10k
-0.8
-2.4
0
10M
60
INPUT (V)
0
-0.4
-2.0
FIGURE 45. CROSSTALK, VS = ±15V
-10
0.4
-1.6
VSOURCE = 1VP-P
0
10
VS = ±15V, RL = 2k, 10k
0.8
OUTPUT (V)
100
1.2
-
CROSSTALK (dB)
140
1
10
100
CAPACITANCE (pF)
1k
10k
FIGURE 50. % OVERSHOOT vs LOAD CAPACITANCE,
VS = ±15V
April 13, 2010
FN6632.4
ISL28117, ISL28217
Applications Information
Functional Description
The ISL28117 and ISL28217 are single and dual, low
noise precision op amps. Both devices are fabricated in a
new precision 40V complementary bipolar DI process. A
super-beta NPN input stage with input bias current
cancellation provides low input bias current (180pA
typical), low input offset voltage (13µV typical), low input
noise voltage (8nV/√Hz), and low 1/f noise corner
frequency (~8Hz). These amplifiers also feature high
open loop gain (18kV/mV) for excellent CMRR (145dB)
and THD+N performance (0.0005% @ 3.5VRMS, 1kHz
into 2kΩ). A complimentary bipolar output stage enables
high capacitive load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V
(±2.25V) to 40V (±20V) range and are fully
characterized at 10V (±5V) and 30V (±15V). The Power
Supply Rejection Ratio typically exceeds 140dB over the
full operating voltage range and 120dB minimum over
the -40°C to +125°C temperature range. The worst case
common mode input voltage range over temperature is
2V to each rail. With ±15V supplies, CMRR performance
is typically >130dB over-temperature. The minimum
CMRR performance over the -40°C to +125°C
temperature range is >120dB for power supply voltages
from ±5V (10V) to ±15V (30V).
Input Performance
The super-beta NPN input pair provides excellent
frequency response while maintaining high input
precision. High NPN beta (>1000) reduces input bias
current while maintaining good frequency response, low
input bias current and low noise. Input bias cancellation
circuits provide additional bias current reduction to
<1nA, and excellent temperature stabilization. Figures 9
through 16 show the high degree of bias current stability
at ±5V and ±15V supplies that is maintained across the
-40°C to +125°C temperature range. The low bias
current TC also produces very low input offset current
TC, which reduces DC input offset errors in precision,
high impedance amplifiers.
The +25°C maximum input offset voltage (VOS) for the
“B” grade is 50µV and 100µV for the “C” grade. Input
offset voltage temperature coefficients (VOSTC) are a
maximum of ±0.6µV/°C for the “B” and ±0.9µV/°C for the
“C” grade. Figures 1 through 4 show the typical gaussianlike distribution over the ±5V to ±15V supply range and
over the full temperature range. The VOS temperature
behavior is smooth (Figures 5 through 8) maintaining
constant TC across the entire temperature range.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD
protection diodes to the positive and negative supply
rails, series connected 500Ω current limiting resistors
and an anti-parallel diode pair across the inputs
(Figure 51).
16
V+
- 500Ω
VIN
+ 500Ω
VOUT
RL
V-
FIGURE 51. INPUT ESD DIODE CURRENT LIMITINGUNITY GAIN
The series resistors limit the high feed-through currents
that can occur in pulse applications when the input
dV/dT exceeds the 0.5V/µs slew rate of the amplifier.
Without the series resistors, the input can forward-bias
the anti-parallel diodes causing current to flow to the
output resulting in severe distortion and possible diode
failure. Figure 46 provides an example of distortion free
large signal response using a 4VP-P input pulse with an
input rise time of <1ns. The series resistors enable the
input differential voltage to be equal to the maximum
power supply voltage (40V) without damage.
In applications where one or both amplifier input
terminals are at risk of exposure to high voltages beyond
the power supply rails, current limiting resistors may be
needed at the input terminal to limit the current through
the power supply ESD diodes to 20mA max.
Output Current Limiting
The output current is internally limited to approximately
±45mA at +25°C and can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability. Figures 25
and 26 show the current limit variation with temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28117 and ISL28217
are immune to output phase reversal, even when the
input voltage is 1V beyond the supplies.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL
(EQ. 1)
April 13, 2010
FN6632.4
ISL28117, ISL28217
where:
LICENSE STATEMENT
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of
1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
ISL28117 and ISL28217 SPICE Model
Figure 52 shows the SPICE model schematic and
Figure 53 shows the net list for the ISL28117 and
ISL28217 SPICE model for a Grade “B” part. The model
is a simplified version of the actual device and simulates
important AC and DC parameters. AC parameters
incorporated into the model are: 1/f and flatband noise,
Slew Rate, CMRR, Gain and Phase. The DC parameters
are VOS, IOS, total supply current and output voltage
swing. The model uses typical parameters given in the
“Electrical Specifications” Table beginning on page 4.
The AVOL is adjusted for 155dB with the dominate pole
at 0.02Hz. The CMRR is set (210dB, fcm = 10Hz). The
input stage models the actual device to present an
accurate AC representation. The model is configured for
ambient temperature of +25°C.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
Figures 54 through 64 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Closed Loop Gain vs RL, Large Signal
Step Response, Open Loop Gain Phase and Simulated
CMRR vs Frequency.
17
April 13, 2010
FN6632.4
ISL28117, ISL28217
.
V++
V++
R3
R4
4.45k
4.45k
4
5
CASCODE
Q4
C4
2pF
Vin-
VIN-
D1
3
SUPERB
SUPERB
DX
R1
C6
1.2pF
0.1V
7
EOS
1
IOS
Mirror
VCM
0.3nA
+
-
5E11
+
-
En
In+
VIN+
Vmid
9
IEE
200E-6
R2
290
Vc
+
-
+
-
Q3
R17
C5
2pF
8
5E11
25
5
Q1 Q2
24
D12
4
6
-
+
CASCODE
Q5
2
V5
DN
IEE1
96E-6
+
VOS
-
13E-6
V-VCM
Voltage Noise
Input Stage
V++
V++
10
+
-
4
5
D2
DX
+
V1
- 1.86V
G3
13
+
-
R5
1
D4
DX
+
V3
- 1.86V
11
G5
R7
1.99e10
Vg
12
-
R8
G4
V2
1.86V
+
+
-
+
D3
DX
+
V-VCM
R6
1
G2
1ST Gain Stage
14
-
15.9159E
17
R11
1
Vc
Vmid
Vc
Vmid
+
-
R9
2.1E3
C2
400pF
R10
2.1E3
C3
1.99e10
V4
1.86V
L1
400pF
R12
1
G6
18
VCM
D5
DX
Vg
+
-
G1
L2
15.9159E
V--
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
V++
+
-
D9
DX
G7
+
E2
22
ISY
0.44mA
Vg
D6
DX
23
V5
20
1.12V
V-
1.12V
G8
+
E3
V-
V--
D10
DY
+
G9
+
-
D11
DY
R16
90
+
-
+
VOUT
VOUT
V6
21
+
DX
-
D7
R15
90
-
+
-
D8
DX
V+
+
V+
G10
Output Stage
Supply Isolation Stage
FIGURE 52. SPICE SCHEMATIC
18
April 13, 2010
FN6632.4
ISL28117, ISL28217
* source ISL28117_SPICEmodel
* Revision B, November 20th 2009 LaFontaine
* Model for Grade B Noise, supply currents, 210dB
f=10Hz CMRR, 155dB f=0.02Hz AOL, SR = 0.5V/µsec
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28117subckt Vin+ Vin-V+ V- VOUT
* source ISL28107subckt
*
*Voltage Noise
E_En
IN+ VIN+ 25 0 1
R_R17
25 0 290
D_D12
24 25 DN
V_V7
24 0 0.1
*
*Input Stage
I_IOS
IN+ VIN- DC 0.08E-9
C_C6
IN+ VIN- 1.2E-12
R_R1
VCM VIN- 5e11
R_R2
IN+ VCM 5e11
Q_Q1
2 VIN- 1 SuperB
Q_Q2
3 8 1 SuperB
Q_Q3
V-- 1 7 Mirror
Q_Q4
4 6 2 Cascode
Q_Q5
5 6 3 Cascode
R_R3
4 V++ 4.45e3
R_R4
5 V++ 4.45e3
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
D_D1
6 7 DX
I_IEE
1 V-- DC 200e-6
I_IEE1
V++ 6 DC 96e-6
V_VOS
9 IN+ 8e-6
E_EOS
8 9 VC VMID 1
*
*1st Gain Stage
G_G1
V++ 11 4 5 8.129384e-2
G_G2
V-- 11 4 5 8.129384e-2
R_R5
11 V++ 1
R_R6
V-- 11 1
D_D2
10 V++ DX
D_D3
V-- 12 DX
V_V1
10 11 1.86
V_V2
11 12 1.86
*
*2nd Gain Stage
G_G3
V++ VG 11 VMID 2.83e-3
G_G4
V-- VG 11 VMID 2.83e-3
R_R7
VG V++ 1.99e10
R_R8
V-- VG 1.99e10
C_C2
VG V++ 4e-10
C_C3
V-- VG 4e-10
D_D4
13 V++ DX
D_D5
V-- 14 DX
V_V3
13 VG 1.86
V_V4
VG 14 1.86
*
*Mid supply Ref
R_R9
VMID V++ 2.1E3
R_R10
V-- VMID 2.1E3
I_ISY
V+ V- DC 0.44E-3
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 3.162277
G_G6
V-- VC VCM VMID 3.162277
R_R11
VC 17 1
R_R12
18 VC 1
L_L1
17 V++ 15.9159E-3
L_L2
18 V-- 15.9159E-3
*
*Output Stage with Correction Current Sources
G_G7
VOUT V++ V++ VG 1.11e-2
G_G8
V-- VOUT VG V-- 1.11e-2
G_G9
22 V-- VOUT VG 1.11e-2
G_G10
23 V-- VG VOUT 1.11e-2
D_D6
VG 20 DX
D_D7
21 VG DX
D_D8
V++ 22 DX
D_D9
V++ 23 DX
D_D10
V-- 22 DY
D_D11
V-- 23 DY
V_V5
20 VOUT 1.12
V_V6
VOUT 21 1.12
R_R15
VOUT V++ 9E1
R_R16
V-- VOUT 9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28117subckt
FIGURE 53. SPICE NET LIST
19
April 13, 2010
FN6632.4
ISL28117, ISL28217
Characterization vs Simulation Results
100
VS = ±18.2V
AV = 1
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
10
1
1
10
100
1k
FREQUENCY (Hz)
10k
1.0
1.0
100k
VS = ±20V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
AV = 10
40
20
AV = 10
0
Rg = OPEN, Rf = 0
10k
1k
100
100k
1M
AV = 1
Rg = OPEN, Rf = 0
-10
10
10M
100
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
1.0M
10M
1
RL = 10k
RL = 10k
1
0
0
-1
RL = 4.99k
-2
-3
GAIN (dB)
GAIN (dB)
1.0k
10k
100k
FREQUENCY (Hz)
FIGURE 57. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
2
RL = 1k
-4
-7
VS = ±15V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
Rg = 10k, Rf = 100k
AV = 1
-10
10
-6
100k
Rg = 100, Rf = 100k
AV = 1000
Rg = 10k, Rf = 100k
10
-5
10k
Rg = 1k, Rf = 100k
GAIN (dB)
GAIN (dB)
60
Rg = 1k, Rf = 100k
30
0
1.0k
FIGURE 55. SIMULATED INPUT NOISE VOLTAGE
Rg = 100, Rf = 100k
AV = 1000
50
20
100
70
70
40
10
FREQUENCY (Hz)
FIGURE 54. CHARACTERIZED INPUT NOISE VOLTAGE
60
10
VS = ±20V
RL = 499
-4
VS = ±15V
RL = 499
-6 AV = +1
AV = +1
1k
VOUT = 50mVP-P
RL = 100
VOUT = 50mVP-P
100
RL = 1k
-2
CL = 4pF
CL = 4pF
-8
10
RL = 4.99k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 58. CHARACTERIZED CLOSED LOOP GAIN vs
RL
20
-8
10
100
RL =100
1.0k
10k
100k
FREQUENCY (Hz)
1.0M
10M
FIGURE 59. SIMULATED CLOSED LOOP GAIN vs RL
April 13, 2010
FN6632.4
ISL28117, ISL28217
Characterization vs Simulation Results (Continued)
3
2.4
2.0
2
1.2
VS = ±15V, RL =10k
0.8
LARGE SIGNAL (V)
LARGE SIGNAL (V)
1.6
0.4
0
-0.4
-0.8
CL = 4pF
AV = +1
VOUT = 4VP-P
-1.2
-1.6
-2.0
-2.4
0
10
20
30
40 50 60
TIME (µs)
70
80
90
0
-1
-3
100
CL = 4pF
AV = +1
VOUT = 4VP-P
0
20
40
60
TIME (µs)
80
100
FIGURE 61. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
200
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
OUTPUT
1
-2
FIGURE 60. CHARACTERIZED LARGE SIGNAL
TRANSIENT RESPONSE vs RL VS = ±15V
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
INPUT
PHASE
GAIN
1
10
100
1k
10k 100k
1M 10M 100M
160
PHASE
120
80
40
GAIN
0
-40
1.0m 10m 0.1
1
FREQUENCY (Hz)
10
100 1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 62. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 63. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
250
CMRR (dB)
200
150
100
50
1m 10m 0.1
1
10 100
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 64. SIMULATED CMRR vs FREQUENCY
21
April 13, 2010
FN6632.4
ISL28117, ISL28217
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
3/18/10
FN6632.4
1. Updated “Ordering Information” on page 2 by adding two rows for MSOP packages
ISL28117FUBZ and ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout
accordingly.
2. Added POD for MSOP M8.118 to the end of datasheet
3. In “Ordering Information” on page 2, Separated each part number with it's own specific T7 and -T13 suffix and removed “Add “-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs
for MSOP Grade C package.
B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS
specs for MSOP Grade C package.
5. Added “Thermal Information” on page 4 for ISL28117 MSOP package.
3/3/10
Added “Related Literature*(see page 23)” on page 1.
Added Evaluation Boards to “Ordering Information” on page 2.
Added Theta JC values to “Thermal Information” on page 4. Added applicable Theta JC Note 5.
Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W.
1/21/10
Part marking in “Ordering Information” on page 2 changed as follows:
ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ"
ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C"
ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ"
ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C"
12/24/09
On page 7: Changed label in Figure 1 from “VS = +5V” to “VS = ±5V”
On page 7: Changed label in Figure 2 from “VS = +15V” to “VS = ±15V”
11/25/09
Changed Typical VOS spec from “13” to “8” (B Grade), “19” to “4” (C Grade), IB from “0.18”
to “0.08, IOS from “0.3” to “0.08”. Edited Spice Schematic - L1 from “95.4957” to “15.9159E”,
R1 from “6k” to 1, R9 from “1” to “2.1E3”, R10 from “1” to “2.1E3, R12 from “6k” to “1”, L2
from “95.4957” to “15.9159E”. Edited Spice Net List - Changed Revision from “A” to “B”, Date
change from “October 29th 2009” to “November 20th 2009”, added after AOL “SR =
0.5V/µsec, Input Stage changed in I_IOS from “0.3E-9” to 0.08E-9”, V_VOS “13e-6” to
“8e-6”, Mid supply Ref R_R9 and R_R10 changed “1” to “2.1E3”, Common Mode Gain Stage
with Zero change in G_G5 and G_G6 “5.27046e-15” to “3.162277”, R_R11 and R_R12 “6.3”
to “1”, L_L1 and L_L2 “95.4957” to “15.9159E-3”
11/12/09
FN6632.3
Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model
and license statement. Replaced typical application schematic on page 1.
10/16/09
FN6632.2
On page 2 “Ordering Information”, changed the following:
a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B".
Corrected part marking for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B"
B) Updated package outline drawing to most recent revision (no changes were made to
package dimensions; land pattern was added and dimensions were moved from table onto
drawing)
c) Added "Add “-T7” or “-T13” suffix for tape and reel." to the tape and reel Note 1.
d) added Note 3 callout to all parts (Note 3 reads: "For Moisture Sensitivity Level (MSL), please
see device information page for ISL28117, ISL28217. For more information on MSL please see
techbrief TB363.")
e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices
22
April 13, 2010
FN6632.4
ISL28117, ISL28217
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev. (Continued)
DATE
REVISION
CHANGE
10/08/09
FN6632.1
1. Removed “very” from “...low noise..” 1st sentence, page 1.
2. Removed “Low” from 6th bullet under features, page 1.
3. Modified typical characteristics curves to show conservative performance. Specific channel
designations removed. On temperature curves, changed formatting to indicate range from
typical value. Changes include:
a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34,
37 & 38 (all Channel A curves)
b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures
9 thru 20 (all “conservative channels”)
c. Added Figures 30, 31, 32
4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same
graphic)
5. Added temp labels to Figures 28 & 29
09/03/09
FN6632.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28117, ISL28217
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
23
April 13, 2010
FN6632.4
ISL28117, ISL28217
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
24
April 13, 2010
FN6632.4
ISL28117, ISL28217
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
25
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
April 13, 2010
FN6632.4