ISL3685 TM Data Sheet January 2001 2.4GHz RF/IF Converter and Synthesizer Features The ISL3685 is a monolithic SiGe half duplex RF/IF transceiver designed to operate in the 2.4GHz ISM band. The receive chain features a low noise, gain selectable amplifier (LNA) followed by a down-converter mixer. An up-converter mixer and a high performance preamplifier compose the transmit chain. The remaining circuitry comprises a high frequency Phase Locked Loop (PLL) synthesizer with a three wire programmable interface for local oscillator applications. • Highly Integrated File Number 4860.2 • Multiplexed RX/TX IF Path prescribes Single IF Filter • Programmable Synthesizer • Gain Selectable LNA • Power Management/Standby Mode • Single Supply 2.7V to 3.3V Operation Cascaded LNA/Mixer (High Gain) • Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25dB A reduced filter count is realized by multiplexing the receive and transmit IF paths and by sharing a common differential matching network. Furthermore, both transmit and receive RF amplifiers can be directly connected to mixers as bandwidth characteristics attenuate image frequencies. The inherent image rejection of both the transmit and receive functions allows this economic advantage. • SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7dB • Input IP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -12dBm • IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz Cascaded LNA/Mixer (Low Gain) • Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9dB The ISL3685 is housed in a 44 lead MLFP package well suited for PCMCIA board and MINI PCI applications. • Input P1dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5dBm Ordering Information Cascaded Mixer/Preamplifier PART NUMBER • Transmit Cascaded Mixer/Preamplifier Gain . . . . . . .25dB TEMP RANGE (oC) PACKAGE ISL3685IR -40 to 85 44 Ld MLFP ISL3685IR96 -40 to 85 Tape and Reel PKG. NO L44.7x7 • Output P1dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4dBm Applications RX_MX_IN RF_OUT • SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . .10dB • IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz Simplified Block Diagram H/L • IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz • IEEE802.11 1Mbps and 2Mbps Standard • Systems Targeting IEEE802.11, 11Mbps Standard • Wireless Local Area Networks RX_IN RX_MX_OUT • PCMCIA Wireless Transceivers • ISM Systems • TDMA Packet Protocol Radios CP_DO • MINI PCI Wireless Transceivers INTERFACE REF_IN PLL MODULE LO_IN TXA_OUT TX_MX_OUT TXA_IN TX_MX_IN 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2000 PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc. ISL3685 Pinout ITAT_RES1 PRE_VCC1 RX_MX_IN TX_MX_IN+ RX_MX_OUT+ PTAT_RES BIAS2_VCC1 43 42 41 40 39 38 37 36 35 34 33 ITAT_RES2 GND 44 RF_OUT COL_OUT ISL3685 (MLF) TOP VIEW RX_MX_OUT- LNA_VCC1 1 GND 2 32 TX_MX_IN- RX_IN 3 31 GND BIAS1_VCC1 4 30 RX_LO_DRIVER_VCC1 H/L 5 29 LO_VCC1 PE2 6 28 LO_IN- PE1 7 27 LO_IN+ TX_VCC1 8 26 TX_LO_DRIVER_VCC1 GND TX_MX_VCC1 11 23 TX_MX_VCC1 18 REF_BY CLK LE DATA 14 15 16 17 GND TXA_IN TX_VCC1 12 13 19 20 21 22 CP_D0 TX_MX_OUT GND CP_VCC2 24 SYN_VCC2 25 10 REF_IN 9 TXA_OUT Pin Description PIN NAME DESCRIPTION 1 LNA_VCC1 3 RX_IN 4 BIAS1_VCC1 5 H/L High or Low Gain Select, controls the LNA high and low gain modes. 6 PE2 This pin along with pin PE1 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. 7 PE1 This pin along with pin PE2 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. 8 TX_VCC1 Transmit Amplifier Positive Power Supply, requires a high quality decoupling capacitor and a short return path. 10 TXA_OUT Transmit Amplifier Output, internally matched to 50Ω, requires an external DC blocking capacitor. 12 TX_VCC1 Transmit Amplifier Positive Power Supply. 13 TXA_IN 15 LE 16 DATA 17 CLK 18 REF_BY Low Noise Amplifier Positive Power Supply. Low Noise Amplifier RF Input, internally DC coupled and requires an external blocking capacitor. A shunt capacitor to ground matches the input for return loss and optimum NF. Bias Positive Power Supply for the LNA and Preamplifier. Transmit Amplifier Input, internally AC coupled. Synthesizer Latch Enable, the serial interface is active when LE is low and the serial data is latched into defined registers on the rising edge of LE. Synthesizer Serial Data Input, clocked in on the rising edge of the serial clock, MSB first. Synthesizer Clock, DATA is clocked in on the rising edge of the serial clock, MSB first. Synthesizer Reference Frequency Input Bypass, internally DC coupled and requires an external bypass to ground when REF_IN is used as a Single Ended input, requires an external AC coupling capacitor when used as a differential input. 2 ISL3685 Pin Description (Continued) PIN NAME 19 REF_IN 20 SYN_VCC2 21 CP_VCC2 22 CP_DO 23 TX_MX_VCC1 Transmit Mixer Positive Power Supply. 24 TX_MX_OUT Transmit Mixer RF output, internal AC coupled and internally matched to 50Ω. 25 TX_MX_VCC1 Transmit Mixer Positive Power Supply. 26 TX_LO_Driver_ VCC1 Transmit LO Driver Positive Power Supply. 27 LO_IN+ Local Oscillator Positive Input, internally AC coupled, internally matched to 50Ω when the LO is driven single ended and the LO_IN- is grounded. 28 LO_IN- Local Oscillator Negative Input, internally AC coupled, differential or single ended capability, ground externally for single ended operation. 29 LO_VCC1 30 DESCRIPTION Synthesizer Reference Frequency Input, internally DC coupled and requires an external AC coupling capacitor. Synthesizer Positive Power Supply. Synthesizer Charge Pump Positive Power Supply. Synthesizer Charge Pump Output, feeds the PLL loop filter. LO Buffer Positive Power Supply. RX_LO_DRIVER Receiver LO Driver Positive Power Supply. _VCC1 32 TX_MX_IN- Transmit Mixer Negative Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. 33 RX_MX_OUT- Receive Mixer Negative Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. 34 RX_MX_OUT+ Receive Mixer Positive Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. 35 TX_MX_IN+ Transmit Mixer Positive Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. 36 RX_MX_IN Receive Mixer RF Input, internally DC coupled and requires external AC coupling as well as RF matching. The recommend network consists of a 3.3pF series capacitor followed by a small series inductance of 1.4nH and then a 1.2nH shunt inductor. The series inductance is best implemented on the PC board using a narrow transmission line inductor. 37 PRE_VCC1 PLL Prescaler Positive Power Supply. 38 ITAT_RES1 Connection to external resistor sets the receive and transmit mixers tail currents, independent of Absolute Temperature. 39 PTAT_RES Connection to external resistor sets the receive and transmit mixers tail currents, proportional of Absolute Temperature. 40 BIAS2_VCC1 41 ITAT_RES2 42 RF_OUT 44 COL_OUT All Others GND Bias Positive Power Supply for the receive and transmit mixers. Connection to external resistor sets the LNA and Preamplifier bias currents, independent of Absolute Temperature. Low Noise Amplifier RF Output, internally AC coupled and internally matched to 50Ω. LNA Collector Output, requires a bypass capacitance which is resonant with the PC board parasitics. A small resistance (20Ω) in series with the main PC board VCC bus is recommended to provide isolation from other VCC bypass capacitors. This ensures the image rejection performance of the LNA is maintained. Circuit Ground Pins (Quantity 6 each). 3 ISL3685 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Thermal Resistance (Typical, Note 1) θJA (oC/W) MLFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MLF - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Intersil TB379. General Electrical Specifications 25oC, VCC = 2.7V Unless Otherwise Specified PARAMETER MIN TYP MAX UNITS 2.7 - 3.3 V Receive Total Supply Current (LNA in High Gain) - 32 38 mA Receive Total Supply Current (LNA in Low Gain) - 25 32 mA Transmit Total Supply Current - 41 45 mA Standby Total Supply Current (PLL and LO Buffers Active) - 6.5 10 mA TX/RX Power Down Supply Current (Note 2) - - 100 µA TX/RX/Power Down Time (Note 3) - 1 10 µs RX/TX, TX/RX Switching Time (Note 3) - 0.2 1 µs CMOS Low Level Input Voltage - - 0.3*VDD V 0.7*VDD - 3.6 V -3.0 - +3.0 µA Supply Voltage CMOS High Level Input Voltage, Any VDD/VCC CMOS High or Low Level Input Current NOTES: 2. Standby current is measured after a long elapsed time (20 seconds). 3. TX/RX/TX switching time and power Down/Up time are dependent on external components. Cascaded LNA/Mixer AC Electrical Specifications PARAMETER Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC TEST CONDITIONS MIN TYP MAX UNITS RF Frequency Range 2400 - 2500 MHz IF Frequency Range 280 374 600 MHz LO Frequency Range 1800 - 2220 MHz -6 0 dBm LO Input Drive Level Single End or Differential -10 Power/Voltage Gain High Gain Mode 21.5 25 29 dB - 3.7 5.0 dB Input IP3 -17.5 -12 - dBm Input P1dB -27.5 -23 - dBm -11 -9 -1 dB Noise Figure - 25 - dB Output IM3 at -12dBm Input Tones - -58 -40 dBc Input P1dB -1 - - dBm Noise Figure SSB Power/Voltage Gain Low Gain Mode 4 ISL3685 Cascaded LNA/Mixer AC Electrical Specifications PARAMETER Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC (Continued) MIN TYP MAX UNITS High Gain Mode - - 2.0:1 - Low Gain Mode - - 2.0:1 - LO VSWR (Direct) LO = Single End - - 2.0:1 - Differential IF Output Load Shared with TX - 200 - Ω IF Output Capacitance (Single Ended) - 1.2 - pF IF Output Resistance (Single Ended) - 5.5 - kΩ LO to LNA Input Feedthrough (Cascaded, no Filter) - -65 -50 dBm LNA Input 50Ω VSWR with Match Network TEST CONDITIONS Gain Switching Speed at Full Scale - High to Low ±1dB settling - 0.03 0.1 µs Gain Switching Speed at Full Scale - Low to High ±1dB settling - 0.25 0.3 µs Image Rejection (Cascaded, No Filter) With Matching Network - 14 - dB Cascaded Transmit Mixer AC Electrical Specifications PARAMETER Assumes a direct connection between the Mixer and Preamplifier, F = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified, 25oC. MIN TYP MAX UNITS RF Frequency Range 2400 - 2500 MHz IF Frequency Range 280 374 600 MHz LO Frequency Range 1800 - 2220 MHz 21 25 29 dB - 10 15 dB Output IP3 +12 +14 - dBm Output P1dB +2.8 +4 - dBm -10 -6 0 dBm - -25 - dBm Power Conversion Gain TEST CONDITIONS 200Ω In, 50Ω Out SSB Noise Figure LO Input Drive Level Same as RX LO to Transmit Amp. Output Feedthrough (Cascaded, No Filter) - - 3.0:1 - LO 50Ω VSWR Preamplifier Output 50Ω VSWR LO = Single End - 1.4:1 2.0:1 - Differential IF Input Load Shared with RX - 200 - Ω IF Input Capacitance (Single Ended) - 1.1 - pF IF Input Resistance (Single Ended) - 0.7 - kΩ MIN TYP MAX UNITS Operating LO Frequency (32/33 Prescaler) 1800 - 2220 MHz Operating LO Frequency (64/65 Prescaler) Phase Lock Loop Electrical Specifications (See Notes 4 through 12) PARAMETER TEST CONDITIONS 1800 - 3500 MHz Reference Oscillator Frequency - - 50 MHz Selectable Prescaler Ratios (P) 32/33 - 64/65 - Swallow Counter Divide Ratio (A Counter) 0 - 127 - Programmable Counter Divide Ratio (B Counter) 3 - 2047 - Reference Counter Divide Ratio (R Counter) 3 - 32767 - 0.5 - VCC VPP Reference Oscillator Sensitivity, Single or Differential Sine Inputs 5 ISL3685 Phase Lock Loop Electrical Specifications (See Notes 4 through 12) PARAMETER (Continued) TEST CONDITIONS MIN TYP MAX UNITS - CMOS - Note 7 40 - 60 % Reference Oscillator Sensitivity, CMOS Inputs, Single Ended or Complementary Reference Oscillator Duty Cycle CMOS Inputs Charge Pump Sink/Source Current/Tolerance 250µA Selection ±25% 0.18 0.25 0.32 mA Charge Pump Sink/Source Current/Tolerance 500µA Selection ±25% 0.375 0.50 0.625 mA Charge Pump Sink/Source Current/Tolerance 750µA Selection ±25% 0.56 0.75 0.94 mA Charge Pump Sink/Source Current/Tolerance 1mA Selection ±25% 0.75 1.0 1.25 mA - - 15 % 0.5 - VCC2 -0.5 V 2.7 - 3.6 V High Level tCWH 20 - - ns Low Level tCWL 20 - - ns Serial Interface Data/Clk Set-Up Time tCS 20 - - ns Serial Interface Data/Clk Hold Time tCH 10 - - ns Serial Interface Clk/LE Set-Up Time tES 20 - - ns Serial Interface LE Pulse Width tEW 20 - - ns Charge Pump Sink/Source Mismatch Charge Pump Output Compliance Charge Pump VCC = VCC2 Charge Pump Supply Voltage Serial Interface Clock Width NOTES: 4. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is latched into defined registers on the rising edge of LE. 5. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of the power down state without requiring the registers to be rewritten. 6. CMOS Reference Oscillator input levels are given in the General Electrical Specification section. POWER ENABLE TRUTH TABLE PE1 PE2 PLL_PE (SERIAL BUS) 0 0 1 Power Down State, PLL in Save Mode, Active Serial Interface 1 1 1 Receive State 1 0 1 Transmit State 0 1 1 PLL Inactive, Inactive RX, TX, Active Serial Interface X X 0 PLL Disabled, Disabled PLL Registers, Active Serial Interface STATUS NOTE: 7. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers. PLL Synthesizer Table REGISTER DEFINITION SERIAL BITS LSB 1 2 3 R Counter 0 0 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) A/B Counter 0 1 A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) Operational Mode 1 0 M(0) 6 4 0 5 6 7 8 9 10 11 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 12 0 13 0 14 15 B(4) B(5) 0 0 16 B(6) 17 B(7) 18 19 MSB X (Don’t Care) B(8) M(13) M(14) M(15) B(9) B(10) X X ISL3685 Reference Frequency Counter/Divider BIT DESCRIPTION R(0-14) Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down by this counter and is compared with a divided LO by a phase detector. LO Frequency Counters/Dividers BIT DESCRIPTION A(0-6) Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider. The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is compared by a phase detector with the divided Reference signal. B(0-11) Operational Modes BIT DESCRIPTION M(0) (PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on. M(2) Prescaler Select. 0 = 32/33, 1 = 64/65. M(3) M(4) Charge Pump Current Setting M(5) M(6) M(7) M(8) M(13) M(14) M(15) Charge Pump Sign LD Pin Multiplex Operation Charge Pump Operation/Test 7 M(4) M(3) OUTPUT SINK/SOURCE 0 0 0.25mA 0 1 0.50mA 1 0 0.75mA 1 1 1.00mA M(6) M(5) 0 0 Source if LO/ [P*B+A] < Ref/R 0 1 Source if LO/ [P*B+A] > Ref/R M(13) M(8) M(7) 0 0 X Lock Detect Operation 0 1 X Short to GND 1 0 X Serial Register Read Back 1 1 0 Ref. Divided by R Waveform 1 1 1 LO Divided by [P*B+A] Waveform M(15) M(14) 0 0 Normal Operation 0 1 Charge Pump Constant Current Source 1 0 Charge Pump Constant Current Sink 1 1 High Impedance State OUTPUT AT PIN LD OPERATION/TEST ISL3685 DATA BIT 20: MSB BIT 19 BIT 10 BIT 9 BIT 1 BIT 1: LSB CLOCK tCWL LE tCS tCH tEW tCWH OR tES LE NOTES: 8. Parenthesis data indicates programmable reference divider data. 9. Data shifted into register on clock rising edge. 10. Data is shifted in MSB first. FIGURE 1. SERIAL DATA INPUT TIMING fR fP LD DO H I I I fR < fP fR < fP Z L fR > fP fR = fP fR < fP NOTES: 11. Phase difference detection range: -2π to +2π . 12. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. FIGURE 2. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 8 ISL3685 R11 ISL3685 Evaluation Schematic Diagram 9.53k C12 C7 .01µF R12 1.5k R13 9.53k C16 C3 0.01µF 0.01µF 7pF 20 COI I OUT GND C8 7pF LNA_OUT C14 0.01µF C2 7pF RF OUT ITAT RES2 BIAS VCC PTATA RES ITAT RES1 PRF VDD RX MX IN TX MX IN+ RX MX OUT+ R2 LNA VCC C10 C9 .01 12 13 14 15 16 17 GP3 7pF TX VCC1 PE1 U1 MLP2 44 PIN PACKAGE 100k 0 R1 R5 18 19 20 21 22 1pF PRE_OUT 33 32 31 30 29 28 27 26 25 24 23 REF BY REF IN SYN VDD CP VDD CP D0 GP2 0.01µF C1 PE2 100 1 2 3 4 5 6 7 8 9 10 11 GND RX IN BIAS VCC H/L PE2 PE1 TX VCC2 GND TXA OUT 7pF C5 100pF 100k GP1 R6 C29 R4 C4 LNA_IN TXA IN GND IF DATA CLK 100k LNA_HL 44 43 42 41 40 39 38 37 36 35 34 R3 C36 .01µF NOTES: L23 is 807 mils from edge of SMA pad to center of component pad. C26 is 381 mils from edge of U1 pin 13 to center of pad. R19 is 37 mils from edge of R17 SMA side to center of pad. PRE_IN PREIN C26 1.5pF (NO FIT) REF_IN A 0.1µF C20 1000pF 1000pF C21 1.5k (NO FIT) F4106 R10 22pF R8 0 7pF C33 0.1µF C54 + 4.7µF C53 9 0 R16 A 1 2 U6 VDD 3 ENB OUT GND 0.56µH C6 4 LOCATION = GP4 (NO FIT) L1 XTAL__VCC (NO FIT) C32 C19 1000pF ISL3685 77 x 5 MIL TRACE ISL3685 Evaluation Schematic Diagram (Continued) L23 RX_MIX_IN 1.2NH C25 C27 R36 3.3pF 0 FILTERS VALUES (10kHz DEFAULT) BW 0.01µF 330pF U4 VCC_IN BP 5 GND 2 C50 0.01µF C55 560 R17 10pF C58 1000pF R19 0.01µF 56 4 6 UPC2745TB 2 3 U3 5 A U2 10pF C47 C46 0.1µF 2 ENFVZ5F81 VCC RF 3 VCONT GROUNDS C56 10pF R34 91 1 R33 82 R35 82 4 5A 5B 5C 5D 330pF C45 1.74k 0.027µF C44 R21 2700pF 20k R25 3.48K 20k R25 C43 R20 DATA CLK 10 UP2 N/C UP1 N/C SHDN BP GND 2 5 C57 0.1µF + 4.7µF 1 C59 3 MAX8867 LE GND EXT_VCO IN 0.1µF OUT C60 0.1µF C61 + 4.7µF C62 20k 47pF R30 10k C23 10k R29 R28 10k 47pF R27 C22 U5 4 GP5 4.7µF 1 C48 SHDN D1 3 + IN MAX8867 4.7µF C51 0.1µF C52 C63 + 4.7µF (NO FIT) + OUT 0.1µF 4 C49 L10 39NH C45 TX_MIX_OUT C38 3.48k 0 TXMXO 0.01µF 0.027µF 1.5k 3.3pF LOIN C40 0.69µF R20 1.74k 220pF 0.01µF C39 0.068µF 2700pF C44 649 C37 TX_MX_VCC2 C43 R21 C34 R MX OUTTX MX INLO GND RX LO DRIVER VCC LO VCC LO INLO IN+ TX LO DRIVER VCC TX MX VCC2+ TX_MX_OUT 10kHz R9 0.01µF A 33 32 31 30 29 28 27 26 25 24 23 1kHz C31 R15 R14 L9 39NH 1.1k TI IF_IN/OUT •4 •IF IO 1.1k C17 3.3pF 220pF ISL3685 Typical Performance Curves VCC = 3.30V RF = 1.7GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK SCALE 5dB/DIV 5 5 3 1 3 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, Real = 16.7Ω, Imaginary = -31.8Ω Marker 3 = 2.45GHz, Real = 15.0Ω, Imaginary = -8.0Ω Marker 5 = 3.0GHz, Real = 16.5Ω, Imaginary = 10.5Ω Marker 1 = 1.7GHz, 7.0dB Marker 3 = 2.45GHz, 15.3dB Marker 5 = 3.0GHz, 12.5dB FIGURE 3. S11 LNA in HIGH GAIN FIGURE 4. S21 LNA in HIGH GAIN VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK SCALE 10dB/DIV 5 3 1 2 3 4 5 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, -46.4dB Marker 3 = 2.45GHz, -44.1dB Marker 5 = 3.0GHz, -35.4dB Marker 1 = 1.7GHz, Real = 8.2Ω, Imaginary = -43.5Ω Marker 3 = 2.45GHz, Real = 39.4Ω, Imaginary = 19.4Ω Marker 5 = 3.0GHz, Real = -50.6Ω, Imaginary = -45.4Ω FIGURE 5. S12 LNA in HIGH GAIN 11 FIGURE 6. S22 LNA in HIGH GAIN ISL3685 Typical Performance Curves (Continued) VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 5 SCALE 5dB/DIV 5 3 1 35 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, Real = 19.2Ω, Imaginary = -26.1Ω Marker 3 = 2.45GHz, Real = 16.7Ω, Imaginary = -2.1Ω Marker 5 = 3.0GHz, Real = 14.1Ω, Imaginary = 15.0Ω Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker 5 = 3.0GHz, -15.4dB FIGURE 7. S11 LOW GAIN LNA FIGURE 8. S21 LOW GAIN LNA VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK SCALE 5dB/DIV 5 3 3 5 1 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker 5 = 3.0GHz, -15.7dB Marker 1 = 1.7GHz, Real = 28.2Ω, Imaginary = -31.7Ω Marker 3 = 2.45GHz, Real = 32.5Ω, Imaginary = 24.2Ω Marker 5 = 3.0GHz, Real = 64.7Ω, Imaginary = -12.8Ω FIGURE 9. S12 LOW GAIN LNA 12 FIGURE 10. S22 LOW GAIN LNA ISL3685 Typical Performance Curves (Continued) VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm NO MATCH NETWORK 3 5 5 3 1 1 Marker 1 = 1.7GHz, Real = 18.6Ω, Imaginary = -84.7Ω Marker 3 = 2.45GHz, Real = 13.0Ω, Imaginary = -46.8Ω Marker 5 = 3.0GHz, Real = 8.0Ω, Imaginary = -25.3Ω Marker 1 = 1.7GHz, Real = 21.0Ω, Imaginary = -54.8Ω Marker 3 = 2.45GHz, Real = 42.1Ω, Imaginary = 6.4Ω Marker 5 = 3.0GHz, Real = 54.4Ω, Imaginary = -34.6Ω FIGURE 11. S11 RX MIXER VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm NO MATCH NETWORK FIGURE 12. S22 TX_MIX_OUT SCALE 5dB/DIV 3 5 3 1 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, Real = 7.8Ω, Imaginary = -47.0Ω Marker 3 = 2.45GHz, Real = 15.4Ω, Imaginary = 7.53Ω Marker 5 = 3.0GHz, Real = 37.9Ω, Imaginary = -12.5Ω FIGURE 13. S11 TX PREAMP 13 Marker 1 = 1.7GHz, 5.6dB Marker 3 = 2.45GHz, 15.6dB Marker 5 = 3.0GHz, 15.3dB FIGURE 14. S21 TX PREAMP 5 ISL3685 Typical Performance Curves (Continued) VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK SCALE 10dB/DIV 3 5 3 1 5 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 1 Marker 1 = 1.7GHz, -46.2dB Marker 3 = 2.45GHz, -30.7dB Marker 5 = 3.0GHz, -32.8dB Marker 1 = 1.7GHz, Real = 7.2Ω, Imaginary = -27.1Ω Marker 3 = 2.45GHz, Real = 39.5Ω, Imaginary = 2.7Ω Marker 5 = 31.8Ω, Real = 31.8Ω, Imaginary = -17.2Ω FIGURE 15. S12 TX PREAMP FIGURE 16. S22 TX PREAMP TYPICAL APPLICATION, TEMP = -40oC TYPICAL APPLICATION, TEMP = 85oC 2.7V 2.7V GAIN 1dB/DIV. 3.3V GAIN 1dB/DIV. 3.3V NF 1dB/DIV. NF 1dB/DIV. 3.3V 2.7V 3.3V 2.7V GAIN AT CURSOR 14.0dB AT 2.7V, 14.3dB AT 3.3V NOISE FIGURE AT CURSOR 3.9dB AT 2.7V, 3.73dB AT 3.3V RF 2.4GHz RF 2.5GHz FIGURE 17. LNA HIGH SETTING, GAIN AND NF 14 GAIN AT CURSOR 16.5dB AT 2.7V, 17.0dB AT 3.3V NOISE FIGURE AT CURSOR 2.64dB AT 2.7V, 2.35dB AT 3.3V RF 2.4GHz RF 2.5GHz FIGURE 18. LNA HIGH SETTING GAIN AND NF ISL3685 Typical Performance Curves (Continued) TYPICAL APPLICATION, TEMP = -40oC TYPICAL APPLICATION, TEMP = 85oC 3.3V 3.3V 2.7V GAIN 1dB/DIV. GAIN 1dB/DIV. NF 1dB/DIV. 2.7V NF 1dB/DIV. 3.3V 3.3V 2.7V 2.7V GAIN AT CURSOR -19.5dB AT 2.7V, -19.2dB AT 3.3V NOISE FIGURE AT CURSOR 20.2dB AT 2.7V, 19.4dB AT 3.3V RF 2.4GHz RF 2.5GHz FIGURE 19. LNA LOW SETTING GAIN AND NF TYPICAL APPLICATION, TEMP = 85oC GAIN AT CURSOR -18.6dB AT 2.7V, -18.0dB AT 3.3V NOISE FIGURE AT CURSOR 17.0dB AT 2.7V, 16.3dB AT 3.3V RF 2.4GHz RF 2.5GHz FIGURE 20. LNA LOW SETTING GAIN AND NF TYPICAL APPLICATION, TEMP = -40oC GAIN 5dB/DIV. GAIN 5dB/DIV. NF 5dB/DIV. 2.7V 3.3V 3.3V 2.7V GAIN AT CURSOR 7.5dB AT 2.7V, 7.7dB AT 3.3V NOISE FIGURE AT CURSOR 10.6dB AT 2.7V, 10.0dB AT 3.3V RF 2.4GHz IF 325.000MHz 2.7V NF 5dB/DIV. 3.3V RF 2.5GHz IF 425.000MHz FIGURE 21. RX MIXER GAIN AND NF 3.3V 2.7V GAIN AT CURSOR 10.0dB AT 2.7V, 10.1dB AT 3.3V NOISE FIGURE AT CURSOR 10.0dB AT 2.7V, 8.3dB AT 3.3V RF 2.4GHz IF 325.000MHz RF 2.5GHz IF 425.000MHz FIGURE 22. RX MIXER GAIN AND NF NOISE FIGURE AT CURSOR 8.1dB AT 2.7V, 8.7dB AT 3.3V TYPICAL APPLICATION, TEMP = -40oC TYPICAL APPLICATION, TEMP = 85oC 3.3V 2.7V 2.7V GAIN 1dB/DIV. 3.3V NF 1dB/DIV. GAIN 1dB/DIV. 2.7V NF 1dB/DIV. 2.7V 3.3V 3.3V GAIN AT CURSOR 7.7dB AT 2.7V, 7.8dB AT 3.3V NOISE FIGURE AT CURSOR 8.9dB AT 2.7V, 9.0dB AT 3.3V RF 0.365GHz RF 0.385GHz FIGURE 23. TX MIXER GAIN AND NF 15 GAIN AT CURSOR 10.4dB AT 2.7V, 10.9dB AT 3.3V, NOISE FIGURE AT CURSOR 8.1dB AT 2.7V, 8.7dB AT 3.3V RF 0.365GHz IF 2440.000MHz RF 0.385GHz IF 2460.000MHz FIGURE 24. TX MIXER GAIN AND NF ISL3685 Typical Performance Curves (Continued) * 0.5mA/DIV DEVICE SUPPLY CURRENT (mA) * VCC = 3.0V ROOM TEMPERATURE = AMBIENT * * * VCC = 2.7V VCC = 3.3V * -40 -30 -20 -10 0 FIGURE 25. GAIN SWITCHING SPEED AT FULL SCALE LNA LOW TO HIGH AT BASEBAND * * VCC = 2.7V VCC = 3.3V * 0 10 20 30 40 50 60 70 80 90 VCC = 2.7V VCC = 3.3V * 0 10 20 30 40 50 60 70 80 FIGURE 28. TRANSMIT TOTAL SUPPLY CURRENT * 0.2dB/DIV * * * VCC = 2.7V VCC = 3.3V * * * * VCC = 2.7V VCC = 3.3V * 10 20 30 40 50 60 70 80 * 90 TEMPERATURE DEGREES (oC) FIGURE 29. POWER/VOLTAGE GAIN HIGH GAIN MODE 16 90 TEMPERATURE DEGREES oC CASCADED LNA/MIXER IIP3 (dBm) CASCADED LNA/MIXER POWER/VOLTAGE GAIN (dB) 90 * * * 0.2dB/DIV 0 70 80 * -40 -30 -20 -10 FIGURE 27. RECEIVE TOTAL SUPPLY CURRENT (LNA IN LOW GAIN) -40 -30 -20 -10 60 * TEMPERATURE DEGREES oC * * 30 40 50 0.5mA/DIV * -40 -30 -20 -10 20 FIGURE 26. RECEIVE TOTAL SUPPLY CURRENT (LNA IN HIGH GAIN) DEVICE SUPPLY CURRENT (mA) DEVICE SUPPLY CURRENT (mA) 0.5mA/DIV * * 10 TEMPERATURE (oC) 172ns -40 -20 0 20 40 60 80 TEMPERATURE DEGREES (oC) FIGURE 30. INPUT IP3 HIGH GAIN MODE 100 ISL3685 Typical Performance Curves CASCADED LNA/MIXER POWER/VOLTAGE GAIN (dB) (Continued) * * CASCADED LNA/MIXER IP1dB (dBm) 0.1dB/DIV * * * * -40 -20 0 20 40 VCC = 2.7V VCC = 3.3V 60 80 100 CASCADED LNA/MIXER IM3 (dBc) * CASCADED LNA/MIXER IM3 (dBc) * VCC = 2.7V VCC = 3.3V 10 20 30 40 50 60 70 80 90 * * VCC = 2.7V VCC = 3.3V * 40 50 60 70 80 TEMPERATURE (oC) FIGURE 35. INPUT P1dB LOW GAIN MODE 17 90 CASCADED LNA/MIXER LO FEEDTHROUGH (dBm) CASCADED LNA/MIXER IP1dB (dBm) * 10 20 30 * 10 20 30 40 50 60 70 80 90 * * * VCC = 2.7V VCC = 3.3V * * * 0 10 20 30 40 50 60 70 80 90 FIGURE 34. RX OUTPUT IM3 AT -12dBm INPUT TONES 0.1dB/DIV 0 0 TEMPERATURE DEGREES (oC) FIGURE 33. RX OUTPUT IM3 AT -5dBm INPUT TONES -40 -30 -20 -10 VCC = 2.7V VCC = 3.3V -40 -30 -20 -10 TEMPERATURE DEGREES (oC) * * * * 1.0dB/DIV * * * FIGURE 32. POWER/VOLTAGE GAIN LOW GAIN MODE 0.5dB/DIV 0 * TEMPERATURE DEGREES (oC) FIGURE 31. INPUT P1dB HIGH GAIN MODE -40 -30 -20 -10 * -40 -30 -20 -10 TEMPERATURE DEGREES (oC) * * 0.2dB/DIV * 0.2dB/DIV * * VCC = 2.7V VCC = 3.3V * * * * -40.0 -20 0 20 40 60 TEMPERATURE DEGREES (oC) FIGURE 36. LO TO LNA INPUT FEEDTHROUGH (CASCADED, NO FILTER) 80 100 ISL3685 (Continued) 0.2dB/DIV * * * * * VCC = 2.7V VCC = 3.3V -40 -30 -20 -10 0 * 10 20 30 40 50 60 70 80 90 CASCADED TRANSMITTER/MIXER OIP3 (dBm) CASCADED TRANSMITTER/MIXER GAIN (dB) Typical Performance Curves 0.2dB/DIV * * * * * -40 -30 -20 -10 40 * * * VCC = 2.7V VCC = 3.3V 40 50 60 TEMPERATURE DEGREES (oC) FIGURE 39. OUTPUT P1dB 18 70 80 90 * * 0.2dB/DIV * * * 10 20 30 50 60 FIGURE 38. OUTPUT IP3 0.2dB/DIV 0 10 20 30 CASCADED TRANSMITTER/ MIXER LO FEEDTHROUGH (dBm) CASCADED TRANSMITTER/MIXER OP1dB (dBm) FIGURE 37. POWER CONVERSION GAIN -40 -30 -20 -10 0 TEMPERATURE DEGREES (oC) TEMPERATURE DEGREES (oC) * * * VCC = 2.7V VCC = 3.3V 70 * 80 90 -40 -20 0 20 40 VCC = 2.7V VCC = 3.3V 60 80 100 TEMPERATURE DEGREES (oC) FIGURE 40. LO TO TRANSMIT AMP OUTPUT FEEDTHROUGH (CASCADED, NO FILTER) ISL3685 Micro Lead Frame Plastic Package (MLFP) L44.7x7 2X 0.25 C A D A 44 LEAD MICRO LEAD FRAME PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VKKD-1 ISSUE A) D/2 INCHES D1 SYMBOL D1/2 2X N 6 0.50 DIA. 0.25 C B 1 2 3 E1/2 E/2 E1 2X B 0.20 C A TOP VIEW 2X 0 A2 A 0.05 C SEATING PLANE A3 SIDE VIEW 5 b 4X P 0.10 M C A B 7 D2 D2/2 0.039 - 1.00 0.002 - 0.05 A2 - 0.031 - A3 0.008 REF 4X P 1 (Ne-1)Xe REF. E2 7 E2/2 L e (Nd-1)Xe REF. BOTTOM VIEW C C A1 C L 5 C L b 0.007 0.012 0.265 BSC D2 - 0.130 0.80 0.20 REF 0.18 0.275 BSC D1 0.30 6.75 BSC - 3.30 E 0.275 BSC 7.00 BSC 0.265 BSC 6.75 BSC E2 - - 0.019 BSC 0.019 0.029 5 7.00 BSC E1 0.130 NOTES 3.30 7 7 0.50 BSC 0.50 0.75 N 44 44 2 Nd 11 11 3 Ne 11 11 3 P 0.009 0.024 0.24 0.60 θ - 12 - 12 Rev. 1 8/00 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd is the number of terminals in the X direction, and Ne is the number of terminals in the Y direction. 4. Controlling dimension: Millimeters. Converted dimensions to inches are not necessarily exact. Angles are in degrees. 5. Dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip. 6. The Pin #1 identifier exists on the top surface as an indentation mark in the molded body. 7. Dimensions D2 and E2 are the maximum exposed pad dimensions for improved grounding and thermal performance. N 2 3 MAX - L A1 MIN - e C MILLIMETERS A D 0.20 C B MAX A1 b E MIN SECTION "C-C" e e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 19